CN107910405B - A kind of production method of light-emitting diode chip for backlight unit - Google Patents
A kind of production method of light-emitting diode chip for backlight unit Download PDFInfo
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- CN107910405B CN107910405B CN201710890555.1A CN201710890555A CN107910405B CN 107910405 B CN107910405 B CN 107910405B CN 201710890555 A CN201710890555 A CN 201710890555A CN 107910405 B CN107910405 B CN 107910405B
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- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
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- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses a kind of production methods of light-emitting diode chip for backlight unit, belong to technical field of semiconductors.It include: that several mutually independent chips are formed on the substrate, each chip includes n type semiconductor layer, luminescent layer, p type semiconductor layer, P-type electrode and N-type electrode, n type semiconductor layer, luminescent layer, p type semiconductor layer stack gradually on substrate, each chip is equipped with the groove that n type semiconductor layer is extended to from p type semiconductor layer, N-type electrode is arranged on the n type semiconductor layer in groove, P-type electrode is arranged on p type semiconductor layer, and the isolation channel that substrate is extended to from n type semiconductor layer is equipped between two neighboring chip；Protective film is formed in isolation channel, protective film is arranged on the substrate in isolation channel, and the material of protective film uses metal or metal oxide；The P-type electrode of each chip and N-type electrode are adhered on glue film respectively；Substrate is removed using laser lift-off technique；Remove protective film.The present invention can avoid damage from laser glue film.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of production method of light-emitting diode chip for backlight unit.
Background technique
Light emitting diode (English: Light Emitting Diode, referred to as: LED) it is that one kind can be converted to electric energy
The semiconductor diode of luminous energy has the characteristics that small in size, brightness is high and energy consumption is small, is widely used in display screen, backlight
Source and lighting area.
Chip is the core component of LED, the production method of existing LED chip include: sequentially form on substrate buffer layer,
N type semiconductor layer, luminescent layer and p type semiconductor layer；The groove for extending to n type semiconductor layer is opened up on p type semiconductor layer,
The isolation channel for extending to substrate is formed on n type semiconductor layer in groove；N-type electricity is formed on n type semiconductor layer in groove
Pole forms P-type electrode on p type semiconductor layer；P-type electrode and N-type electrode are adhered on glue film；Using laser lift-off technique
Substrate is removed, several mutually independent LED chips are formed.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
When using laser lift-off technique removal substrate, laser is along the formation direction directive substrate of LED chip, wherein directive
The laser of isolation channel can reach glue film and burnt glue film, cause glue film not can be removed clean or chip and be damaged, LED chip
Production failure.
Summary of the invention
In order to solve the problems, such as prior art glue film by laser it is burnt cause LED chip production failure, the embodiment of the present invention
Provide a kind of production method of light-emitting diode chip for backlight unit.The technical solution is as follows:
The embodiment of the invention provides a kind of production method of light-emitting diode chip for backlight unit, the production method includes:
Several mutually independent chips are formed on the substrate, each chip includes n type semiconductor layer, luminescent layer, p-type
Semiconductor layer, P-type electrode and N-type electrode, the n type semiconductor layer, the luminescent layer, the p type semiconductor layer stack gradually
Over the substrate, each chip is equipped with the groove that the n type semiconductor layer is extended to from the p type semiconductor layer,
On the n type semiconductor layer of the N-type electrode setting in the groove, the P-type electrode is arranged in the p type semiconductor layer
On, the isolation channel that the substrate is extended to from the n type semiconductor layer is equipped between the two neighboring chip；
Protective film is formed in the isolation channel, the protective film is arranged on the substrate in the isolation channel, institute
The material of protective film is stated using metal or metal oxide；
The P-type electrode of each chip and N-type electrode are adhered on glue film respectively；
The substrate is removed using laser lift-off technique；
Remove the protective film.
Optionally, the protective film is additionally arranged on the side wall of the n type semiconductor layer in the isolation channel.
Optionally, the protective film with a thickness of 1nm~5000nm.
It is optionally, described to form protective film in the isolation channel, comprising:
Negative photoresist is formed using photoetching technique on the chip；
Metal film or metal oxide film are laid in the negative photoresist and the isolation channel；
The negative photoresist is removed, the protective film is formed.
Preferably, described that metal film or metal oxide film, packet are laid in the negative photoresist and the isolation channel
It includes:
Metal film or metal oxide film are laid in the negative photoresist and the isolation channel using sputtering technology.
Optionally, the glue film includes polyvinyl chloride substrate and acrylic system sticker.
Preferably, the removal protective film, comprising:
Concentration is used to remove the protective film for 3%~15% hydrochloric acid.
It is optionally, described that several mutually independent chips are formed on the substrate, comprising:
Using metallo-organic compound chemical gaseous phase deposition technology on substrate successively grow n type semiconductor layer, luminescent layer,
P type semiconductor layer；
The photoresist of the first figure is formed on the p type semiconductor layer using photoetching technique；
Under the protection of the photoresist of first figure, dry method is carried out to the p type semiconductor layer and the luminescent layer
Etching forms the groove that the n type semiconductor layer is extended to from the p type semiconductor layer；
Remove the photoresist of first figure；
Second graph is formed on the n type semiconductor layer in the p type semiconductor layer and the groove using photoetching technique
Photoresist；
Under the protection of the photoresist of the second graph, dry etching is carried out to the n type semiconductor layer, is formed from institute
State the isolation channel that n type semiconductor layer extends to the substrate；
Remove the photoresist of the second graph；
Using photoetching technique in the n type semiconductor layer and the isolation channel in the p type semiconductor layer, the groove
The photoresist of third figure is formed on substrate；
Metal layer is laid on the photoresist, the p type semiconductor layer and the n type semiconductor layer of the third figure；
The photoresist of the third figure is removed, the metal layer on the p type semiconductor layer forms P-type electrode, the N-type
Metal layer on semiconductor layer forms N-type electrode.
Preferably, each chip further includes transparency conducting layer, and the transparency conducting layer is that setting is partly led in the p-type
Indium oxide tin film on body layer；
It is described that several mutually independent chips are formed on the substrate, further includes:
In the n type semiconductor layer using photoetching technique in the p type semiconductor layer, the groove and the isolation
It is formed on substrate in slot before the photoresist of third figure, the N-type semiconductor in the p type semiconductor layer, the groove
Indium oxide tin film is laid on substrate in layer and the isolation channel；
The photoresist of the 4th figure is formed on the indium oxide tin film using photoetching technique；
Under the protection of the photoresist of the 4th figure, wet etching is carried out to the indium oxide tin film, described in formation
Transparency conducting layer；
Remove the photoresist of the 4th figure；
It anneals to the transparency conducting layer.
It is highly preferred that each chip further includes passivation layer, the passivation layer is that setting removes the P on the chip
The silicon dioxide layer in the region except on the substrate in type electrode, the N-type electrode and the isolation channel；
It is described that several mutually independent chips are formed on the substrate, further includes:
After the photoresist of the removal third figure, it is laid with silicon dioxide layer on the chip；
The photoresist of the 5th figure is formed in the silicon dioxide layer using photoetching technique；
Under the protection of the photoresist of the 5th figure, wet etching is carried out to the silicon dioxide layer, described in formation
Passivation layer；
Remove the photoresist of the 5th figure.
Technical solution provided in an embodiment of the present invention has the benefit that
By forming metal film or metal oxide film on the substrate in advance in isolation channel as protective film, then using sharp
Photospallation technology removes substrate, and when formation direction directive substrate of the laser along chip, wherein the major part of directive isolation channel swashs
Light can be absorbed by protective film and can not reach glue film, therefore can carry out next step processing to avoid glue film by damage from laser, complete
The production of LED chip.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of flow chart of the production method of light-emitting diode chip for backlight unit provided in an embodiment of the present invention；
Fig. 2 a- Fig. 2 j is the structural schematic diagram of chip in manufacturing process provided in an embodiment of the present invention；
Fig. 3 is curve graph of the indium oxide tin film provided in an embodiment of the present invention to the light transmittance of different wave length light.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Embodiment
The embodiment of the invention provides a kind of production methods of light-emitting diode chip for backlight unit, are particularly suitable for miniature light-emitting diodes
The production of pipe (English: Micro LED) chip.Referring to Fig. 1, which includes:
Step 101: several mutually independent chips are formed on the substrate, each chip includes n type semiconductor layer, shines
Layer, p type semiconductor layer, P-type electrode and N-type electrode, n type semiconductor layer, luminescent layer, p type semiconductor layer are sequentially laminated on substrate
On, each chip is equipped with the groove that n type semiconductor layer is extended to from p type semiconductor layer, and the N in groove is arranged in N-type electrode
In type semiconductor layer, P-type electrode is arranged on p type semiconductor layer, is equipped between two neighboring chip from n type semiconductor layer and extends
To the isolation channel of substrate.
Specifically, which may include:
The first step, using metallo-organic compound chemical gaseous phase deposition technology (English: Metal Organic Chemical
Vapor Deposition, referred to as: MOCVD) n type semiconductor layer, luminescent layer, p type semiconductor layer are successively grown on substrate.
Fig. 2 a is the structural schematic diagram of chip after the first step executes.Wherein, 11 be substrate, and 12 be n type semiconductor layer, 13
It is p type semiconductor layer for luminescent layer, 14.As shown in Figure 2 a, n type semiconductor layer 12, luminescent layer 13, p type semiconductor layer 14 be successively
It is layered on substrate 11.
In the concrete realization, high-purity hydrogen (H can be used2) or high pure nitrogen (N2) or high-purity H2And high-purity N2
Mixed gas as carrier gas, high-purity ammonia (NH3) it is used as nitrogen source, trimethyl gallium (TMGa) and triethyl-gallium (TEGa) are used as gallium
Source, trimethyl indium (TMIn) are used as indium source, and trimethyl aluminium (TMAl) is used as silicon source, and silane (SiH4) is used as N type dopant, two cyclopentadienyls
Magnesium (CP2Mg) it is used as P-type dopant.Chamber pressure is controlled in 100~600torr.
Specifically, substrate can be Sapphire Substrate, and n type semiconductor layer can be the gallium nitride layer of n-type doping, p-type half
Conductor layer can be the gallium nitride layer of p-type doping；Luminescent layer may include multiple quantum well layers and multiple quantum barrier layers, Duo Geliang
Sub- well layer and the alternately laminated setting of multiple quantum barrier layers, quantum well layer are indium gallium nitrogen layer, and quantum barrier layer is gallium nitride layer.
In practical applications, each chip can also include the buffer layer being layered between substrate and n type semiconductor layer, with
Alleviate the lattice mismatch between sapphire and gallium nitride material.Specifically, buffer layer can be gallium nitride layer or aln layer.
Correspondingly, in the first step, using MOCVD on substrate successively grown buffer layer, n type semiconductor layer, luminescent layer,
P type semiconductor layer.
Second step forms the photoresist of the first figure using photoetching technique on p type semiconductor layer.
In practical applications, when forming the photoresist of certain figure, it can be first laid with a layer photoresist, then in mask plate
Block it is lower photoresist is exposed, finally by after exposure photoresist impregnate in developer solution, part photoresist is dissolved in aobvious
In shadow liquid, the photoresist of required figure is left.
Third step carries out dry etching to p type semiconductor layer and luminescent layer under the protection of the photoresist of the first figure,
Form the groove that n type semiconductor layer is extended to from p type semiconductor layer.
In the concrete realization, can using inductively coupled plasma body (English: Inductive Coupled Plasma,
Referred to as: ICP) technology carries out dry etching to p type semiconductor layer and luminescent layer.
4th step removes the photoresist of the first figure.
In the present embodiment, second step to the 4th step is used to form groove, wherein the photoresist overlay of the first figure is in P
Region in type semiconductor layer in addition to groove position, so that dry etching does not have the p type semiconductor layer of photoresist overlay
Groove is formed with luminescent layer.
Fig. 2 b is the structural schematic diagram of chip after the 4th step executes.Wherein, 21 be groove.As shown in Figure 2 b, groove 21
N type semiconductor layer 12 is extended to from p type semiconductor layer 14.
Specifically, the depth of groove is equal to the sum of p type semiconductor layer and the thickness of luminescent layer.More specifically, the depth of groove
Degree can be 1 μm~1.5 μm.
5th step forms second graph using photoetching technique on the n type semiconductor layer in p type semiconductor layer and groove
Photoresist.
Implementing step can be similar with second step, the difference is that only that the shape of the mask plate of use is different, because
And the figure of the photoresist formed is different.
6th step carries out dry etching to n type semiconductor layer, is formed from N-type under the protection of the photoresist of second graph
Semiconductor layer extends to the isolation channel of substrate.
In the concrete realization, dry etching can be carried out to n type semiconductor layer using ICP technology.
7th step removes the photoresist of second graph.
In the present embodiment, the 5th step to the 7th step is used to form isolation channel, wherein the photoresist overlay of second graph exists
Region on p type semiconductor layer and n type semiconductor layer in addition to isolation channel position, so that dry etching does not have photoresist to cover
The n type semiconductor layer of lid forms isolation channel.
Fig. 2 c is the structural schematic diagram of chip after the 7th step executes.Wherein, 22 be isolation channel.As shown in Figure 2 c, it is isolated
Slot 22 extends to substrate 11 from n type semiconductor layer 12.
Specifically, the sum of depth of isolation channel and groove is equal to the thickness of p type semiconductor layer, luminescent layer and n type semiconductor layer
The sum of degree.More specifically, the sum of depth of isolation channel and groove can be 5 μm~10 μm.
Optionally, each chip can also include transparency conducting layer, and transparency conducting layer is to be arranged on p type semiconductor layer
Tin indium oxide (English: Indium Tin Oxide, referred to as: ITO) film, so as to the electric current of P-type electrode extending transversely injection.
Correspondingly, which can also include:
Before the 8th step, it is laid on the substrate in the n type semiconductor layer and isolation channel in p type semiconductor layer, groove
Indium oxide tin film；
The photoresist of the 4th figure is formed on indium oxide tin film using photoetching technique；
Under the protection of the photoresist of the 4th figure, wet etching is carried out to indium oxide tin film, forms transparency conducting layer；
Remove the photoresist of the 4th figure；
It anneals to transparency conducting layer.
In the present embodiment, position of the photoresist overlay of the 4th figure on p type semiconductor layer where transparency conducting layer,
The indium oxide tin film in other regions to remove, the transparency conducting layer of shape needed for being formed.In addition, being moved back to transparency conducting layer
Fire can make to form Ohmic contact between transparency conducting layer and p type semiconductor layer.
Fig. 2 d is the structural schematic diagram of chip after above-mentioned steps execute.Wherein, 15 be transparency conducting layer.Such as Fig. 2 d institute
Show, transparency conducting layer 15 is arranged on p type semiconductor layer.
Specifically, the thickness of transparency conducting layer can be 20nm~200nm.
8th step, using substrate of the photoetching technique in the n type semiconductor layer and isolation channel in p type semiconductor layer, groove
The upper photoresist for forming third figure.
Implementing step can be similar with second step, the difference is that only that the shape of the mask plate of use is different, because
And the figure of the photoresist formed is different.
9th step is laid with metal layer on the photoresist, p type semiconductor layer and n type semiconductor layer of third figure.
Tenth step removes the photoresist of third figure, and the metal layer on p type semiconductor layer forms P-type electrode, and N-type is partly led
Metal layer on body layer forms N-type electrode.
In the present embodiment, the 8th step to the tenth step is used to form electrode, wherein the photoresist overlay of third figure is in P
Except before N-type electrode position on region and n type semiconductor layer in type semiconductor layer in addition to P-type electrode position
Metal layer on the photoresist of third figure is removed together, is left when so as to the subsequent photoresist for removing third figure by region
P-type electrode and N-type electrode.
Fig. 2 e is the structural schematic diagram of chip after the tenth step executes.Wherein, 16 be P-type electrode, and 17 be N-type electrode.Such as
Shown in Fig. 2 e, P-type electrode 16 is arranged on p type semiconductor layer 14, and N-type electrode 17 is arranged on n type semiconductor layer 12.
Optionally, the thickness of N-type electrode can be equal to the sum of the thickness from P-type electrode, p type semiconductor layer and luminescent layer,
So that on subsequent removal substrate, N-type electrode can be adhered on glue film together with P-type electrode, the fastness of adherency and steady is improved
It is qualitative.
Optionally, each chip can also include passivation layer, and passivation layer includes being arranged on chip except P-type electrode, N-type electricity
The silicon dioxide layer in the region except on the substrate in pole and isolation channel is protected with being formed to chip, avoids damage to and leak
Electricity.
Correspondingly, which can also include:
After the tenth step, silicon dioxide layer is laid on chip；
The photoresist of the 5th figure is formed in silicon dioxide layer using photoetching technique；
Under the protection of the photoresist of the 5th figure, wet etching is carried out to silicon dioxide layer, forms passivation layer；
Remove the photoresist of the 5th figure.
In the present embodiment, position of the photoresist overlay of the 5th figure on chip where passivation layer, to remove its
The silicon dioxide layer in its region, the passivation layer of shape needed for being formed.
Fig. 2 f is the structural schematic diagram of chip after above-mentioned steps execute.Wherein, 18 be passivation layer.As shown in figure 2f, blunt
Change layer 18 and is covered on all areas on chip in addition to P-type electrode 16 and N-type electrode 17, including transparency conducting layer 15, p-type half
Conductor layer 14, the side wall of groove 21, n type semiconductor layer 12, the side wall of isolation channel 22 and substrate 11.
Step 102: protective film is formed in isolation channel, protective film is arranged on the substrate in isolation channel, protective film
Material use metal or metal oxide.
Fig. 2 g is the structural schematic diagram of chip after step 102 executes.Wherein, 23 be protective film.As shown in Figure 2 g, it protects
Film 23 is arranged in isolation channel 22.
Specifically, when the material of protective film uses metal, the material of protective film specifically can be using aluminium (Al), gold
(Au), one of silver-colored (Ag), nickel (Ni), platinum (Pt) and titanium (Ti) simple substance or at least two alloy；When the material of protective film
When using metal oxide, the material of protective film specifically can be using tin indium oxide (English: Indium Tin Oxides, abbreviation
ITO), ZnO transparent conductive glass (GZO), indium gallium zinc oxygen that the ZnO transparent conductive glass (AZO), gallium of aluminium doping adulterate
One of compound (English: Indium Gallium Zinc Oxide, abbreviation IGZO), ZnO.
In the present embodiment, the material of protective film uses ITO.
Optionally, protective film can also be arranged on the side wall of the n type semiconductor layer in isolation channel, and laser is avoided to reach
Chip is damaged during glue film, prevents chip from failing due to damage.
It should be noted that the front of chip is not no protective film, in case chip leaks electricity.Wherein, the front of chip is
Finger-type at p type semiconductor layer etc. surface.
Optionally, the thickness of protective film can be 1nm~5000nm.If the thickness of protective film is less than 1nm, can not protect
Glue film；If the thickness of protective film is greater than 5000nm, it will cause the wastes of material.
Optionally, which may include:
Negative photoresist is formed on chip using photoetching technique；
Metal film or metal oxide film are laid in negative photoresist and isolation channel；
Negative photoresist is removed, protective film is formed.
Part metals film or metal oxide film are removed using above-mentioned lift-off technology, remove part gold with using lithographic technique
Belong to film or metal oxide film is compared, chip (the especially side wall of groove) can be caused to damage to avoid in etching process.
Preferably, it is laid with metal film or metal oxide film in negative photoresist and isolation channel, may include:
Metal film or metal oxide film are laid in negative photoresist and isolation channel using sputtering technology.
It should be noted that the metal oxide film that do not anneal, such as indium oxide tin film, are very easy to by acid molten
Corrosion, usually can be corroded within several seconds completely, therefore the present embodiment after protective film is formed without annealing, so as to
It is subsequent easily to remove protective film, the removal rate of protective film is improved 5 times.
Step 103: the P-type electrode of each chip and N-type electrode are adhered on glue film respectively.
Fig. 2 h is the structural schematic diagram of chip after step 103 executes.Wherein, 24 be glue film.As shown in fig. 2h, glue film 24
It is adhered in the P-type electrode 16 and N-type electrode 17 of chip.
Specifically, glue film may include polyvinyl chloride substrate and acrylic system sticker, i.e. described blue film in the industry, material
It is convenient to obtain, and cost of implementation is low.
Step 104: substrate is removed using laser lift-off technique.
Fig. 2 i is the structural schematic diagram of chip after step 104 executes.As shown in fig. 2i, substrate 11 has been removed.
In the concrete realization, by laser action in buffer layer, gallium nitride is decomposed using laser energy and sapphire has a common boundary
The buffer layer at place, so that Sapphire Substrate be separated from gallium nitride material.
Fig. 3 is curve graph of the indium oxide tin film to the light transmittance of the light of different wave length.As shown in figure 3, being in wavelength
In the range of 300nm~800nm, wavelength is shorter, and indium oxide tin film is lower to the transmitance of light, i.e., absorptivity is higher, and mesh
The wavelength of laser used by preceding removal substrate is 255nm, therefore most of laser can be absorbed (almost in indium oxide tin film
100%).And the laser energy of this wavelength is big, can efficiently separate substrate.
The present invention, which passes through, forms metal film or metal oxide film as protective film on the substrate in isolation channel in advance, then
Substrate is removed using laser lift-off technique, when formation direction directive substrate of the laser along chip, wherein directive isolation channel is big
Fraction of laser light can be absorbed by protective film and can not reach glue film, therefore to avoid glue film by damage from laser can add in next step
Work completes the production of LED chip.
Step 105: removal protective film.
Fig. 2 j is the structural schematic diagram of chip after step 105 executes.As shown in figure 2j, protective film 23 has been removed.
As previously mentioned, the metal oxide film (such as indium oxide tin film) that do not anneal is very easy to by acid solution corruption
Erosion can usually be corroded completely for several seconds, while acid solution does not act on glue film, therefore can be very using acid solution
Easily remove protective film.
Optionally, which may include:
Concentration is used to remove protective film for 3%~15% hydrochloric acid.
On the one hand using the etchant solution generally sold in the market, procurement cost is low；It on the other hand can be molten to avoid corroding
Damage of the liquid to other layers.
Preferably, the temperature of hydrochloric acid can be 25 DEG C~60 DEG C, easy to accomplish using room temperature.
In practical applications, after the step 105, it can be dried with chip, chip is fixed on substrate, form formal dress
Chip；Alternatively, first by adhesive die attachment on another glue film, then chip is fixed on substrate, forms flip-chip.In addition,
Before chip is fixed on substrate, expansion film can be carried out to glue film, to adjust the distance between adjacent chips.
The embodiment of the present invention, which passes through, forms indium oxide tin film as protective film on the substrate in isolation channel in advance, then uses
Laser lift-off technique removes substrate, when formation direction directive substrate of the laser along chip, the wherein major part of directive isolation channel
Laser can be absorbed by the indium oxide tin film as protective film and can not reach glue film, thus can to avoid glue film by damage from laser,
Next step processing is carried out, the production of LED chip is completed.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (9)
1. a kind of production method of light-emitting diode chip for backlight unit, which is characterized in that the production method includes:
It is formed on the substrate several mutually independent chips, each chip includes that n type semiconductor layer, luminescent layer, p-type are partly led
Body layer, P-type electrode and N-type electrode, the n type semiconductor layer, the luminescent layer, the p type semiconductor layer are sequentially laminated on institute
It states on substrate, each chip is equipped with the groove that the n type semiconductor layer is extended to from the p type semiconductor layer, the N
On the n type semiconductor layer of type electrode setting in the groove, the P-type electrode is arranged on the p type semiconductor layer, adjacent
The isolation channel that the substrate is extended to from the n type semiconductor layer is equipped between two chips；
Protective film is formed in the isolation channel, the protective film is arranged on the substrate in the isolation channel, the guarantor
The material of cuticula use metal or metal oxide, the protective film with a thickness of 1nm~5000nm；
The P-type electrode of each chip and N-type electrode are adhered on glue film respectively；
The substrate is removed using laser lift-off technique；
Remove the protective film.
2. manufacturing method according to claim 1, which is characterized in that the protective film is additionally arranged in the isolation channel
On the side wall of n type semiconductor layer.
3. production method according to claim 1 or 2, which is characterized in that it is described to form protective film in the isolation channel,
Include:
Negative photoresist is formed using photoetching technique on the chip；
Metal film or metal oxide film are laid in the negative photoresist and the isolation channel；
The negative photoresist is removed, the protective film is formed.
4. production method according to claim 3, which is characterized in that described in the negative photoresist and the isolation channel
Interior laying metal film or metal oxide film, comprising:
Metal film or metal oxide film are laid in the negative photoresist and the isolation channel using sputtering technology.
5. production method according to claim 1 or 2, which is characterized in that the glue film includes polyvinyl chloride substrate and Asia
Gram force system sticker.
6. production method according to claim 5, which is characterized in that the removal protective film, comprising:
Concentration is used to remove the protective film for 3%~15% hydrochloric acid.
7. production method according to claim 1 or 2, which is characterized in that it is described be formed on the substrate it is several mutually indepedent
Chip, comprising:
N type semiconductor layer, luminescent layer, p-type are successively grown using metallo-organic compound chemical gaseous phase deposition technology on substrate
Semiconductor layer；
The photoresist of the first figure is formed on the p type semiconductor layer using photoetching technique；
Under the protection of the photoresist of first figure, dry etching is carried out to the p type semiconductor layer and the luminescent layer,
Form the groove that the n type semiconductor layer is extended to from the p type semiconductor layer；
Remove the photoresist of first figure；
The light of second graph is formed on the n type semiconductor layer in the p type semiconductor layer and the groove using photoetching technique
Photoresist；
Under the protection of the photoresist of the second graph, dry etching is carried out to the n type semiconductor layer, is formed from the N
Type semiconductor layer extends to the isolation channel of the substrate；
Remove the photoresist of the second graph；
Using substrate of the photoetching technique in the n type semiconductor layer and the isolation channel in the p type semiconductor layer, the groove
The upper photoresist for forming third figure；
Metal layer is laid on the photoresist, the p type semiconductor layer and the n type semiconductor layer of the third figure；
The photoresist of the third figure is removed, the metal layer on the p type semiconductor layer forms P-type electrode, and the N-type is partly led
Metal layer on body layer forms N-type electrode.
8. production method according to claim 7, which is characterized in that each chip further includes transparency conducting layer, institute
Stating transparency conducting layer is the indium oxide tin film being arranged on the p type semiconductor layer；
It is described that several mutually independent chips are formed on the substrate, further includes:
It is described using photoetching technique in the n type semiconductor layer and the isolation channel in the p type semiconductor layer, the groove
Substrate on formed before the photoresist of third figure, n type semiconductor layer in the p type semiconductor layer, the groove and
Indium oxide tin film is laid on substrate in the isolation channel；
The photoresist of the 4th figure is formed on the indium oxide tin film using photoetching technique；
Under the protection of the photoresist of the 4th figure, wet etching is carried out to the indium oxide tin film, is formed described transparent
Conductive layer；
Remove the photoresist of the 4th figure；
It anneals to the transparency conducting layer.
9. production method according to claim 8, which is characterized in that each chip further includes passivation layer, described blunt
Changing layer is to be arranged on the chip in addition on the substrate in the P-type electrode, the N-type electrode and the isolation channel
Region silicon dioxide layer；
It is described that several mutually independent chips are formed on the substrate, further includes:
After the photoresist of the removal third figure, it is laid with silicon dioxide layer on the chip；
The photoresist of the 5th figure is formed in the silicon dioxide layer using photoetching technique；
Under the protection of the photoresist of the 5th figure, wet etching is carried out to the silicon dioxide layer, forms the passivation
Layer；
Remove the photoresist of the 5th figure.
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| CN112713167B (en) * | 2019-10-25 | 2023-05-19 | 成都辰显光电有限公司 | Display panel and preparation method thereof |
| CN110838503A (en) * | 2019-11-20 | 2020-02-25 | 广东省半导体产业技术研究院 | Manufacturing method of micro LED chip, manufacturing method of micro LED display device and micro LED display device |
| CN112968082B (en) * | 2020-10-13 | 2022-04-19 | 重庆康佳光电技术研究院有限公司 | Manufacturing method of light-emitting device structure, display back plate and display device |
| CN112582515B (en) * | 2020-12-11 | 2021-09-28 | 苏州芯聚半导体有限公司 | Light emitting diode and manufacturing method thereof |
| CN113437185A (en) * | 2021-06-23 | 2021-09-24 | 南方科技大学 | Method and system for efficiently preparing Micro-LED chip |
| CN113539127B (en) * | 2021-07-09 | 2023-04-11 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
| CN114122202B (en) * | 2021-11-11 | 2023-05-16 | 重庆康佳光电技术研究院有限公司 | Chip and preparation method thereof |
| CN115613011A (en) * | 2022-09-01 | 2023-01-17 | 福建兆元光电有限公司 | SiO for improving rear electrode 2 Exfoliated chemical vapor deposition method |
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| CN101099223A (en) * | 2005-01-11 | 2008-01-02 | 美商旭明国际股份有限公司 | Light emitting diode with conducting metal substrate |
| CN102171845A (en) * | 2008-10-06 | 2011-08-31 | 奥斯兰姆奥普托半导体有限责任公司 | Method for producing an optoelectronic semiconductor component and optoelectronic semiconductor component |
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| CN101099223A (en) * | 2005-01-11 | 2008-01-02 | 美商旭明国际股份有限公司 | Light emitting diode with conducting metal substrate |
| CN102171845A (en) * | 2008-10-06 | 2011-08-31 | 奥斯兰姆奥普托半导体有限责任公司 | Method for producing an optoelectronic semiconductor component and optoelectronic semiconductor component |
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