CN107908897A - A kind of differentiation priority polling system based on FPGA - Google Patents
A kind of differentiation priority polling system based on FPGA Download PDFInfo
- Publication number
- CN107908897A CN107908897A CN201711261425.8A CN201711261425A CN107908897A CN 107908897 A CN107908897 A CN 107908897A CN 201711261425 A CN201711261425 A CN 201711261425A CN 107908897 A CN107908897 A CN 107908897A
- Authority
- CN
- China
- Prior art keywords
- website
- information
- fpga
- service
- information block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004069 differentiation Effects 0.000 title claims abstract description 16
- 238000009826 distribution Methods 0.000 claims abstract description 22
- 238000004891 communication Methods 0.000 claims abstract description 10
- 230000005540 biological transmission Effects 0.000 claims abstract description 6
- 238000005516 engineering process Methods 0.000 claims abstract description 6
- 238000012546 transfer Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 20
- 230000015654 memory Effects 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 13
- 238000003860 storage Methods 0.000 claims description 12
- 238000013461 design Methods 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 claims description 4
- 238000007781 pre-processing Methods 0.000 claims description 4
- 230000033228 biological regulation Effects 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 3
- 230000003111 delayed effect Effects 0.000 claims description 3
- 238000001914 filtration Methods 0.000 claims description 3
- 238000011084 recovery Methods 0.000 claims description 3
- 230000002123 temporal effect Effects 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims description 2
- 238000013507 mapping Methods 0.000 claims description 2
- 238000000465 moulding Methods 0.000 claims 1
- 238000003825 pressing Methods 0.000 claims 1
- 238000012795 verification Methods 0.000 abstract 1
- 241000854291 Dianthus carthusianorum Species 0.000 description 4
- 230000004927 fusion Effects 0.000 description 4
- 230000002776 aggregation Effects 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 235000008331 Pinus X rigitaeda Nutrition 0.000 description 1
- 235000011613 Pinus brutia Nutrition 0.000 description 1
- 241000018646 Pinus brutia Species 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 235000003642 hunger Nutrition 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000005039 memory span Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008521 reorganization Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer And Data Communications (AREA)
Abstract
The present invention relates to a kind of differentiation priority polling system based on FPGA, belongs to network communication of wireless sensor field.By MATLAB instruments, the raw information packet for obeying Poisson distribution is dexterously produced using frequency splitting technology for the system；Using the transfer of Verilog HDL language state of a control machines, the control to system service order is realized, realize the mixed scheduling to high priority website full service in system, common website gated polling system；Cached, sent using the soft verification station information of asynchronous FIFO built in FPGA, have effectively achieved each site information and be grouped into up to the speeds match with transmission process.Server priority carries out central station point full service, provides gated polling system to common website, so that central site business has preferable delay character, the business of common website is taken into account again at the same time, phase is effectively prevent in system to stop or the problem of frequent switching, control is flexible, can be widely applied to distinguish in priority, the multiservice system more demanding to delay character.
Description
Technical field
The present invention relates to a kind of differentiation priority polling system based on FPGA, belongs to network communication of wireless sensor field.
Background technology
Wireless sensor network as a kind of restructural infrastructure, have it is general, flexible, can safeguard, self-organizing, can learn
The characteristics such as habit, are widely used in the fields such as agricultural, industry, military affairs, and polling system is because of its fairness, flexibility, high efficiency, reality
It is widely used in characteristics such as property, high quality-of-services in wireless sensor network.Wireless sensor network is by micro sensing
The multi-hop ad hoc Task network system with data center that device node is made up of communication, itself belongs to point
Cloth system, sensor node form some cluster regional structures by dynamic reorganization, effectively avoid Single Point of Faliure, maintainable
By force, system survivability energy is improved, automatic forwarding detection data carry out data to aggregation node (cluster head node), aggregation node
It is wirelessly transmitted to after fusion by internet or satellite etc. up to management node, management node is according to certain data algorithm
Effectively configure and manage.Controlled by factors such as geographical conditions, how to reduce energy expenditure, maximize system life week
Phase becomes design challenges.Cluster head communicates with ordinary node coordinates (PCF) polling dispatching strategy based on point, and cluster head node passes through foundation
Inquiry sends ordinary node data message to polling list polling table successively in order, effectively prevent in common multiple access protocol different nodes at the same time
Use energy loss caused by channel.
Different systems has different quality of service requirement, to consider in design cluster zone distance, optimization path,
The factors such as network cycle, fault-tolerance dispose multi-service application, in cluster communication polling mechanism using which kind of service strategy (point completely,
Thresholding, limit three kinds of service strategies) become the key that performance optimizes.Polling system with exhaustive service queue length is minimum, time delay is special
Property it is best, can utilize very well in the more demanding operation system of real-time performance, its deficiency is to handle high concurrent data letter
During breath, system can rest on a certain phase for a long time, cause other website hunger phenomenons.Limit (K=1) Service Polling System
Delay character and control flexibility are worst, but fairness is best.The delay character of gated polling system polling system, fairness are placed in the middle,
It can be applicable to the not high single type operation system of characteristic requirements.In practical applications, in face of the diversified service of polymorphic type business
Demand, the difference in view of different server process performance, single service strategy cannot meet multiservice system well
Control requirement, the differentiations priority blended service polling system of flexibility higher becomes the hot spot of design, as influence system
The key of performance.
The content of the invention
Present invention aims at for different business it is different to quality of service requirement the problem of, propose it is a kind of based on FPGA,
Distinguish priority and blended service, differentiation priority polling system based on FPGA are carried out to site information.
Further object of the present invention is a kind of method for introducing intelligent screening, storing effective information, solves information arrival
Speeds match problem between system service.
Another object of the present invention is to provide a kind of so that the information block that each website produces obeys and specifies arrival rate Poisson
The solution of distribution.
Differentiation priority polling system of the invention based on FPGA is completed in the following manner：Distinguish priority poll
System is made of a central site and N number of common website two-stage, and server priority services central station point, works as central station
Point information is sent as common website information block is directly inquired about, sent during sky, and ormal station is pressed after the completion of sight limit rule service
Then continue inquiry, service centre's website and next common website by certain conversion time；
Comprise the concrete steps that：Whole priority polling system of distinguishing is divided into information source module, website mould using schematic diagram method
Four block, control module and receiving module parts, wherein information source module produce the raw information packet for obeying Poisson distribution；Website
Module is responsible for pre-processing the information block that information source module collects, stores, sends；Control module is whole system service
Control centre, by the channel right to use and service time that service order decision website is assigned to each common website；Receiving module
For correctly recovering the information block of each website from the bus data of system.
Present invention information source module part first, which will produce, obeys the information block with the Poisson distribution for specifying arrival rate, profit
Poisson distribution sequence document is produced with MATLAB instruments, the txt documents of generation are converted into what the soft core RAM of FPGA can be read
Mif files, RAM reads document data after address decoding, its data read represents the one clock production of FPGA sequence circuits
Raw how many a information blocks；
Next real-time storage is carried out to the information block that information source module produces, the information block that unit time slot produces contains
Size is 0 invalid information, reduces amount of redundancy to improve communication efficiency, website module section sets a wave filter, passes through ratio
Output effective information is relatively crossed, and the soft core write enable signals of FIFO built in control are effective, so as to fulfill information source module effective information point
The real-time storage of group；
Whether the memory of server Help Center's website first is empty, and the information block transmission to non-NULL central site is
The service signal of next common website is put 1 at once after sky, that is, realizes that 0 time of central site to common website changes；When being
First common website, loop cycle are returned again after system last complete common website of poll services；System is received in website
Service order when, corresponding FIFO reads that enable signal is effective, and stored information block is in the case where reading clock control according to elder generation
It is transferred to successively on system bus to the order first gone out.
It is finally the recovery that receiving module carries out each station data information using the service enable signal of control module, by
Controlled in each website to bus transfer data information by the service signal of control module, so suitable with same control in receiving terminal
Sequential signal can correctly recover the data message of each website as synchronization fifo write enable signal from bus data.
The service regulation of the central site is：After often having serviced a common website, server turns by what is set
Change whether time inquiring central site has information block to be sent, the central site continuous service for obtaining Service Privileges is deposited to it
For sky, i.e., the information block reached in service process will be also transmitted the information block of storage.
The service regulation of described N number of common website is：Server is according to certain rule in order 1,2 ..., and N is to ormal station
Point is inquired about, serviced, and common website 1 is returned after having serviced common website N；Common website to obtaining service power, system is only
Website stored information block when obtaining the authority moment is sent, i.e., the information block of the website is reached in service process certainly
Turn services for next time.
Default turn need to be passed through when server transfers Help Center's website by common website in the present system course of work
Change the time, and require system to be turned by common website without time delays, this operating characteristic when central site turns to common website
To the Parallel Scheduling that completed during central site to central site and common website working status, can be deposited according to two websites
The capacity status of reservoir makes correct decisions, is serviced for it if central site memory non-NULL, otherwise directly services
Common website.
The information block that the present invention reaches each website should meet Markov property, obey with the pool for specifying arrival rate
Pine distribution.Each website arrival information block need to be pre-processed first stores transmission afterwards, this process removes redundancy usually through filtering.
The central site information block no-delay information block for sending next common website after having sent, basis
FIFO built in FPGA exports empty, the full state that signal correctly judges the memory, it is contemplated that wruse signals and empty signals it
Between temporal characteristics, utilize the two signals carry out comprehensive descision；If wruse signals are not 0 when inquiring about website FIFO,
Empty signals are 1, illustrate FIFO for sky；If wruse signals are that 0, empty signals are 0 in service process, illustrate website at this time
FIFO information is sky, this is because FIFO memory spacing wave empty itself, which can be delayed one, reads clock output.
The document sequence for obeying the Poisson distribution for specifying arrival rate is fully produced in present invention design by MATLAB instruments
And the original text that FPGA built-in RAMs can be read is converted it to, number is read by FPGA built-in RAMs after address decoding circuitry
According to.When carrying out Mapping and Converting according to data, solve the problems, such as that single time slot produces multiple information blocks using frequency splitting technology, so that
Poisson distribution data are produced, and meet requirement when FIFO stores data to settling time.
The information block that each website of the present invention produces screens out invalid information by a comparator, and controls FPGA's with this
FIFO memory write enable signal real-time storage effective information.
Brief description of the drawings
Fig. 1 is the overall framework figure of the present invention.
Fig. 2 is the website module frame figure of the present invention.
Fig. 3 is the control module state transition diagram of the present invention.
Embodiment
The embodiment of the system is illustrated with reference to the operation principle of the present invention.
The present invention combines the secondary design again that Verilog HDL hardware description languages realize FPGA with principle drawing method, flexibly
The scheduling mode of polling system is controlled, control server is according to central site full service, the strategy of common website gated polling system
Each site information is transmitted, control system, which often services a common website, will access whether central site needs to take again
Business, so that the service quality of central site is guaranteed.
One simple polling procedure can be expressed as each site information packet arrival process, information block service process with
And adjacent sites poll transfer process, main because of the invention realize that content is：Whole system is divided into using schematic diagram method
Four information source module, website module, control module, receiving module parts.
Information source module produces the raw information packet for obeying Poisson distribution, and website module locates raw information packet in advance
Reason, that is, filter, the effective information after processing cached, and control module simulation cluster head node realizes single-hop communication in cluster, control
Make each node and send data using channel uncontestedly, receiving module correctly recovers the bus data after fusion.
Information source module combination MATLAB instruments core soft with FPGA built-in RAMs produces can not be real in hardware time order circuit
The raw information packet of existing, the specified arrival rate of obedience Poisson distribution.Pool is produced by MATLAB instrument calling systems function
Loose distribution document sequence, and the .mif files that FPGA built-in RAMs can be read are converted it to, using frequency splitting technology in single time slot
Produce with generating the corresponding n information block of document sequence, so that the information block that information source module sequence circuit produces
Meet Poisson distribution characteristic, on this basis with reference to certain time delay technology so that system meets that FIFO stores data when working
When requirement to settling time, control is flexible.
The website module is responsible for pre-processing the information block that information source module collects, stores, sends.It is actual
In work, the arrival rate of each site information of polling system is more many soon than the service speed of server, the storage of website module
Device will can overcome both speeds match problems, and the present invention realizes storage by the asynchronous FIFO memory built in FPGA and reads
The doubleclocking independent control of process is taken, solves this problem well.In wireless sensor network, what sensor collected
Data message has larger redundancy, it is necessary to by pre-processing compressed data, reduces data capacity.The present invention is by filtering skill
Art goes the invalid information that divider value is 0, and control FIFO write enable signals only store effective information, reads to enable after being connected to service order
Signal is effective, in the sequential delivery that the effective information stored first goes out according to arriving first to system bus, improves system communication effect
Rate.
The control module is the control centre of system service, and website is determined by assigning service order to each website
The channel right to use and service time.Server is often completed just parallel by corresponding conversion time after the service of a common website
The memory span information of Help Center's website and next common website, its information block bedding and clothing when central site has demand for services
Business device is preferentially sent, and is turned at once after ensuring that all data messages of central site are sent as sky and is serviced next common website；
If central site data are sky, server directly services next common website.During controlling herein, system will be according in FPGA
Put FIFO output terminal wruse signals and empty signals correctly judge empty, the full state of the memory, so that correct control system
Service order and service time；
The receiving module is used for the information block that each website is correctly recovered from the bus data of system, described
The uncontested channel right to use of enjoying of each website of polling system sends data, data fusion is realized by OR circuit, after fusion
The sequencing of each site information of data immobilizes with transmission time, as long as therefore making in the same control signal of receiving terminal
Synchronizing FIFO storages for write enable signal just can realize that the correct of each site information recovers.
Information source module part, which will produce, first obeys the information block with the Poisson distribution for specifying arrival rate, utilizes
MATLAB instruments produce Poisson distribution sequence document, and the txt documents of generation are converted into the mif that the soft core RAM of FPGA can read
File, RAM reads document data after address decoding, and it is more that its data read represents that one clock of FPGA sequence circuits produces
Few information block.
Poisson distribution arrival rate value is 0.1 in design, and information block is produced in a time slot and is up to 3, therefore right in designing
Reference clock signal carries out 4 frequency dividings enough, and unit time slot produces the information block of corresponding number by counting principle after frequency dividing, full
Sufficient Poisson distribution characteristic.
Next real-time storage is carried out to the information block that information source module produces, the information block that unit time slot produces contains
Size is 0 invalid information, reduces amount of redundancy to improve communication efficiency, website module section sets a wave filter, passes through ratio
Output effective information is relatively crossed, and the soft core write enable signals of FIFO built in control are effective, so as to fulfill information source module effective information point
The real-time storage of group.
Whether the memory of server Help Center's website first is empty, (to export signal just by FIFO according to built in FPGA
Really judge empty, the full state of the memory, it is contemplated that the temporal characteristics between wruse signals and empty signals, utilize the two
Signal carries out comprehensive descision；If wruse signals are not that 0, empty signals are 1 when inquiring about website FIFO, illustrate FIFO for sky；
If wruse signals are that 0, empty signals are 0 in service process, illustrate that website FIFO information is sky at this time, this is because FIFO is deposited
Reservoir spacing wave empty itself, which can be delayed one, reads clock output), the information block of non-NULL central site is sent to be vertical after sky
Carve and the service signal of next common website is put 1, that is, realize that 0 time of central site to common website changes.
After one clock, software section realizes that state shifts, and needs to distinguish the working status of currently common website at this time, if
Site capacity is shown as empty at this time, then previous clock is equivalent to conversion time, system want at this time Parallel Scheduling central site and
The memory state of next common website；If site capacity non-NULL at this time, previous clock is service time, when the website module
From being kept to 0, (when the station services signal is effective, counter reads the wruse signal numerical value of website FIFO, this value to counter
Represent the information block number that the website should be sent according to thresholding rule, as soon as often sending an information block afterwards, counter is certainly
Subtract 1), that is, after having sent the commonly information block at website acquisition sending permission moment, currently common station services Signal Fail, clothes
Business device parallel query central site and next common site information after conversion time.
Control method is same as described above.Return to first again after last complete common website of system poll services commonly
Website, loop cycle.
When website receives the service order of system, corresponding FIFO reads effective, the stored information of enable signal
The order for reading according to arriving first first to go out under clock control is grouped in be transferred on system bus successively.
Due to single-hop communication between each website, Service Privileges are enjoyed successively, are not conflicted mutually, therefore pass through 4 input OR circuits
The fused data of each website can be obtained.
It is finally the recovery that receiving module carries out each station data information using the service enable signal of control module, by
Controlled in each website to bus transfer data information by the service signal of control module, so suitable with same control in receiving terminal
Sequential signal can correctly recover the data message of each website as synchronization fifo write enable signal from bus data.
Claims (9)
1. a kind of differentiation priority polling system based on FPGA, it is characterised in that distinguish priority polling system by a center
Website is formed with N number of common website two-stage, and server priority services central station point, when central site information is sent as sky
When directly inquire about, send common website information block, ormal station then turns after the completion of pressing sight limit rule service by certain
Change the time and continue inquiry, service centre's website and next common website；
Comprise the concrete steps that：Whole priority polling system of distinguishing is divided into information source module, website module, control using schematic diagram method
Four parts of molding block and receiving module, wherein information source module produce the raw information packet for obeying Poisson distribution；Website module
It is responsible for pre-processing the information block that information source module collects, storing, sending；Control module is whole system Service controll
Center, by the channel right to use and service time that service order decision website is assigned to each common website；Receiving module is used for
The information block of each website is correctly recovered from the bus data of system.
2. the differentiation priority polling system according to claim 1 based on FPGA, it is characterised in that information source module first
Part, which will produce, obeys the information block with the Poisson distribution for specifying arrival rate, and Poisson distribution sequence is produced using MATLAB instruments
Row document, is converted into the mif files that the soft core RAM of FPGA can read, RAM is read after address decoding by the txt documents of generation
Document data, its data read represent that one clock of FPGA sequence circuits produces how many a information blocks；
Next real-time storage is carried out to the information block that information source module produces, the information block that unit time slot produces contains size
For 0 invalid information, reduce amount of redundancy to improve communication efficiency, website module section sets a wave filter, by comparing
Effective information is exported, and the soft core write enable signals of FIFO built in control are effective, so as to fulfill the packet of information source module effective information
Real-time storage；
Whether the memory of server Help Center's website first is empty, and the information block of non-NULL central site is sent as after sky
The service signal of next common website is put 1 at once, that is, realizes that 0 time of central site to common website changes；When system wheel
Inquiry returns to first common website, loop cycle again after having serviced last common website；The clothes of system are received in website
During business instruction, corresponding FIFO reads that enable signal is effective, and stored information block is in the case where reading clock control according to arriving first elder generation
The order gone out is transferred on system bus successively；
It is finally the recovery that receiving module carries out each station data information using the service enable signal of control module, due to each
Website is controlled to bus transfer data information by the service signal of control module, so believing in the same control sequence of receiving terminal
The data message of each website number can be correctly recovered from bus data as synchronization fifo write enable signal.
3. the differentiation priority polling system according to claim 1 based on FPGA, it is characterised in that the clothes of central site
Business rule be：After often having serviced a common website, whether server needs by the conversion time Help Center website set
Information block is sent, the information block stored to the central site continuous service for obtaining Service Privileges to it is sky, that is, is being serviced
During the information block that reaches also to be transmitted.
4. the differentiation priority polling system according to claim 1 based on FPGA, it is characterised in that N number of common website
Service regulation is：Server is according to certain rule in order 1,2 ..., and N inquires about ormal station point, is serviced, and has serviced ormal station
Common website 1 is returned after point N；Common website to obtaining service power, system only send website when obtaining the authority moment and have deposited
The information block of storage, i.e., the information block that the website is reached in service process switch to next service automatically.
5. the differentiation priority polling system according to claim 1 based on FPGA, it is characterised in that system work process
Middle server need to pass through default conversion time when transferring Help Center's website by common website, and be turned in central site common
Without time delays during website, this operating characteristic requires system by be completed to central site during common website turning center website
With the Parallel Scheduling of common website working status, correct decisions can be made according to the capacity status of two website memories,
Serviced for it if central site memory non-NULL, otherwise directly service common website.
6. the differentiation priority polling system according to claim 1 based on FPGA, it is characterised in that reach each website
Information block should meet Markov property, obey and reach information block with the Poisson distribution for specifying arrival rate, each website
It need to first be pre-processed and store transmission afterwards, this process removes redundancy usually through filtering.
7. the differentiation priority polling system based on FPGA according to claim 1 or 5, it is characterised in that central site is believed
Cease packet transmission it is complete after the no-delay information block for sending next common website, the FIFO according to built in FPGA to export signal correct
Judge empty, the full state of the memory, it is contemplated that the temporal characteristics between wruse signals and empty signals, utilize the two letters
Number carry out comprehensive descision；If wruse signals are not that 0, empty signals are 1 when inquiring about website FIFO, illustrate FIFO for sky；Clothes
If wruse signals are that 0, empty signals are 0 during business, illustrate that website FIFO information is sky at this time, this is because FIFO is stored
Device spacing wave empty itself, which can be delayed one, reads clock output.
8. the differentiation priority polling system according to claim 6 based on FPGA, it is characterised in that fully borrowed in design
Help that MATLAB instruments produce the document sequence for obeying the Poisson distribution for specifying arrival rate and to convert it to FPGA built-in RAMs readable
The original text taken, data are read after address decoding circuitry by FPGA built-in RAMs, and Mapping and Converting is being carried out according to data
When, solve the problems, such as that single time slot produces multiple information blocks using frequency splitting technology, so as to produce Poisson distribution data, and meet
Requirement when FIFO stores data to settling time.
9. the differentiation priority polling system according to claim 6 based on FPGA, it is characterised in that what each website produced
Information block screens out invalid information by a comparator, and controls the FIFO memory write enable signal of FPGA to deposit in real time with this
Store up effective information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711261425.8A CN107908897A (en) | 2017-12-04 | 2017-12-04 | A kind of differentiation priority polling system based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711261425.8A CN107908897A (en) | 2017-12-04 | 2017-12-04 | A kind of differentiation priority polling system based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107908897A true CN107908897A (en) | 2018-04-13 |
Family
ID=61854216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711261425.8A Pending CN107908897A (en) | 2017-12-04 | 2017-12-04 | A kind of differentiation priority polling system based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107908897A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109819457A (en) * | 2019-01-25 | 2019-05-28 | 云南大学 | Two-stage thresholding polling system based on FPGA |
| CN110222002A (en) * | 2019-06-17 | 2019-09-10 | 青岛依爱通信设备有限公司 | A kind of display parameter of display screen poll acquisition method and system based on RS485 serial communication |
| CN110296501A (en) * | 2019-07-11 | 2019-10-01 | 珠海格力电器股份有限公司 | A kind of centralized management system and method for air-conditioning system |
| CN111372213A (en) * | 2020-02-24 | 2020-07-03 | 云南大学 | Two-layer system of random multiple access and polling multiple access protocol based on FPGA |
| CN111431648A (en) * | 2020-04-13 | 2020-07-17 | 云南大学 | Access control communication protocol design method and system based on double-layer polling |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106060955A (en) * | 2016-05-17 | 2016-10-26 | 杨志军 | Method and system for controlling wireless sensor network MAC protocol polling based on three types of services |
| CN106993306A (en) * | 2017-02-16 | 2017-07-28 | 云南大学 | Wireless network MAC layer distributed coordination system and its construction method based on FPGA |
| CN107347201A (en) * | 2017-07-07 | 2017-11-14 | 云南大学 | A kind of wireless sensor network polling system control method based on priority |
-
2017
- 2017-12-04 CN CN201711261425.8A patent/CN107908897A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106060955A (en) * | 2016-05-17 | 2016-10-26 | 杨志军 | Method and system for controlling wireless sensor network MAC protocol polling based on three types of services |
| CN106993306A (en) * | 2017-02-16 | 2017-07-28 | 云南大学 | Wireless network MAC layer distributed coordination system and its construction method based on FPGA |
| CN107347201A (en) * | 2017-07-07 | 2017-11-14 | 云南大学 | A kind of wireless sensor network polling system control method based on priority |
Non-Patent Citations (2)
| Title |
|---|
| 任杰: "无线传感器网络优先级轮询控制策略研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 刘龙军 等: "基于FPGA WSN轮询接入控制协议的研究", 《通信学报》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109819457A (en) * | 2019-01-25 | 2019-05-28 | 云南大学 | Two-stage thresholding polling system based on FPGA |
| CN110222002A (en) * | 2019-06-17 | 2019-09-10 | 青岛依爱通信设备有限公司 | A kind of display parameter of display screen poll acquisition method and system based on RS485 serial communication |
| CN110296501A (en) * | 2019-07-11 | 2019-10-01 | 珠海格力电器股份有限公司 | A kind of centralized management system and method for air-conditioning system |
| CN110296501B (en) * | 2019-07-11 | 2021-04-02 | 珠海格力电器股份有限公司 | Centralized management and control system and method for air conditioning system |
| CN111372213A (en) * | 2020-02-24 | 2020-07-03 | 云南大学 | Two-layer system of random multiple access and polling multiple access protocol based on FPGA |
| CN111372213B (en) * | 2020-02-24 | 2021-08-31 | 云南大学 | Two-layer system of random multiple access and polling multiple access protocol based on FPGA |
| CN111431648A (en) * | 2020-04-13 | 2020-07-17 | 云南大学 | Access control communication protocol design method and system based on double-layer polling |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107908897A (en) | A kind of differentiation priority polling system based on FPGA | |
| CN110113242A (en) | Multi-node synchronization sampling and data transmission method in ring-type communication network | |
| CN101001209B (en) | System for switching variable-length data packets of heterogeneous network and method thereof and method for forming address list using signal loop interface | |
| EP0096419B1 (en) | Distributed variable-band switching system for speech and data | |
| CN104980224A (en) | FC-AE-1553 data exchange mode design method, FC-AE-1553 data exchange mode network control method and FC-AE-1553 data exchange mode energy saving method | |
| CN102111327B (en) | Method and system for cell dispatching | |
| CN101729407A (en) | Low delay jitter exchanging method and equipment based on unicast and multicast differentiated treatment | |
| CN103199968A (en) | Sending method of messages and system | |
| CN110928694B (en) | Computer system | |
| CN101707629B (en) | Synchronous communication method of mirror images for self organization information of safety and stability control device of electric network | |
| CN101695192A (en) | Method and system for realizing resource distribution between baseband processing unit and radio frequency unit | |
| CN101719876A (en) | Network communication dispatching method and system | |
| CN106571991A (en) | Method and data for transmitting data | |
| CN103888374A (en) | Comprehensive sensor network service middle piece and service transmission achieving method thereof | |
| CN100334819C (en) | Ethernet optical fiber transceiver and data transceiving method used on said tranceiver | |
| CN107508648A (en) | Time triggered Ethernet substep time synchronized strategy based on functions of the equipments classification | |
| CN103078808B (en) | The data flow being applicable to multithread matching regular expressions exchanges multiplex system and method | |
| CN102497603B (en) | EPON cell downlink service scheduling optimization method for easing main line communication pressure | |
| CN1559126B (en) | Method for operating an isochronous cyclic communication system | |
| CN101415027A (en) | Communication module based on HDLC protocol, and control method for data real time forwarding and storage | |
| CN108462653A (en) | The quick sending method of Protocol Control frame based on TTE | |
| CN109819457A (en) | Two-stage thresholding polling system based on FPGA | |
| CN105530065B (en) | For system and method at IEEE1588 pairs of PRP/HSR | |
| CN108616570A (en) | One kind being based on the asymmetric gated polling system polling systems of FPGA | |
| CN103414660A (en) | Node device of sensing network capable of supporting sensing access and optical packet transmission |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180413 |