CN107908577B - Multi-channel access memory controller circuit with arbitration function - Google Patents
Multi-channel access memory controller circuit with arbitration function Download PDFInfo
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- CN107908577B CN107908577B CN201711202544.6A CN201711202544A CN107908577B CN 107908577 B CN107908577 B CN 107908577B CN 201711202544 A CN201711202544 A CN 201711202544A CN 107908577 B CN107908577 B CN 107908577B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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Abstract
The invention belongs to the technical field of integrated circuits, and relates to a circuit of a multi-channel access memory controller with an arbitration function, which comprises: the device comprises a request monitoring and caching circuit (1), a request arbitration circuit (2), an address decoding circuit (3), a data address caching circuit (4), a response feedback circuit (5) and a time sequence conversion circuit (6). The circuit with the arbitration function for the multi-channel access memory controller is used for realizing the access of a plurality of processing cores to the memory controller, supporting multi-priority arbitration and supporting continuous and discrete control mode switching.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and relates to a circuit of a multi-channel access memory controller with an arbitration function.
Background
Graphics processors typically have multiple processing cores that all require access to the memory chip through a memory controller, but the memory controller can only respond to access requirements of one core. There is a need for a circuit with arbitration to reasonably arbitrate and sequence access requests of multiple paths, and then arrange a memory controller to service the access requests. The arbitration circuit should guarantee the priority of each core and guarantee the data bandwidth of each channel through the switching of the discrete and continuous modes, so as to support the efficient operation of each core.
Disclosure of Invention
The purpose of the invention is: the circuit of the multi-channel access memory controller with the arbitration function is used for realizing the access of a plurality of processing cores to the memory controller, supporting multi-priority arbitration and supporting continuous and discrete control mode switching.
The technical solution of the invention is as follows:
a circuit of a multiple access memory controller having arbitration functionality, comprising:
the device comprises a request monitoring and caching circuit 1, a request arbitration circuit 2, an address decoding circuit 3, a data address caching circuit 4, a response feedback circuit 5 and a time sequence conversion circuit 6;
request monitor and cache circuit 1, which monitors all ways every cycle, stores the tag location "1" of the requested way in the cache. The control mode (discrete control mode or continuous control mode) of the reading channel and the reading and writing mode are sent to the response feedback circuit 5;
a request arbitration circuit 2, which acquires the zone bit of the request channel from the request monitoring and cache circuit 1, acquires the zone bit of the served channel from the response feedback circuit 5, and uses the zone bit of the served channel to shield the zone bit of the request channel to obtain the zone bit of the channel to be served; arbitrating a current path needing service according to the priority of the path, and opening a corresponding address decoding channel in the address decoding circuit 3 and a data cache channel in the data address cache circuit 4;
an address decoding circuit 3 for decoding the address currently sent by the service access, sending a decoding completion signal to a response feedback circuit 5, and storing the decoded address in a data address cache circuit 4;
a data address buffer circuit 4 for buffering the address decoded by the address decoding circuit 3; during writing operation, the cache is extracted by the data waiting time sequence conversion circuit 6 sent by the service access, and during reading operation, the cache waits for the access to extract the data returned by the time sequence conversion circuit 6;
and the response feedback circuit 5 receives the channel control mode sent by the request monitoring and caching circuit 1, the address decoding completion signal of the request arbitration circuit 2 and the data return signal of the timing conversion circuit 6. For the write operation, the response feedback circuit 5 will send the flag bit of the served channel to the request arbitration circuit 2 when the address decoding is completed; for the read operation, in the discrete control mode, the response feedback circuit 5 will send the flag bit of the served channel to the request arbitration circuit 2 when the address decoding is completed, and in the continuous control mode, the response feedback circuit 5 will send the flag bit of the served channel to the request arbitration circuit 2 when the data return is completed;
and the timing conversion circuit 6 is used for sending the address and the data in the data address cache circuit 4 to the memory controller and storing the data returned by the memory controller into the data address cache circuit 4.
The invention has the advantages that: the circuit with the arbitration function for the multi-channel access memory controller is used for realizing the access of a plurality of processing cores to the memory controller, supporting multi-priority arbitration and supporting continuous and discrete control mode switching.
Drawings
FIG. 1 is a block diagram and flow diagram of a multi-channel access memory controller with arbitration according to the present invention;
FIG. 2 is a diagram illustrating an arbitration method.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings.
The invention relates to a circuit of a multi-channel access memory controller with an arbitration function, as shown in fig. 1, comprising: the device comprises a request monitoring and cache circuit 1, a request arbitration circuit 2, an address decoding circuit 3, a data address cache circuit 4, a response feedback circuit 5 and a time sequence conversion circuit 6.
Request monitor and cache circuit 1, which monitors all ways every cycle, stores the tag location "1" of the requested way in the cache. The control mode (discrete control mode or continuous control mode) of the read path and the read/write mode are sent to the response feedback circuit 5.
A request arbitration circuit 2, which acquires the zone bit of the request channel from the request monitoring and cache circuit 1, acquires the zone bit of the served channel from the response feedback circuit 5, and uses the zone bit of the served channel to shield the zone bit of the request channel to obtain the zone bit of the channel to be served; arbitrating the current path to be served according to the priority of the path, and opening the corresponding address decoding channel in the address decoding circuit 3 and the data cache channel in the data address cache circuit 4.
An address decoding circuit 3 for decoding the address currently sent by the service access, sending a decoding completion signal to a response feedback circuit 5, and storing the decoded address in a data address cache circuit 4;
a data address buffer circuit 4 for buffering the address decoded by the address decoding circuit 3; the data sent by the service path is buffered during the write operation to wait for the timing conversion circuit 6 to extract, and the data returned by the timing conversion circuit 6 is buffered during the read operation to wait for the path to extract.
And the response feedback circuit 5 receives the channel control mode sent by the request monitoring and caching circuit 1, the address decoding completion signal of the request arbitration circuit 2 and the data return signal of the timing conversion circuit 6. For the write operation, the response feedback circuit 5 will send the flag bit of the served channel to the request arbitration circuit 2 when the address decoding is completed; for a read operation, in the discrete control mode, the response feedback circuit 5 sends the flag bit of the served channel to the request arbitration circuit 2 when the address decoding is completed, and in the continuous control mode, the response feedback circuit 5 sends the flag bit of the served channel to the request arbitration circuit 2 when the data return is completed.
And the timing conversion circuit 6 is used for sending the address and the data in the data address cache circuit 4 to the memory controller and storing the data returned by the memory controller into the data address cache circuit 4.
The arbitration process for the request is shown in FIG. 2: requests issued by n different paths in the same cycle are extracted as n flag bits. The path that has been serviced is extracted as n mask bits. The request flag bit is masked into a new flag bit list, and the service is continued according to the priority from high to low. The arbitrated new service path will continue to perform address decoding and data buffering operations.
Finally, it should be noted that: the above is only used to illustrate the technical solution of the present invention, and not to limit it; while the invention has been described in detail with reference to the foregoing, those of ordinary skill in the art will understand that: the technical solution described above can still be modified or some of the technical features can be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (1)
1. A circuit of a multiple access memory controller having an arbitration function, characterized by: the circuit comprises: the device comprises a request monitoring and caching circuit (1), a request arbitration circuit (2), an address decoding circuit (3), a data address caching circuit (4), a response feedback circuit (5) and a time sequence conversion circuit (6); wherein:
the request monitoring and cache circuit (1) monitors all the paths in each period, and stores the mark position '1' of the request path into a cache; the control mode and the read-write mode of the reading channel are sent to a response feedback circuit (5); the control mode comprises a discrete control mode and a continuous control mode; the discrete control mode is that the response feedback circuit (5) sends a flag bit of a served channel to the request arbitration circuit (2) when the address decoding is finished; the continuous control mode is that the response feedback circuit (5) sends a flag bit of a served channel to the request arbitration circuit (2) when the data return is completed;
the request arbitration circuit (2) acquires the zone bit of the request channel from the request monitoring and cache circuit (1), acquires the zone bit of the served channel from the response feedback circuit (5), and shields the zone bit of the request channel by using the zone bit of the served channel to obtain the zone bit of the channel to be served; arbitrating a current path needing service according to the priority of the path, and opening a corresponding address decoding channel in the address decoding circuit (3) and a data cache channel in the data address cache circuit (4);
the address decoding circuit (3) decodes the address sent by the current served channel, sends a decoding completion signal to the response feedback circuit (5), and stores the decoded address into the data address cache circuit (4);
the data address cache circuit (4) caches the address decoded by the address decoding circuit (3); during writing operation, caching data sent by the service path to wait for the timing sequence conversion circuit (6) to extract, and during reading operation, caching data returned by the timing sequence conversion circuit (6) to wait for the path to extract;
the response feedback circuit (5) receives a channel control mode sent by the request monitoring and cache circuit (1), an address decoding completion signal of the request arbitration circuit (2) and a data return signal of the time sequence conversion circuit (6); for write operation, the response feedback circuit (5) sends the flag bit of the served channel to the request arbitration circuit (2) when the address decoding is completed; for reading operation, in a discrete control mode, the response feedback circuit (5) sends a flag bit of a served channel to the request arbitration circuit (2) when address decoding is completed, and in a continuous control mode, the response feedback circuit (5) sends the flag bit of the served channel to the request arbitration circuit (2) when data return is completed;
the time sequence conversion circuit (6) sends the address and the data in the data address buffer circuit (4) to the memory controller, and stores the data returned by the memory controller into the data address buffer circuit (4).
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| CN201711202544.6A CN107908577B (en) | 2017-11-24 | 2017-11-24 | Multi-channel access memory controller circuit with arbitration function |
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| CN107908577B true CN107908577B (en) | 2021-03-26 |
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| CN112650697B (en) * | 2020-12-24 | 2023-04-18 | 西安翔腾微电子科技有限公司 | Arbitration circuit of multiple main devices based on DDR3 storage controller interface |
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| JP2007094649A (en) * | 2005-09-28 | 2007-04-12 | Kyocera Mita Corp | Access arbitration circuit |
| CN101065739A (en) * | 2004-09-28 | 2007-10-31 | 皇家飞利浦电子股份有限公司 | Data processing system and method for memory arbitration |
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| CN104321758A (en) * | 2013-01-17 | 2015-01-28 | 英特尔公司 | Arbitrating memory accesses via a shared memory fabric |
| US9489314B2 (en) * | 2012-10-24 | 2016-11-08 | Texas Instruments Incorporated | Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP5974720B2 (en) * | 2012-08-09 | 2016-08-23 | 富士通株式会社 | Arithmetic processing device, information processing device, and control method for information processing device |
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| CN101065739A (en) * | 2004-09-28 | 2007-10-31 | 皇家飞利浦电子股份有限公司 | Data processing system and method for memory arbitration |
| JP2007094649A (en) * | 2005-09-28 | 2007-04-12 | Kyocera Mita Corp | Access arbitration circuit |
| CN102023890A (en) * | 2009-09-15 | 2011-04-20 | Arm有限公司 | A data processing apparatus and method for setting dynamic priority levels for transactions according to latency feedback |
| US9489314B2 (en) * | 2012-10-24 | 2016-11-08 | Texas Instruments Incorporated | Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC |
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