CN107894966A - A kind of fft processor engine prototype under block floating point pattern based on streamline - Google Patents
A kind of fft processor engine prototype under block floating point pattern based on streamline Download PDFInfo
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- CN107894966A CN107894966A CN201711300694.0A CN201711300694A CN107894966A CN 107894966 A CN107894966 A CN 107894966A CN 201711300694 A CN201711300694 A CN 201711300694A CN 107894966 A CN107894966 A CN 107894966A
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- streamline
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
- G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
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Abstract
The present invention discloses the fft processor engine prototype under a kind of block floating point pattern based on streamline.The feature of framework is that data are first read from memory；Input register group, plus control logic；By streamline shift register group, along with control logic；Output register group, finally writes back to memory.By input register group, control logic, streamline shift register group, output register group, the fft processor engine prototype under the block floating point pattern based on streamline is built.
Description
Technical field
The present invention relates to the fft processor engine prototype under a kind of block floating point pattern based on streamline
Background technology
The speed of sequence circuit by between any two register or one input a register between or one deposit
Most long path limits in the path of device and outlet chamber.This most long path can pass through the appropriate insertion stream in circuit structure
Pipeline register shortens.The pipeline design is to be prolonged using register pair complex combination logic circuit according to desired critical path
The slow time is split, and critical path delay reduces after design, and clock frequency improves, throughput increase.
As a kind of alternative that can improve circuit performance, pipeline-type register can be inserted into combinational logic
Key position on, by logical division into the group with more short path.The layout of these registers is by before data path
Feedback cut set is determined, to ensure that data are still correlation.Pipelining reduces the series in combinational logic, shortens
Data path between memory element.
Pipelining has cost reasons.But for high-end FPGA, they have abundant register,
So it is easily achieved pipeline organization.Pipelining by calculating smaller function in a short time, with the complexity in space
Spend to exchange the complexity of time for.This technology is by by the logical width needed for a time cycle completion repertoire
What the method being assigned on multiple short clock-cycles was realized.
It is that data are divided into group using block floating point algorithm, the bi-directional scaling relative to each other of the data in group, but can not be with
The member of other groups scales in the same proportion, even if the so simple mathematical operation of such as multiplication.In more complicated matrix
More complicated mathematical operation is needed in situation of inverting, between packet, must just use block floating point processor.
Block floating point quantization algorithm is based on the fact that in a small time interval entropy of data will be less than whole data
The entropy of collection.Block floating point quantizer is the output stream of a reception analog-digital converter, and is original by sampled data unified quantization
A kind of equipment of effectively representation of beginning data, only requires that bit number is less than sample number in quantizing process.
Most important resource is exactly DSP in FPGA.FPGA has done very more fit to traditional communication, picture signal processing
Match somebody with somebody, the hardware structure of early stage has been able to this kind of algorithm of perfect cooperation.Designer only needs simple research DSP structure just very
Easily find：DSP is matched completely with algorithm.
The invention provides the fft processor engine prototype under a kind of block floating point pattern based on streamline.The spy of framework
Levy and be, data are first read from memory；Input register group, plus control logic；By streamline shift register group, then
Plus control logic；Output register group, finally writes back to memory.By input register group, control logic, streamline displacement
Register group, output register group, build the fft processor engine prototype under the block floating point pattern based on streamline.
The content of the invention
It is an object of the invention to provide the fft processor engine prototype under a kind of block floating point pattern based on streamline.
The present invention includes following characteristics：
Inventive technique scheme
1. the DSP inside structures under a kind of block floating point pattern based on streamline, the feature of framework：
1) data are first read from memory；
2) input register group, plus control logic；
3) by streamline shift register group, along with control logic；
4) output register group, memory is finally write back to.
2. the framework based on claim 1, by input register group, control logic, streamline shift register group, output
Register group, build the fft processor engine prototype under the block floating point pattern based on streamline.
Brief description of the drawings
Accompanying drawing 1 is the fft processor engine prototype figure under the block floating point pattern based on streamline.
Embodiment
Fft processor engine prototype under this block floating point pattern based on streamline, comprises the following steps feature：
1) data are first read from memory；
2) input register group, plus control logic；
3) by streamline shift register group, along with control logic；
4) output register group, memory is finally write back to；
5) by input register group, control logic, streamline shift register group, output register group, structure is based on stream
Fft processor engine prototype under the block floating point pattern of waterline.
Claims (2)
1. the DSP inside structures under a kind of block floating point pattern based on streamline, the feature of framework：
1) data are first read from memory；
2) input register group, plus control logic；
3) by streamline shift register group, along with control logic；
4) output register group, memory is finally write back to.
2. the framework based on claim 1, deposited by input register group, control logic, streamline shift register group, output
Device group, build the fft processor engine prototype under the block floating point pattern based on streamline.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711300694.0A CN107894966A (en) | 2017-12-11 | 2017-12-11 | A kind of fft processor engine prototype under block floating point pattern based on streamline |
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| CN201711300694.0A CN107894966A (en) | 2017-12-11 | 2017-12-11 | A kind of fft processor engine prototype under block floating point pattern based on streamline |
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| CN107894966A true CN107894966A (en) | 2018-04-10 |
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| CN201711300694.0A Pending CN107894966A (en) | 2017-12-11 | 2017-12-11 | A kind of fft processor engine prototype under block floating point pattern based on streamline |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108037953A (en) * | 2017-12-11 | 2018-05-15 | 上海齐网网络科技有限公司 | A kind of DSP inside structures under block floating point pattern based on assembly line |
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| CN101720025A (en) * | 2009-12-07 | 2010-06-02 | 上海电器科学研究所（集团）有限公司 | Water area wireless image transmission system of high-performance unmanned patrol device above water |
| CN102033732A (en) * | 2010-12-17 | 2011-04-27 | 浙江大学 | Field programmable gate array (FPGA)-based high-speed and low-delay floating point accumulator and realizing method thereof |
| CN102629191A (en) * | 2011-04-25 | 2012-08-08 | 中国电子科技集团公司第三十八研究所 | Digital signal processor addressing method |
| CN107168927A (en) * | 2017-04-26 | 2017-09-15 | 北京理工大学 | A kind of sparse Fourier transform implementation method based on flowing water feedback filtering structure |
| TW201737075A (en) * | 2016-04-01 | 2017-10-16 | Ａｒｍ股份有限公司 | Complex multiply instruction |
| CN108037953A (en) * | 2017-12-11 | 2018-05-15 | 上海齐网网络科技有限公司 | A kind of DSP inside structures under block floating point pattern based on assembly line |
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2017
- 2017-12-11 CN CN201711300694.0A patent/CN107894966A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101720025A (en) * | 2009-12-07 | 2010-06-02 | 上海电器科学研究所（集团）有限公司 | Water area wireless image transmission system of high-performance unmanned patrol device above water |
| CN102033732A (en) * | 2010-12-17 | 2011-04-27 | 浙江大学 | Field programmable gate array (FPGA)-based high-speed and low-delay floating point accumulator and realizing method thereof |
| CN102629191A (en) * | 2011-04-25 | 2012-08-08 | 中国电子科技集团公司第三十八研究所 | Digital signal processor addressing method |
| TW201737075A (en) * | 2016-04-01 | 2017-10-16 | Ａｒｍ股份有限公司 | Complex multiply instruction |
| CN107168927A (en) * | 2017-04-26 | 2017-09-15 | 北京理工大学 | A kind of sparse Fourier transform implementation method based on flowing water feedback filtering structure |
| CN108037953A (en) * | 2017-12-11 | 2018-05-15 | 上海齐网网络科技有限公司 | A kind of DSP inside structures under block floating point pattern based on assembly line |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108037953A (en) * | 2017-12-11 | 2018-05-15 | 上海齐网网络科技有限公司 | A kind of DSP inside structures under block floating point pattern based on assembly line |
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Application publication date: 20180410 |