CN107871665B - Field effect transistor with electrode portion sequentially coated by oxide layer and nitride layer and manufacturing method thereof - Google Patents
Field effect transistor with electrode portion sequentially coated by oxide layer and nitride layer and manufacturing method thereof Download PDFInfo
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- CN107871665B CN107871665B CN201610857570.1A CN201610857570A CN107871665B CN 107871665 B CN107871665 B CN 107871665B CN 201610857570 A CN201610857570 A CN 201610857570A CN 107871665 B CN107871665 B CN 107871665B
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- 230000005669 field effect Effects 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 369
- 210000000746 body region Anatomy 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 18
- 238000000576 coating method Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 16
- 238000005253 cladding Methods 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 101000701286 Pseudomonas aeruginosa (strain ATCC 15692 / DSM 22644 / CIP 104116 / JCM 14847 / LMG 12228 / 1C / PRS 101 / PAO1) Alkanesulfonate monooxygenase Proteins 0.000 description 4
- 101000983349 Solanum commersonii Osmotin-like protein OSML13 Proteins 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000750 constant-initial-state spectroscopy Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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Abstract
A field effect transistor using oxide layer and nitride layer to cover electrode part in sequence and its manufacturing method, the epitaxial layer on the semiconductor substrate in the field effect transistor is equipped with a groove, and the residual oxide layer in the groove is covered with a covering nitride layer, the covering nitride layer is covered with a covering oxide layer, the covering oxide layer is covered with an electrode part. The grid electrode oxidation layer is formed on the side wall of the groove, and covers the nitride layer and the residual oxidation layer. The grid electrode part is formed on the grid electrode oxide layer and is separated from the electrode part sequentially through the grid electrode oxide layer, the covering nitride layer and the covering oxide layer. The epitaxial layer is provided with a body region and a source region adjacent to the gate part, and the source region and the gate part are covered with an interlayer dielectric layer. The source electrode covers the body region and the interlayer dielectric layer and contacts the source region.
Description
Technical Field
The present invention relates to a field effect transistor with an electrode portion sequentially covered by an oxide layer and a nitride layer and a method for manufacturing the same, and more particularly, to a field effect transistor with an electrode portion sequentially covered by an oxide layer and a nitride layer and a method for manufacturing the same.
Background
With the development of technology and the advancement of era, the advancement of Semiconductor process technology has led to the development of Metal-Oxide-Semiconductor Field Effect transistors (MOSFETs, hereinafter referred to as MOSFETs).
Referring to fig. 1, fig. 1 shows a schematic structural view of a prior art field effect transistor of the present invention, as shown in fig. 1, in a field effect transistor PA1 formed by a conventional method, an electrode portion PA12 and a gate portion PA13 are formed in a trench PA11, wherein the electrode portion PA12 and the gate portion PA13 are isolated from each other, and in the conventional forming method, the gate portion PA13 generally has a recess (double) structure PA 131.
However, the recessed structure PA131 also causes problems with conventional MOSFETs, such as high total gate charge (Qg) and high practical performance index (FOM) problems.
The total grid charge refers to the charge required by the grid when the MOSFET is in a complete conduction state, the total grid charge is related to the starting speed of the MOSFET, and the high total grid charge can reduce the switching speed and increase the grid loss, so that the switching conversion loss is improved and the efficiency is reduced; the actual performance index is determined by the on-resistance and the total gate charge (Qg multiplied by Rdson), with a high actual performance index indicating poor on-loss and switching loss.
Therefore, in the process of manufacturing the MOSFET and forming the trench, how to improve the recess structure to reduce the total gate charge and the actual performance index becomes an improvement target of the prior art.
Disclosure of Invention
In view of the problems of high total gate charge and high practical performance index of the conventional MOSFET structure and the manufacturing process thereof. Accordingly, the present invention provides a field effect transistor and a method for manufacturing the same, wherein an electrode is sequentially coated with an oxide layer and a nitride layer, and the total gate charge and the actual performance index are reduced by sequentially coating the electrode with the oxide layer and the nitride layer.
In view of the above, the present invention provides a method for manufacturing a field effect transistor, in which an electrode portion is sequentially coated with an oxide layer and a nitride layer, the method including steps (a) to (n), the step (a) providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and then performing the step (b) etching a trench extending in a vertical direction in the epitaxial layer, the trench having a trench sidewall and a trench bottom. Then, step (c) is carried out to form a first oxide layer on the surface of the epitaxial layer, the side wall of the groove and the bottom of the groove, and a first nitride layer is formed on the first oxide layer, and step (d) is carried out to form a second oxide layer on the first nitride layer, and a first polysilicon layer is formed on the second oxide layer. And (f) forming a third oxide layer on the electrode part and the second oxide layer.
And (g) etching part of the second oxide layer and the third oxide layer to form a coating oxide layer coating the electrode part by the residual second oxide layer and the third oxide layer, and (h) forming a second nitride layer on the coating oxide layer and the first nitride layer. And (f) performing step (i) to etch part of the first nitride layer and the second nitride layer, so that the residual first nitride layer and the residual second nitride layer form a cladding nitride layer which wraps the cladding oxide layer in the groove. And (k) forming a gate oxide layer on the side wall of the trench, the cladding nitride layer and the residual oxide layer, and forming a gate part on the gate oxide layer, wherein the gate part is separated from the electrode part sequentially through the gate oxide layer, the cladding nitride layer and the cladding oxide layer. Then, step (l) is performed to sequentially form a body region and a source region on the epitaxial layer adjacent to the gate portion, and step (m) is performed to form an interlayer dielectric layer covering the source region and the gate portion. And (n) forming a source electrode covering the body region and the interlayer dielectric layer and contacting the source region to manufacture the field effect transistor with the oxide layer and the nitride layer sequentially covering the electrode part.
Based on the above-mentioned necessary technical means, the method for manufacturing a field effect transistor in which an electrode portion is sequentially covered with an oxide layer and a nitride layer further includes the following preferred auxiliary technical means. In step (c), the first oxide layer includes a first sub-oxide layer and a second sub-oxide layer, the first sub-oxide layer is formed on the surface of the epitaxial layer, the trench sidewall and the trench bottom of the trench, and the second sub-oxide layer is formed on the first sub-oxide layer. In addition, in step (j), the residual oxide layer has a gradually recessed structure gradually recessed from the periphery toward the center of the trench, and in step (k), the gate oxide layer fills the gradually recessed structure. In addition, the step (k) further includes a step (k0) of forming a second polysilicon layer on the gate oxide layer, and etching a portion of the second polysilicon layer to form a gate portion in the trench with the remaining second polysilicon layer.
In view of the above, the main technical means of the present invention is to provide a field effect transistor with an electrode portion sequentially covered by an oxide layer and a nitride layer, which comprises a semiconductor substrate, an epitaxial layer, a residual oxide layer, an electrode portion, a covering oxide layer, a covering nitride layer, a gate oxide layer, a gate portion, a body portion, a source region, an interlayer dielectric layer, and a source electrode. The epitaxial layer is formed on the semiconductor substrate and extends along a vertical direction to form at least one groove, and the groove is provided with a groove side wall and a groove bottom. The residual oxide layer is formed on the side wall of the groove and the bottom of the groove, and the electrode part is formed in the groove. The coating oxide layer is formed in the groove and coats the electrode part, and the coating nitride layer is formed in the groove and coats the coating oxide layer and is partially coated by the residual oxide layer. The grid electrode oxide layer is formed on the side wall of the groove, the covering nitride layer and the residual oxide layer, and the grid electrode part is formed on the grid electrode oxide layer and is separated from the electrode part sequentially through the grid electrode oxide layer, the covering nitride layer and the covering oxide layer. The body region is arranged on the epitaxial layer, is adjacent to the grid part and is separated from the grid part through the grid oxide layer. The source region is arranged on the body region and is separated from the gate part by the gate oxide layer, the interlayer dielectric layer covers the source region and the gate part, and the source electrode covers the body region and the interlayer dielectric layer and is contacted with the source region.
Based on the above-mentioned necessary technical means, the field effect transistor in which the electrode portion is sequentially covered with the oxide layer and the nitride layer further includes the following preferred auxiliary technical means. The residual oxide layer has a gradually concave structure gradually recessed from the periphery toward the center of the trench, and the gate oxide layer fills the gradually concave structure.
After the field effect transistor and the manufacturing method thereof which sequentially coat the electrode part by using the Oxide layer and the Nitride layer are adopted, the coating Nitride layer is partially coated by the residual Oxide layer, the coating Oxide layer is coated by the coating Nitride layer, and the electrode part is coated by the coating Oxide layer to form an ONO (Oxide-Nitride-Oxide) structure, so that the total grid charge and the actual performance index can be effectively reduced.
In addition, after the field effect transistor and the manufacturing method thereof which sequentially cover the electrode part by the oxide layer and the nitride layer are adopted, the grid oxide layer is filled with the gradually concave structure, so that the concave structure in the prior art can be effectively improved, and the total grid charge and the actual performance index are reduced.
The present invention will be further described with reference to the following embodiments and drawings.
Drawings
FIG. 1 is a schematic diagram of a prior art FET structure;
fig. 2A and 2B are schematic flow charts illustrating a method for manufacturing a field effect transistor in which an electrode portion is sequentially covered with an oxide layer and a nitride layer according to a preferred embodiment of the present invention.
Fig. 3 is a cross-sectional view of a semiconductor substrate and an epitaxial layer according to a preferred embodiment of the invention.
Fig. 4 shows a cross-sectional view of a trench etched into an epitaxial layer in accordance with a preferred embodiment of the present invention.
FIG. 5 is a cross-sectional view of a sacrificial oxide layer formed in a trench according to a preferred embodiment of the present invention.
Fig. 6 is a cross-sectional view of a first oxide layer, a first nitride layer, a second oxide layer and a first polysilicon layer formed in a trench according to a preferred embodiment of the invention.
Fig. 7 is a cross-sectional view of a third oxide layer formed on an electrode portion and a second oxide layer according to a preferred embodiment of the invention.
FIG. 8 is a cross-sectional view of a second nitride layer formed on the first nitride layer and the cladding oxide layer according to a preferred embodiment of the invention.
FIG. 9 is a cross-sectional view illustrating the etching of the first nitride layer, the second nitride layer and the first oxide layer according to the preferred embodiment of the present invention.
FIG. 10 is a cross-sectional view of the gate oxide layer and the second polysilicon layer according to the preferred embodiment of the present invention.
FIG. 11 is a cross-sectional view of an interlayer dielectric layer according to a preferred embodiment of the present invention.
Fig. 12 shows a cross-sectional view of the mask layer formed by the etch and portions of the body and source regions etched in accordance with a preferred embodiment of the present invention.
Fig. 13 is a cross-sectional view of a field effect transistor having an electrode portion sequentially covered with an oxide layer and a nitride layer according to a preferred embodiment of the present invention.
Fig. 14 shows a schematic diagram of a simulated structure of a prior art field effect transistor.
FIG. 15 is a schematic diagram showing a simulated structure of a field effect transistor with an electrode portion sequentially covered with an oxide layer and a nitride layer according to a preferred embodiment of the present invention.
FIG. 16 shows waveforms of the input capacitor of the present invention and the prior art.
FIG. 17 shows waveforms of the output capacitor of the present invention and the prior art.
FIG. 18 shows waveforms of inverse switched capacitors of the present invention and the prior art.
FIG. 19 shows waveforms of total gate charge for the present invention and the prior art.
[ notation ] to show
PA1 field effect transistor
PA11 groove
PA12 electrode part
PA13 gate part
PA131 concave structure
1 field effect transistor with electrode portion sequentially coated with oxide layer and nitride layer
11 semiconductor substrate
12 epitaxial layer
121 trench
1211 trench side
1212 groove bottom
13 electrode part
14 coating oxide layer
15 coating a nitride layer
16 residual oxide layer
161 gradually concave structure
17 gate oxide layer
18 grid part
19 body region
20 source region
21 interlayer dielectric layer
22 source electrode
100 hard mask
200 photoresist layer
400 first oxide layer
4001 first suboxide layer
4002 second sub-oxide layer
500 first nitride layer
600 second oxide layer
700 first poly-silicon layer
800 third oxide layer
900 second nitride layer
1000 second polysilicon layer
1100 mask layer
2000. 3000, 4000, 5000, 6000, waveform
7000、8000、9000、10000、11000
L vertical direction
Detailed Description
In the field effect transistor and the manufacturing method thereof using the oxide layer and the nitride layer to sequentially cover the electrode portion according to the present invention, the combination embodiments are not enumerated, so that the detailed description is omitted, and only a preferred embodiment is specifically described.
Referring to fig. 2A to 13, fig. 2A and 2B are schematic flow charts illustrating a method for manufacturing a field effect transistor with an electrode portion sequentially covered with an oxide layer and a nitride layer according to a preferred embodiment of the invention. Fig. 3 is a cross-sectional view of a semiconductor substrate and an epitaxial layer according to a preferred embodiment of the invention. Fig. 4 shows a cross-sectional view of a trench etched into an epitaxial layer in accordance with a preferred embodiment of the present invention. FIG. 5 is a cross-sectional view of a sacrificial oxide layer formed in a trench according to a preferred embodiment of the present invention. Fig. 6 is a cross-sectional view of a first oxide layer, a first nitride layer, a second oxide layer and a first polysilicon layer formed in a trench according to a preferred embodiment of the invention.
Fig. 7 is a cross-sectional view of a third oxide layer formed on an electrode portion and a second oxide layer according to a preferred embodiment of the invention. FIG. 8 is a cross-sectional view of a second nitride layer formed on the first nitride layer and the cladding oxide layer according to a preferred embodiment of the invention. FIG. 9 is a cross-sectional view illustrating the etching of the first nitride layer, the second nitride layer and the first oxide layer according to the preferred embodiment of the present invention. FIG. 10 is a cross-sectional view of the gate oxide layer and the second polysilicon layer according to the preferred embodiment of the present invention. FIG. 11 is a cross-sectional view of an interlayer dielectric layer according to a preferred embodiment of the present invention. Fig. 12 shows a cross-sectional view of the mask layer formed by the etch and portions of the body and source regions etched in accordance with a preferred embodiment of the present invention. Fig. 13 is a cross-sectional view of a field effect transistor having an electrode portion sequentially covered with an oxide layer and a nitride layer according to a preferred embodiment of the present invention.
As shown in fig. 13, in the steps of the method for manufacturing a field effect transistor with an electrode portion sequentially covered by an oxide layer and a nitride layer according to the preferred embodiment of the present invention, as shown in fig. 3, step S101 is first performed to provide a semiconductor substrate 11, and an epitaxial layer 12 is formed on the semiconductor substrate 11 (the forming method is prior art, and the forming method will not be described again. The semiconductor substrate 11 is generally doped with an ion concentration (e.g., N type), the epitaxial layer 12 is also generally doped with an ion concentration (e.g., N type), and the ion concentration of the epitaxial layer 12 is lower than that of the semiconductor substrate 11.
After step S101, step S102 is performed to etch at least one trench 121 (only one trench 121 is shown in fig. 4) extending in a vertical direction L in the epitaxial layer 12, where the trench 121 has a trench sidewall 1211 and a trench bottom 1212, and in the etching method, as shown in fig. 4, a hard mask 100 (the material is prior art and is not described again) is formed on the epitaxial layer 12, and then a photoresist layer 200 (the material is prior art and is not described again) is formed on the hard mask 100, and then the trench 121 is etched (which etching is prior art and which etching is used in the portion of "etching" mentioned below is not described again). In addition, it should be noted that the trench sidewall 1211 in the preferred embodiment of the present invention refers to the sidewall of the entire trench 121, i.e., if viewed from the above, the sidewall is integral, rather than having two sidewalls as viewed from the cross-sectional view; in other embodiments, the trench may have two trench sidewalls 1211 themselves, as described herein.
As shown in fig. 5 and fig. 6, step S103 is performed to form a first oxide layer (oxidation)400 on the surface of the epitaxial layer 12, the trench sidewall 1211 and the trench bottom 1212 of the trench 121, and a first nitride layer (nitride) 500 is formed on the first oxide layer 400, wherein the materials of the first oxide layer 400 and the first nitride layer 500 are conventional and will not be described again.
Specifically, in step S103, a first sub-oxide layer 4001 is formed on the surface of the epitaxial layer 12, the trench sidewall 1211 and the trench bottom 1212 of the trench 121, and a second sub-oxide layer 4002 is formed on the first sub-oxide layer 4001, so that the first oxide layer 400 is formed by the second sub-oxide layer 4002 and the first sub-oxide layer 4001.
As shown in fig. 6, step S104 is performed to form a second oxide layer 600 on the first nitride layer 500, and a first polysilicon layer (polysilicon) 700 with an approximate T-shape is formed on the second oxide layer 600, and similarly, the materials of the second oxide layer 600 and the first polysilicon layer (polysilicon) 700 are also the prior art and will not be described again.
As shown in fig. 7, step S105 is performed to etch a portion of the first polysilicon layer 700, so that the remaining first polysilicon layer 700 forms an electrode portion 13 in the trench 121. Then, step S106 is performed to form a third oxide layer (oxidation)800 on the electrode portion 13 and the second oxide layer 600, and similarly, the material of the third oxide layer 800 is also the prior art and is not described again.
As shown in fig. 8, step S107 is performed to etch a portion of the second oxide layer 600 and the third oxide layer 800, so that the remaining second oxide layer 600 and the remaining third oxide layer 800 form a cladding oxide layer 14 covering the electrode portion 13. Then, step S108 is performed to form a second nitride layer (nitride) 900 on the cap oxide layer 14 and the first nitride layer 500, and the material of the second nitride layer 900 is also conventional and will not be described again.
As shown in fig. 9, step S109 is performed to etch a portion of the first nitride layer 500 and the second nitride layer 900, so that the remaining first nitride layer 500 and the remaining second nitride layer 900 form a covering nitride layer 15 covering the covering oxide layer 14 in the trench 121. Then, step S110 is performed to etch a portion of the first oxide layer 400, so that the remaining first oxide layer 400 forms a remaining oxide layer 16 in the trench 121, and the remaining oxide layer 16 has a gradually recessed structure 161 gradually recessed from the periphery toward the center of the trench 121.
As shown in fig. 10 and 11, step S111 is performed to form a gate oxide layer 17 on the trench sidewall 1211, the covering nitride layer 15 and the residual oxide layer 16, and form a gate portion 18 on the gate oxide layer 17, wherein the gate portion 18 is sequentially spaced from the electrode portion 13 by the gate oxide layer 17, the covering nitride layer 15 and the covering oxide layer 14, and the gate oxide layer 17 fills the tapered recess structure 161.
In addition, in the method for forming the gate portion 18, a second polysilicon layer 1000 is formed on the gate oxide layer 17, and a portion of the second polysilicon layer 1000 is etched, so that a gate portion 18 is formed in the trench 121 by the remaining second polysilicon layer 1000, thereby forming the gate portion 18 on the gate oxide layer 17.
As shown in fig. 11, step S112 is performed to sequentially form a body region (P-body)19 and a source region (N +)20 in the epitaxial layer 12 adjacent to the gate portion 18, which is not described in detail. The body region 19 is separated from the gate portion 18 by the gate oxide layer 17, the source region 20 is separated from the gate portion 18 by the gate oxide layer 17, and then step S113 is performed to form an Interlayer Dielectric (ILD) 21 covering the source region 20 and the gate portion 18.
As shown in fig. 12, a mask layer 1100 is formed on the interlayer dielectric layer 21, and after etching a portion of the body region 19 and the source region 20, the mask layer 1100 is removed.
As shown in fig. 13, step S114 is finally performed to form a source electrode 22 covering the body region 19 and the interlayer dielectric layer 21 and contacting the source region 20, thereby manufacturing the field effect transistor 1 of the preferred embodiment of the present invention in which the electrode portion is sequentially covered with the oxide layer and the nitride layer, wherein the source electrode 22 has an approximately n-shaped structure.
That is, in the field effect transistor 1 of the preferred embodiment of the present invention in which the electrode portions are sequentially covered with the oxide layer and the nitride layer, the epitaxial layer 12 is formed on the semiconductor substrate 11, the residual oxide layer 16 is located on the trench sidewall 1211 and the trench bottom 1212, and the electrode portion 13 is formed in the trench 121. The covering oxide layer 14 is located in the trench 121 and covers the electrode portion 13, and the covering nitride layer 15 is located in the trench 121, covers the covering oxide layer 14, and is partially covered by the residual oxide layer 16.
The gate oxide layer 17 is located on the trench sidewall 1211, the covering nitride layer 15 and the residual oxide layer 16, and the gate portion 18 is located on the gate oxide layer 17 and is sequentially spaced from the electrode portion 13 by the gate oxide layer 17, the covering nitride layer 15 and the covering oxide layer 14.
Referring to fig. 14 and 15 together, fig. 14 shows a simulated structure of a field effect transistor in the prior art, and fig. 15 shows a simulated structure of a field effect transistor in which an electrode portion is sequentially coated with an oxide layer and a nitride layer according to a preferred embodiment of the present invention.
As shown, after dc simulation of the structure of fig. 14 and 15 with software, the present invention can obtain the following values:
as can be seen from the above, the actual performance index of the structure provided by the present invention is lower than that of the prior art, so that the actual performance index can be effectively reduced by using the structure of the present invention. In addition, as can be seen from the figure, the field effect transistor 1 of the preferred embodiment of the present invention, which utilizes the oxide layer and the nitride layer to sequentially cover the electrode portion, can effectively improve the recess structure of the prior art.
Referring to fig. 16, fig. 16 shows waveforms of the input Capacitor (CISS) according to the present invention and the prior art. As shown in fig. 16, the ac simulation is performed with the structures of fig. 14 to 15, wherein the waveform 2000 represents the waveform of the structure of fig. 14, the waveform 3000 represents the waveform of the structure of fig. 15, and it can be known from the waveforms 2000 and 3000 that the input capacitance of the structure adopted by the present invention is significantly smaller than that of the prior art when the drain bias VD is 50V.
| VD＝50V | Input capacitance (pF) | Percentage of phase comparison |
| The structure of FIG. 14 | 4701.22 | N/A |
| The structure of FIG. 15 | 3046.956 | -35.19％ |
Referring to fig. 17, fig. 17 shows waveforms of the output Capacitor (COSS) according to the present invention and the prior art. As shown, fig. 17 is an Alternating Current (AC) simulation of the structure of fig. 14 and 15, wherein waveform 4000 represents the waveform of the structure of fig. 14, and waveform 5000 represents the waveform of the structure of fig. 15. From the waveforms 4000 and 5000, it can be seen that the output capacitance of the structure of the present invention is significantly smaller than that of the prior art when the drain bias VD is compared with 50V.
| VD＝50V | Output capacitance (pF) | Percentage of phase comparison |
| The structure of FIG. 14 | 824.3329 | N/A |
| The structure of FIG. 15 | 614.4153 | -25.47％ |
Referring to fig. 18, fig. 18 shows waveforms of inverse conversion Capacitors (CRSS) according to the present invention and the prior art. As shown, fig. 18 is a simulation of the structure of fig. 14 and 15, wherein waveform 6000 represents the waveform of the structure of fig. 14, and waveform 7000 represents the waveform of the structure of fig. 15. From the waveforms 6000 and 7000, it can be seen that the reverse conversion capacitance of the structure adopted by the present invention is significantly smaller than that of the prior art when the reverse conversion capacitance is compared with the drain bias VD of 50V.
| Converse conversion capacitor (pF) | Percentage of phase comparison | |
| The structure of FIG. 14 | 17.15413 | N/A |
| The structure of FIG. 15 | 9.846057 | -42.6％ |
Referring to fig. 19, fig. 19 shows waveforms of total gate charges according to the present invention and the prior art. As shown, after ac simulation, waveforms 8000 and 10000 represent waveforms of the structure of fig. 14, and waveforms 9000 and 11000 represent waveforms of the structure of fig. 15. From the waveforms 8000, 9000, 10000 and 11000, the total gate charge (Qg) of the structure of the present invention is lower regardless of the same gate bias VG or the same drain bias VD.
In summary, after the field effect transistor and the manufacturing method thereof sequentially covering the electrode portion with the oxide layer and the nitride layer provided by the present invention are adopted, since the complete ONO structure is formed and the gate oxide layer is filled in the gradually recessed structure, the recessed structure of the prior art can be effectively improved to reduce the total gate charge and the actual performance index.
The above detailed description of the preferred embodiments is intended to more clearly illustrate the features and spirit of the present invention, and is not intended to limit the scope of the present invention by the preferred embodiments disclosed above. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the scope of the claims.
Claims (8)
1. A method for manufacturing a field effect transistor with an electrode portion sequentially coated by an oxide layer and a nitride layer comprises the following steps:
(a) providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate;
(b) etching a groove extending along a vertical direction on the epitaxial layer, wherein the groove is provided with a groove side wall and a groove bottom;
(c) forming a first oxide layer on the surface of the epitaxial layer, the side wall of the groove and the bottom of the groove, and forming a first nitride layer on the first oxide layer;
(d) forming a second oxide layer on the first nitride layer, and forming a first polysilicon layer on the second oxide layer;
(e) etching part of the first polysilicon layer to form an electrode part in the groove by the residual first polysilicon layer;
(f) forming a third oxide layer on the electrode portion and the second oxide layer;
(g) etching part of the second oxide layer and the third oxide layer to form a coating oxide layer coating the electrode part by the residual second oxide layer and the third oxide layer;
(h) forming a second nitride layer on the cladding oxide layer and the first nitride layer;
(i) etching part of the first nitride layer and the second nitride layer to form a coating nitride layer coating the coating oxide layer in the groove by the residual first nitride layer and the second nitride layer;
(j) etching part of the first oxide layer to form a residual oxide layer in the trench;
(k) forming a gate oxide layer on the trench sidewall, the cladding nitride layer and the residual oxide layer, and forming a gate portion on the gate oxide layer, wherein the gate portion is spaced from the electrode portion sequentially through the gate oxide layer, the cladding nitride layer and the cladding oxide layer;
(l) Sequentially forming a body region and a source region on the epitaxial layer adjacent to the gate portion;
(m) forming an interlayer dielectric layer covering the source region and the gate portion; and
(n) forming a source electrode covering the body region and the interlayer dielectric layer and contacting the source region to manufacture the field effect transistor with the electrode portion sequentially covered by the oxide layer and the nitride layer.
2. The method according to claim 1, wherein in the step (c), the first oxide layer comprises a first sub-oxide layer and a second sub-oxide layer, the first sub-oxide layer is formed on the surface of the epitaxial layer, the trench sidewall of the trench and the trench bottom, and the second sub-oxide layer is formed on the first sub-oxide layer.
3. The method according to claim 1, wherein in step (j), the residual oxide layer has a gradually concave structure gradually concaved from the periphery toward the center of the trench.
4. The method according to claim 3, wherein in step (k), the gate oxide layer fills the recess structure.
5. The method according to claim 1, wherein said step (k) further comprises a step (k0) of forming a second polysilicon layer on said gate oxide layer and etching a portion of said second polysilicon layer such that the remaining second polysilicon layer forms said gate portion in said trench.
6. A field effect transistor with an electrode portion sequentially covered with an oxide layer and a nitride layer, comprising:
a semiconductor substrate;
an epitaxial layer formed on the semiconductor substrate and extending along a vertical direction to form at least one trench having a trench sidewall and a trench bottom;
a residual oxide layer formed on the side wall of the trench and the bottom of the trench;
an electrode part formed in the groove;
an encapsulating oxide layer formed in the trench and encapsulating the electrode portion;
a covering nitride layer formed in the trench, covering the covering oxide layer, and partially covered by the residual oxide layer;
a gate oxide layer formed on the trench sidewall, the cladding nitride layer and the residual oxide layer;
a gate part formed on the gate oxide layer and spaced from the electrode part by the gate oxide layer, the cladding nitride layer and the cladding oxide layer in sequence;
a body region disposed on the epitaxial layer and adjacent to the gate portion, and spaced from the gate portion by the gate oxide layer;
a source region disposed on the body region and spaced apart from the gate portion by the gate oxide layer;
an interlayer dielectric layer covering the source region and the gate portion; and
a source electrode covering the body region and the interlayer dielectric layer and contacting the source region.
7. The field effect transistor of claim 6, wherein the residual oxide layer has a gradually concave structure that gradually concaves from the periphery toward the center of the trench.
8. The field effect transistor of claim 7, wherein the tapered recess is filled with the gate oxide layer.
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| CN101473443A (en) * | 2006-06-19 | 2009-07-01 | 飞兆半导体公司 | Structure and method for forming a shielded gate trench FET with the shield and gate electrodes being connected together |
| CN102856182A (en) * | 2011-06-27 | 2013-01-02 | 半导体元件工业有限责任公司 | Method of making an insulated gate semiconductor device and structure |
| CN105355560A (en) * | 2015-10-27 | 2016-02-24 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for trench gate MOSFET with shield gate |
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| US8314471B2 (en) * | 2009-11-17 | 2012-11-20 | Diodes Incorporated | Trench devices having improved breakdown voltages and method for manufacturing same |
| US8642425B2 (en) * | 2012-05-29 | 2014-02-04 | Semiconductor Components Industries, Llc | Method of making an insulated gate semiconductor device and structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101473443A (en) * | 2006-06-19 | 2009-07-01 | 飞兆半导体公司 | Structure and method for forming a shielded gate trench FET with the shield and gate electrodes being connected together |
| CN102856182A (en) * | 2011-06-27 | 2013-01-02 | 半导体元件工业有限责任公司 | Method of making an insulated gate semiconductor device and structure |
| CN105355560A (en) * | 2015-10-27 | 2016-02-24 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for trench gate MOSFET with shield gate |
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