CN107862371B

CN107862371B - Vehicle loading counting control system

Info

Publication number: CN107862371B
Application number: CN201711133999.7A
Authority: CN
Inventors: 曾晓红; 凌云; 陈刚
Original assignee: Hunan University of Technology
Current assignee: Hefei Jiuzhou Longteng Scientific And Technological Achievement Transformation Co ltd; Ju Yang
Priority date: 2017-11-16
Filing date: 2017-11-16
Publication date: 2021-02-26
Anticipated expiration: 2037-11-16
Also published as: CN107862371A

Abstract

A vehicle loading counting control system comprises a controller unit, a human-computer interface unit, a 1-way or multi-way loading belt driving unit, a counting signal generating unit and an anti-interference circuit unit. When the system is used for loading, the loading products are automatically counted, so that the problem that manual counting is easy to cause errors is solved; the counting pulse can automatically filter narrow pulse interference, so that the counting accuracy is ensured; the anti-interference effect of the filtered narrow pulses can be adjusted by adjusting parameters in the multi-channel anti-interference circuit unit.

Description

Vehicle loading counting control system

Technical Field

The invention relates to the field of logistics, in particular to a vehicle loading counting control system.

Background

In the production enterprises of chemical fertilizers, cement, feed, grain depots and the like, a large amount of bagged products need to be shipped every day, counting is usually carried out in a manual bag-by-bag counting mode in the loading process, and after the number of loaded bags is reached, a conveying belt is informed to stop running. The manual counting is easy to generate errors, so that the company is lost or disputes occur with the goods taking personnel; the manual counting efficiency is low, and the cost is high.

Disclosure of Invention

In order to solve the problems in the loading counting of the existing bagged products, the invention provides a vehicle loading counting control system which comprises a controller unit, a human-computer interface unit, an L-path loading belt driving unit, an L-path counting signal generating unit and an L-path anti-interference circuit unit. And L is an integer greater than or equal to 1.

The L-path loading belt driving unit is connected with the controller unit and is used for driving the L-path loading belt system to operate; the human-computer interface unit is connected with the controller unit and used for setting and displaying the loading quantity and starting the L-way loading belt system to run and start loading; the L-path counting signal generating unit is respectively arranged on the L-path loading belt system and respectively generates and outputs L-path counting initial pulses; the L paths of counting initial pulses are respectively sent to input pulse ends of the L paths of anti-interference circuit units; and the output pulse end of the L-path anti-interference circuit unit is connected to the controller unit.

After the L-path loading belt system is started to operate and start loading, the controller unit counts the loading number of the vehicles according to the output pulse of the L-path anti-interference circuit unit, and the L-path loading belt system stops operating after the set loading number is reached.

And the L-path counting signal generating units are all photoelectric switch sensors. The controller unit is a programmable controller.

The L-path anti-interference circuit units are the same anti-interference circuit units; the anti-interference circuit unit comprises a shift register, a1 sampling value counter, a0 sampling value counter, a comparison threshold value setter, a first numerical value comparator, a second numerical value comparator, an RS trigger and an oscillator.

The shift register comprises a serial input end, an N-bit parallel output end and a sampling clock pulse input end, wherein the serial input end of the shift register is an input pulse end of the anti-interference circuit unit, and the N-bit parallel output end of the shift register outputs sequence data; the input of the 1 sampling value statistics device is sequence data, and the output is 1 sampling value statistics value; the input of the sampling value 0 number statistic device is sequence data, and the output is the sampling value 0 number statistic value; the output of the comparison threshold value setter is a comparison threshold value; the input of the first numerical value comparator is 1 number of statistical values and comparison threshold of sampling value, the output is the first set signal; the input of the second numerical value comparator is a sampling value 0 number statistical value and a comparison threshold value, and the output is a second set signal; the input end of the RS trigger is a first setting signal and a second setting signal, and the output end of the RS trigger is an output pulse end of the anti-interference circuit unit; the oscillator outputs a sampling clock pulse.

The sequence data is the latest N times sampling value of the shift register on the input pulse at the edge of the sampling clock pulse, the sampling value is

binary data

0 or 1, and N is an integer greater than or equal to 2. The comparison threshold is an integer greater than N/2(N divided by 2) and less than or equal to N.

The function of the 1 sampling value statistic device is that 1 output sampling value statistic is the number value of the number of '1' in the input sequence data; the function of the sampling value 0 number statistical device is that the output sampling value 0 number statistical value is the number value of '0' in the input sequence data.

The function of the first numerical value comparator is that when the number statistic value of the sampling value 1 is more than or equal to the comparison threshold value, the output first set signal is valid, otherwise, the output first set signal is invalid; the function of the second numerical value comparator is that when the number statistic of the sampling values 0 is more than or equal to the comparison threshold, the output second set signal is valid, otherwise, the output second set signal is invalid.

The first setting signal is a setting signal of the RS trigger, and the second setting signal is a reset signal of the RS trigger; the output pulse is output from the non-inverting output terminal of the RS trigger, and the output pulse is output from the inverting output terminal of the RS trigger.

The invention has the beneficial effects that: when loading, the 1-path or multi-path loading products are automatically counted, so that the problem that manual counting is easy to cause errors is avoided; the counting pulse can automatically filter out positive narrow pulse interference and negative narrow pulse interference, and the counting accuracy is ensured; the anti-interference effect of filtering narrow pulses can be adjusted by changing the number of bits of the parallel output end of the shift register or changing the size of the comparison threshold.

Drawings

FIG. 1 is a block diagram of an embodiment of a vehicle loading count control system;

FIG. 2 shows an embodiment of a count signal generating unit;

FIG. 3 illustrates an exemplary embodiment of an immunity circuit unit;

fig. 4 shows an embodiment of an N-5 shift register;

fig. 5 shows an embodiment of a 1-sample-value statistics device when N is 5;

fig. 6 shows an embodiment of a counter for 0 samples when N is 5;

fig. 7 is an embodiment of the comparison threshold setter and the first value comparator when N is 5;

FIG. 8 is an RS flip-flop embodiment;

FIG. 9 is an oscillator embodiment;

fig. 10 is a schematic diagram illustrating the interference rejection of the input/output pulse when N is 5.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

Fig. 1 is a block diagram of an embodiment of a vehicle loading counting control system when L is 2, which is used for controlling and driving a loading system with a 2-way loading belt conveyor, and includes a 2-way counting signal generating unit, a 2-way anti-jamming circuit unit, a controller unit 10, a 2-way loading belt driving unit 11, and a human-computer interface unit 12, wherein the 2-way counting signal generating unit is a 1# counting signal generating unit and a 2# counting signal generating unit, and the 2-way anti-jamming circuit unit is a 1# anti-jamming circuit unit and a 2# anti-jamming circuit unit.

FIG. 2 shows an embodiment of a # 1 count signal generating unit, which employs an ohm-dragon correlation type photoelectric switch, and a light projector 201 is model E3 ZG-T61-S; the model of the light receiver 202 is E3ZG-T61-S, the output end OUT1 adopts NPN triode collector open circuit output, the resistor R201 is the collector resistance thereof, and the 1# counting initial pulse P10 of the 1# counting signal generating unit is output from the OUT1 end of the light receiver 202. In fig. 5, + VCC is the power supply of the photoelectric switch, and GND is the common ground. The 1# counting signal generating unit can also adopt other correlation type photoelectric switches and reflection type photoelectric switches, and the pulse output form of the photoelectric switches can also be other forms of output types. The circuit and the structure of the 2# counting signal generating unit are the same as those of the 1# counting signal generating unit. The 2 paths of counting signal generating units 1# and 2# are respectively installed on the 2 paths of loading belt conveying devices and are respectively used for generating counting initial pulses P11 and P21 when loading products are loaded through the 2 paths of loading belt conveying devices.

In the embodiment of the vehicle loading counting control system when the number L is 2, the anti-jamming circuit units with the same structure are adopted as the 1# anti-jamming circuit unit and the 2# anti-jamming circuit unit. The counting initial pulses P11 and P21 are respectively input from the input pulse ends of the 1# anti-jamming circuit unit and the 2# anti-jamming circuit unit, the output pulse ends of the 1# anti-jamming circuit unit and the 2# anti-jamming circuit unit respectively output counting pulses P12 and P22, and the counting initial pulses P12 and P22 are connected to the controller unit 10, namely to 2 counting input ends of the PLC.

Fig. 3 shows an embodiment of the immunity circuit unit. In fig. 3, the shift register 101 includes a serial input terminal, an N-bit parallel output terminal, and a sampling clock pulse input terminal, an input pulse P1 is input from the serial input terminal of the shift register 101, and the serial input terminal of the shift register 101 is an input pulse terminal of the anti-jamming circuit unit; a sampling clock pulse CLK is input from a sampling clock pulse input end of the shift register 101, and an N-bit parallel output end of the shift register 101 outputs N-bit sequence data X1; the input of the sampling value 1 number statistic device 102 is sequence data X1, and the output is sampling value 1 number statistic Y1; the input of the sampling value 0 number statistic device 103 is sequence data X1, and the output is a sampling value 0 number statistic Y2; the output of the comparison threshold setter 104 is the comparison threshold Y0; the input of the first numerical comparator 105 is a sampling value 1 statistical value Y1 and a comparison threshold value Y0, and the output is a first set signal SE 1; the input of the second numerical comparator 106 is the sampling value 0, the statistical value Y2 and the comparison threshold value Y0, and the output is a second set signal RE 1; the input of the RS flip-flop 107 is a first set signal SE1 and a second set signal RE1, the output is an output pulse end of the anti-jamming circuit unit, and the output of the output pulse end is an output pulse P2; the oscillator 108 outputs a sampling clock pulse CLK.

In the following exemplary embodiment of the interference suppression circuit unit, N is 5.

FIG. 4 is an embodiment of a 5-bit shift register. In fig. 4, 5D flip-flops FF1, FF2, FF3, FF4 and FF5 form a 5-bit serial shift register, and an input end D of FF1 is a serial input end of the shift register and is connected to an input pulse P1; after the clock input ends CLK of FF1, FF2, FF3, FF4 and FF5 are connected in parallel, the clock input ends are formed into a shift pulse input end of the shift register, namely a sampling clock pulse input end of the shift register and are connected to the sampling clock pulse CLK; the output end Q of FF1, FF2, FF3, FF4 and FF5 is X11, X12, X13, X14 and X15 respectively, and in fig. 4, the sequence data X1 is composed of X11, X12, X13, X14 and X15. The sequence data X1 is the last N sample values of the shift register on the input pulse P1 at the rising edge of the sampling clock pulse CLK edge.

When N is other value, the number of D flip-flops in fig. 4 can be increased or decreased to realize the function of the shift register. The D flip-flop in fig. 4 may be replaced by other flip-flops, for example, N JK flip-flops are used to implement the function of the shift register. The shift register can also be implemented by using a single or multiple dedicated multi-bit shift registers, for example, 1 chip 74HC164 or 1 chip 74HC595 can be used to implement the function of the shift register with no more than 8 bits, and multiple chips 74HC164 or 74HC595 can be used to implement the function of the shift register with more than 8 bits.

Fig. 5 is an embodiment of a 1-sample-value-when-N-5 counter. The function of the sample value 1 count counter is that the output sample value 1 count value Y1 is the number value of "1" in the input sequence data X1. In fig. 5, the 1-bit total adder in fig. 5 includes a 1-bit addend input terminal a, a 1-bit addend input terminal B, a carry input terminal Ci, a 1-bit result output terminal S, and a 1-bit carry output terminal Co. The 1-bit full adder FA1 realizes statistics of the number of '1' in x11, x12 and x13, and n2 and n1 are 2-bit binary statistics results output of FA 1. 2 1-bit full adders FA2 and FA3 form a 2-bit binary adder, the FA2 and FA3 take n2 and n1 as an addend, take x14 as another addend, and take x15 as a low-order carry to carry out addition to obtain 3-bit binary outputs of Y13, Y12 and Y11, and the Y13, Y12 and Y11 are the 1 statistical value Y1 of the sampling value; when x14 is taken as another addend, the high order bit input from the B terminal of FA3 is 0. When the digital signal processor is connected to the input end of the statistical device with the sampling value of 1, the connection positions of x11, x12, x13, x14 and x15 can be interchanged with one another at will. The N-bit sequence data X1 is N-bit binary data, and the 1-sample value statistic device is actually a statistic adder for counting the number of "1" in the N-bit binary data.

The sampling value 0 number counter is composed of a counting adder and an N-bit inverter, wherein the structure and composition of the counting adder are the same as those of the sampling value 1 number counter; the input of the N-bit inverter is N-bit sequence data X1, and the output is N-bit inverted sequence data. Fig. 6 is an embodiment of a counter for counting 0 sample values when N is 5. The function of the sample value 0 statistic device is that the output sample value 0 statistic Y2 is the value of the number of "0" in the input sequence data X1. In fig. 6, the statistics device for 0 number of sampling values comprises a 5-bit inverter composed of 5 inverters FN1, FN2, FN3, FN4 and FN5 and a statistics adder composed of 3 1-bit full adders FA4, FA5 and FA6, wherein the function of the 5-bit inverter is to invert X11, X12, X13, X14 and X15 of 5-bit sequence data X1 one by one, and statistically convert the number of "0" into the number of "1"The number of the cells is counted. The 1-bit full adders in fig. 6 also include a 1-bit addend input terminal a, a 1-bit addend input terminal B, a carry input terminal Ci, and a 1-bit result output terminal S and a 1-bit carry output terminal Co. The 1-bit full adder FA4 realizes statistics of the number of '0' in x11, x12 and x13, and m2 and m1 are 2-bit binary statistics results output of FA 4. 2 1-bit full adders FA5 and FA6 form a 2-bit binary adder, and the FA5 and FA6 take m2 and m1 as addends and use the m2 and the m1 as addends

As another addend, will

Adding the low-order carry bits to obtain 3-bit binary outputs Y23, Y22 and Y21, wherein Y23, Y22 and Y21 are statistics values Y2 of the sampling value 0; will be provided with

When the other addend is set, the high order bit input from the B terminal of the FA6 is 0. When the device is connected to the input end of the statistics device of 0 sampling values, the connection positions of x11, x12, x13, x14 and x15 can be interchanged with one another at will.

The 1-bit adder function in the sample value 1 statistics and sample value 0 statistics functions may also be implemented in other circuit forms, for example, a carry look ahead integrated 4-bit adder 74HC283, a 4-bit binary parallel carry full adder CD4008, a 3-bit serial adder CD4032, or a combinational logic circuit composed of gates may be used to replace all or part of the 1-bit adders in fig. 5 and 6.

Fig. 7 shows an embodiment of the comparison threshold setter and the first numerical comparator when N is 5, in fig. 7, the comparison threshold setter is composed of a 3-bit binary dial switch SW1, + VCC is a power supply, GND is a common ground, and its 3-bit binary outputs Y03, Y02, and Y01 constitute a comparison threshold Y0. Since N is 5, Y0 can only take values of 3, 4, and 5, in this embodiment, the comparison threshold Y0 takes a value of 4, that is, Y03, Y02, and Y01 take values of 1, 0, and 0. The comparison threshold setter can be composed of a multi-bit binary dial switch, or a BCD dial switch, or a plurality of common switches and pull resistors, or a plurality of pull-up resistors for controlling 0 and 1 outputs, a circuit short-circuit point, and other circuits capable of outputting multi-bit binary set values.

In fig. 7, a first numerical comparator is composed of a four-bit binary numerical comparator FC1, FC1 is model 74HC 85. 3-bit binary outputs Y13, Y12 and Y11 of a statistical value Y1 of the sampling value 1 are respectively connected to input ends A2, A1 and A0 of FC1, 3-bit binary outputs Y03, Y02 and Y01 of a comparison threshold Y0 are respectively connected to input ends B2, B1 and B0 of FC1, and input ends A3 and B3 are both connected with 0. The input terminals a > B IN and a < B IN of FC1 are both connected to 0, and the input terminal a ═ B IN is connected to 1. The output terminal a < B OUT of the FC1 outputs the first set signal SE 1. The first numerical comparator in fig. 7 implements a function of outputting SE1 at a low level when the 1-sample statistical value Y1 is equal to or greater than the comparison threshold Y0, and otherwise SE1 at a high level. SE1 is active low in FIG. 7.

When the value of N is larger, 2 or more pieces of 74HC85 can be selected to form a multi-bit binary value comparator to realize the function of a first value comparator; the function of the first numerical comparator can also be realized by 1 or more four-bit binary numerical comparators CD4063, or by other combinational logic circuits. The second numerical comparator is the same as the first numerical comparator in the implementation principle circuit, and has the functions that when the statistical value Y2 of the sampling value 0 is greater than or equal to the comparison threshold Y0, the output RE1 is at a low level, otherwise, the RE1 is at a high level; RE1 is active low. RE1 may also be active high.

Fig. 8 is an RS flip-flop embodiment. In fig. 8, the nand gates FA8 and FA9 constitute an RS flip-flop, and both the first set signal SE1 and the second set signal RE1 are active low. When the SE1 is active and the RE1 is inactive, the output pulse P2 output from the in-phase output terminal FA8 is set to 1; when the SE1 is invalid and the RE1 is valid, the output pulse P2 is set to 0; when both SE1 and RE1 are inactive, the state of the output pulse P2 is unchanged. The RS flip-flop may also take other forms.

In fig. 8, the output pulse P2 and the input pulse P1 are in phase with each other. If the output pulse P2 is instead output from the inverting output, i.e., the nand gate FA9, the function changes to set the output pulse P2 to 0 when SE1 is active and RE1 is inactive; when the SE1 is invalid and the RE1 is valid, setting the output pulse P2 to be 1; when both SE1 and RE1 are inactive, the state of the output pulse P2 is unchanged; in this case, the output pulse P2 and the input pulse P1 are in an inverse correlation.

Fig. 9 is an oscillator embodiment. In fig. 9, CMOS not gates FN6 and FN7, a resistor R91, and a capacitor C91 constitute a multivibrator, and a sampling clock CLK is output from an output terminal of FN7, and the frequency of CLK can be changed by adjusting the values of the resistor R91 and the capacitor C91. The oscillator may also be implemented using other types of multivibrators.

In the above embodiment where N is 5, the comparison threshold Y0 takes a value of 4. When the number statistic Y1 of 1 sampling value is more than or equal to 4, the output SE1 is valid, the output pulse P2 is set to 1, and the essence is that when the number of '1' in the 5-bit sequence data X1 is more than or equal to 4, the output SE1 is valid, and the output pulse P2 is set to 1; when the number statistic Y2 of 0 samples is equal to or greater than 4, the output RE1 is valid, and the output pulse P2 is set to 0, which is essential that, when the number of "0" in the 5-bit sequence data X1 is equal to or greater than 4, the output RE1 is valid, and the output pulse P2 is set to 0. Since the comparison threshold Y0 is an integer greater than N/2 and equal to or less than N, the first set signal SE1 and the second set signal RE1 cannot be simultaneously asserted, and thus the output of the RS flip-flop is not indeterminate in logic state.

Fig. 10 is a schematic diagram illustrating the interference rejection of the input/output pulse when N is 5. The results of sampling the input pulse P1 with 15 sampling clock pulses CLK are shown in fig. 10, along with the resulting output pulse P2. Assuming that the 5 series data X1 sampled before sample point 1 of CLK in fig. 10 have all 0 sample values, the output pulse P2 is 0. In fig. 10, positive pulse interference occurs before sampling point 3 and after sampling point 4 of CLK in the input pulse P1, which results in that X1 samples at sampling point 3 and sampling point 4 to obtain an interference sampling value 1; the input pulse P1 has positive narrow pulse interference between sample point 5 and sample point 6 of CLK, but the positive narrow pulse width is smaller than the sampling period and between 2 sample points, and the sampling result of the sequence data X1 is not affected, i.e. the sampling process automatically filters out the positive narrow pulse interference. The input pulse P1 starts to change from 0 to 1 after the sampling point 8 of CLK, and 2 times of edge jitter occurs in the process of changing from 0 to 1, wherein the 2 nd positive narrow pulse jitter interference is automatically filtered by the sampling process, and the values of the sampling point 9 and the sampling point 10 are 1 and 0 respectively. In fig. 10, the sample value obtained at sample point 1 to sample point 15 of the sampling clock CLK for the sequence data X1 is 001100001011111. Setting the value of Y0 as 4, observing the conditions of a plurality of sampling points, wherein at the sampling point 3, Y1 is equal to 1, Y2 is equal to 4, RE1 is effective, and P2 is 0; at sample point 4, Y1 equals 2, Y2 equals 3, SE1, RE1 are both inactive, and P2 remains 0; at sample point 5, Y1 equals 2, Y2 equals 3, SE1, RE1 are both inactive, and P2 remains 0; at sample point 6, Y1 equals 2, Y2 equals 3, SE1, RE1 are both inactive, and P2 remains 0; at sample point 7, Y1 equals 2, Y2 equals 3, SE1, RE1 are both inactive, and P2 remains 0; at sample point 8, Y1 equals 1, Y2 equals 4, RE1 is active, P2 is 0; at sample point 12, Y1 equals 3, Y2 equals 2, SE1, RE1 are both inactive, and P2 remains 0; at sample point 13, Y1 equals 4, Y2 equals 1, SE1 is active, P2 is 1; obviously, in the consecutive 5 sequence data X1 values, until the sampling point 13 of fig. 10, the condition that the number of "1" in the 5-bit sequence data X1 is 4 or more is not satisfied, the first set signal SE1 is active, and the output pulse P2 changes from 0 to 1. The condition that the number of "1" s in X1 is equal to or greater than 4 is satisfied from sample point 14 to sample point 15, and the first set signal SE1 remains valid.

Fig. 10 shows the anti-glitch effect of the anti-glitch circuit unit when the input pulse P1 is 0, and the condition and process of the input pulse P1 changing from 0 to 1. Due to the symmetry of the circuit, the anti-glitch circuit unit has the same conditions and processes of anti-undershoot glitch when the input pulse P1 is 1, changing the input pulse P1 from 1 to 0, anti-positive glitch effect when the input pulse P1 is 0, and changing the input pulse P1 from 0 to 1. 5 sampling values of CLK to the input pulse P1 before a sampling point 31 of the sampling clock pulse CCLK are all 1, the output pulse P2 is 1, N-bit sequence data X1 sampled from the sampling point 31 to the sampling point 45, the statistical value Y1 of the sampling value 1 and the output pulse P2 are shown in Table 1, and the statistical value Y2 of the sampling value 0 is equal to 5-Y1 (subtracting Y1 from 5).

TABLE 1N-bit sequence data X1 for sample points 31-45, sample value 1 statistic Y1, and output pulse P2

Observing the condition of the sampling points in the table 1, at the sampling points 31-32, Y1 is more than or equal to Y0, SE1 is effective, RE1 is ineffective, and P2 is set to be 1; at sample points 33-41, Y1 was less than Y0 and Y2 was less than Y0, both SE1 and RE1 were inactive and P2 remained 1; at sample points 42-45, Y2 is equal to or greater than Y0, RE1 is active, SE1 is inactive, and P2 is set to 0.

The in-phase relationship between the output pulse P2 and the input pulse P1 is further described as an example. The working process of the anti-interference circuit unit is that when Y1 is more than or equal to Y0, namely the number of '1' in the sequence data X1 is more than or equal to Y0, the output pulse P2 is set to 1; when Y2 is equal to or more than Y0, namely the number of '0' in the sequence data X1 is equal to or more than Y0, the output pulse P2 is set to 0. Since the comparison threshold value Y0 is an integer greater than N/2 and equal to or less than N, the 2 conditions that the number of "1" s in the sequence data X1 is equal to or greater than Y0 and the number of "0" s in the sequence data X1 is equal to or greater than Y0 are not satisfied at the same time. When both the input pulse P1 and the output pulse P2 are 0, in the consecutive N times of sampling, as long as the number of "1" in the sequence data X1 is not greater than the equal Y0 due to the sampling result formed by the interference of a single or multiple positive pulses, the output pulse P2 does not become 1; when both the input pulse P1 and the output pulse P2 are 1, the output pulse P2 does not become 0 unless the number of "0" in the sequence data X1 is equal to or greater than Y0 as a result of sampling by single or multiple negative pulse disturbances in consecutive N samples. When both P1 and P2 are at low level, a positive pulse corresponding to the positive pulse in P1 can be output from P2 as long as Y0 or more of N consecutive P1 sample values are 1 due to the positive pulse in P1; when both P1 and P2 are at a high level, if the negative pulse appearing in P1 makes Y0 or more of N consecutive P1 sample values 0, the negative pulse corresponding to the negative pulse in P1 can be output from P2. After the input pulse P1 has changed from 0 to 1, or from 1 to 0, the output pulse P2 needs to change the number of "1" s in the sequence data X1 to Y0, or the number of "0" s in the sequence data X1 to Y0, before changing the output pulse P2 from 0 to 1, or changing the output pulse P2 from 1 to 0, with a delay of several sampling pulse periods. When the value of Y0 is increased within the value range, the anti-jamming circuit unit changes the conditions of the output pulse P2 from 0 to 1 and from 1 to 0 are more rigorous, the anti-jamming effect is better, but the delay time of the output pulse P2 relative to the input pulse P1 is longer; when the value of Y0 becomes smaller in the range, the interference suppression circuit unit widens the conditions of changing the output pulse P2 from 0 to 1 and from 1 to 0, and the interference suppression effect becomes smaller, but the delay time of the output pulse P2 with respect to the input pulse P1 becomes smaller. When the value of N is larger, the anti-jamming circuit unit strictly changes the conditions of changing the output pulse P2 from 0 to 1 and changing the output pulse P2 from 1 to 0, so that the anti-jamming effect is better, but the delay time of the output pulse P2 relative to the input pulse P1 is larger; when the value of N becomes small, the interference suppression circuit unit widens the conditions of changing the output pulse P2 from 0 to 1 and from 1 to 0, and the interference suppression effect becomes small, but the delay time of the output pulse P2 with respect to the input pulse P1 becomes small.

The period of the sampling clock pulse is determined according to the pulse width, the changing speed and the width of the interference-free input pulse P1. In the vehicle loading counting control system, the transportation angles of loaded goods are different, and partial goods such as cement bags and the like can be deformed, so that the narrow pulses can be disturbed by shaking at the front edge and the rear edge of the counting pulse when passing through the photoelectric switch. According to the running speed of the conveying belt and the size of the loaded goods, the effective counting pulse width is formed to be 200ms to 1000ms, and the generated narrow interference pulse is less than one tenth of the corresponding effective counting pulse width. Thus, the period of the sampling clock pulses is chosen between 30ms and 40ms, and N is in the range of 3 to 7.

All of the L-path anti-interference circuit unit shift register, the 1 sampling value counter, the 0 sampling value counter, the comparison threshold value setter, the first numerical value comparator, the second numerical value comparator, the RS trigger and the oscillator, or part of functions can be realized by adopting PAL, GAL, CPLD and FPGA, or other programmable logic devices and logic units.

When L is 2, the 2-way loading belt conveying device is driven by 2 driving motors and motor driving circuits thereof in the 2-way loading belt driving unit 11.

The human-computer interface unit 12 is used for setting the number of the counting cargos to be loaded, displaying the number of the counting cargos to be loaded and the number of the remaining counting cargos to be loaded, starting the operation of the 2-way loading belt conveyor to start loading and the like. The human interface unit 12 is preferably a touch screen but may also select other input devices such as buttons, a keyboard, a BCD dial, etc., and other output displays such as a liquid crystal display, an LED display, etc. The controller unit 10 in the embodiment of fig. 1 selects a PLC. The controller unit can also select other controllers such as a singlechip, an ARM and the like. According to the actual need of the loading system, the vehicle loading counting control system can also comprise an upper industrial personal computer for system control and management.

Except for the technical features described in the specification, the method is the conventional technology which is mastered by a person skilled in the art. For example, according to the actual requirement of a loading belt conveying device in a loading system, a driving motor in a loading belt driving unit is selected, and a corresponding motor driving circuit is designed to realize a corresponding function; selecting a human-computer interface unit and connecting the human-computer interface unit with a controller unit to realize corresponding functions according to the actual requirements of the loading system; selecting a controller unit and designing a peripheral circuit and an interface circuit thereof to realize corresponding functions; and the like, are conventional techniques known to those skilled in the art.

Claims

1. The utility model provides a vehicle loading count control system which characterized in that:

the system comprises a controller unit, a human-computer interface unit, an L-path loading belt driving unit, an L-path counting signal generating unit and an L-path anti-interference circuit unit;

the L-path loading belt driving unit is connected with the controller unit and is used for driving the L-path loading belt conveying device to operate;

the human-computer interface unit is connected with the controller unit and is used for setting and displaying the loading quantity and starting the L-way loading belt conveying device to run and start loading;

the L-path counting signal generating unit is respectively arranged on the L-path loading belt conveying device and respectively generates and outputs L-path counting initial pulses; the L paths of counting initial pulses are respectively sent to input pulse ends of the L paths of anti-interference circuit units; the output pulse end of the L-path anti-interference circuit unit is connected to the controller unit;

after the L-path loading belt conveying device is started to operate and start loading, the controller unit counts the loading number of the vehicles according to the output pulse of the L-path anti-interference circuit unit, and stops the L-path loading belt conveying device after the set loading number is reached;

l is an integer greater than or equal to 1;

the L-path anti-interference circuit units are the same anti-interference circuit units;

the anti-interference circuit unit comprises a shift register, a1 sampling value counter, a0 sampling value counter, a comparison threshold value setter, a first numerical comparator, a second numerical comparator, an RS trigger and an oscillator;

the shift register comprises a serial input end, an N-bit parallel output end and a sampling clock pulse input end, wherein the serial input end of the shift register is an input pulse end of the anti-interference circuit unit, and the N-bit parallel output end of the shift register outputs sequence data; the input of the 1 sampling value statistics device is sequence data, and the output is 1 sampling value statistics value; the input of the sampling value 0 number statistic device is sequence data, and the output is the sampling value 0 number statistic value; the output of the comparison threshold value setter is a comparison threshold value; the input of the first numerical value comparator is 1 number of statistical values and comparison threshold of sampling value, the output is the first set signal; the input of the second numerical value comparator is a sampling value 0 number statistical value and a comparison threshold value, and the output is a second set signal; the input end of the RS trigger is a first setting signal and a second setting signal, and the output end of the RS trigger is an output pulse end of the anti-interference circuit unit; the oscillator outputs a sampling clock pulse;

the sequence data is the latest N times sampling value of the shift register to the input pulse at the edge of the sampling clock pulse, the sampling value is binary data 0 or 1, and N is an integer greater than or equal to 2; the comparison threshold is an integer which is greater than N/2 and less than or equal to N;

the function of the 1 sampling value statistic device is that 1 output sampling value statistic is the number value of the number of '1' in the input sequence data; the function of the sampling value 0 number statistical device is that the output sampling value 0 number statistical value is the number value of '0' number in the input sequence data;

2. The vehicle loading count control system according to claim 1, characterized in that: and the L-path counting signal generating units are all photoelectric switch sensors.

3. The vehicle loading count control system according to claim 1, characterized in that: the controller unit is a programmable controller.

4. The vehicle loading count control system according to any one of claims 1 to 3, characterized in that: the first setting signal is a setting signal of the RS trigger, and the second setting signal is a reset signal of the RS trigger; the output pulse is output from the non-inverting output terminal of the RS trigger, and the output pulse is output from the inverting output terminal of the RS trigger.