CN107819446A - High PSRR operational amplification circuit - Google Patents
High PSRR operational amplification circuit Download PDFInfo
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- CN107819446A CN107819446A CN201610825131.2A CN201610825131A CN107819446A CN 107819446 A CN107819446 A CN 107819446A CN 201610825131 A CN201610825131 A CN 201610825131A CN 107819446 A CN107819446 A CN 107819446A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/471—Indexing scheme relating to amplifiers the voltage being sensed
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Abstract
The invention discloses a kind of high PSRR operational amplification circuit,Including current offset sub-circuit,The first order amplification sub-circuit being connected with the current offset sub-circuit,Amplify sub-circuit in the second level being connected with first order amplification sub-circuit,It is connected between the first order amplification sub-circuit and second level amplification sub-circuit and is used to improve the high PSRR sub-circuit of the PSRR of the high PSRR operational amplification circuit and be connected to the first order to amplify the compensating electric capacity for being used for control loop stability between sub-circuit and second level amplification sub-circuit,The current offset sub-circuit provides bias current for the high PSRR operational amplification circuit,The first order amplification sub-circuit receives the differential signal of input and the second level amplification sub-circuit is sent to after being amplified,The second level amplification sub-circuit exports after being amplified to the signal received.The present invention improves the PSRR of the high band part of operational amplification circuit.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to a kind of digital display circuit high band part for analog circuit
High PSRR operational amplification circuit.
Background technology
Operational amplification circuit is circuit module indispensable in communication and High Speed Analog converting system, in some high speed numbers
In type families system, requirement of the circuit for PSRR (PSRR, Power Supply Rejection Ratio) is often than one
As system it is high.
In the prior art, the stabilization of loop is generally reached using miller-compensated technology to two-stage calculation amplifying circuit,
Although the PSRR of circuit can be designed to sufficiently high in low-frequency range, the power supply of circuit suppresses during for high band
Than being then unable to reach requirement, therefore limit application of the operational amplification circuit in digital display circuit.
Therefore, it is necessary to provide a kind of high PSRR computing of the digital display circuit high band part for analog circuit
Amplifying circuit.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of digital display circuit high frequency for analog circuit
The high PSRR operational amplification circuit of section part.
The purpose of the present invention is achieved through the following technical solutions：A kind of high PSRR operational amplification circuit,
The first order being connected including current offset sub-circuit, with the current offset sub-circuit is amplified sub-circuit, put with the first order
The connected second level amplification sub-circuit of big sub-circuit, it is connected to the first order amplification sub-circuit and second level amplification son electricity
Between road be used for improve the high PSRR operational amplification circuit PSRR high PSRR sub-circuit and
It is connected to the compensation for being used for control loop stability between the first order amplification sub-circuit and second level amplification sub-circuit
Electric capacity, the current offset sub-circuit provide bias current, the first order for the high PSRR operational amplification circuit
Amplification sub-circuit receives the differential signal of input and the second level amplification sub-circuit, the second level is sent to after being amplified
Amplification sub-circuit exports after being amplified to the signal received.
Second effect that the first order amplification sub-circuit includes the first FET, is connected with first FET
Ying Guan, the 3rd FET, the 4th FET being connected with the 3rd FET, first FET with it is described
Second FET is for receiving the Differential Input of the differential signal of input to pipe, and the second level amplification sub-circuit includes the
Five FETs, the current offset sub-circuit include the 6th FET, be connected with the 6th FET the 7th
Effect pipe, the 8th FET being connected with the 7th FET, the 9th effect being connected with the 8th FET
Ying Guan, the tenth FET being connected with the 9th FET, the 11st effect being connected with the 7th FET
Ying Guan, the 12nd FET being connected with the 8th FET, be connected with the 9th FET the 13rd
Effect pipe, the 14th FET being connected with the tenth FET, be connected with the 11st FET the tenth
Five FETs, the 16th FET being connected with the 15th FET, it is connected with the 16th FET
The 17th FET, be connected with the 17th FET the 18th FET, with the 18th field-effect
Pipe connected the 19th FET and the 20th FET, the high PSRR sub-circuit include the described ten effect
Ying Guan, the 14th FET, the 19th FET, it is connected to the 14th FET and the described tenth
The 21st FET and the first electric capacity between nine FETs, the compensating electric capacity include the second electric capacity.
The grid of the grid of first FET and second FET receives the differential signal of input respectively,
The source class of first FET is connected the drain electrode of the 6th FET with the source class of second FET jointly,
The drain electrode of first FET is connected with the drain electrode of the source class and the 18th FET of the 4th FET.
The drain electrode of second FET and the source class of the 3rd FET and the 17th FET
Drain electrode is connected；The grid of 3rd FET, grid, the grid of the 15th FET of the 4th FET
The grid of pole and the 21st FET connects jointly, drain electrode and the 7th field-effect of the 3rd FET
The grid of pipe, the draining of the 11st FET, the drain electrode of the 12nd FET and the 15th field-effect
The drain electrode of pipe is connected.
The drain electrode of 4th FET and the draining of the 13rd FET, the 14th FET
Drain electrode, one end of first electric capacity, the grid of the 5th FET and the drain electrode phase of the 21st FET
Even；The drain electrode of 5th FET is connected with the drain electrode of the 20th FET and one end of second electric capacity,
And as the output end output signal of the high PSRR operational amplification circuit of the present invention；The grid of 6th FET
Pole, the grid of the 8th FET, the grid of the grid of the 9th FET and the tenth FET are common
Connection.
The drain electrode of 7th FET is connected with the source class of the 11st FET；8th FET
Drain electrode be connected with the source class of the 12nd FET；The drain electrode of 9th FET and the 13rd field-effect
The source class of pipe is connected；The drain electrode of tenth FET is connected with the source class of the 14th FET；Described 11st
The grid of FET, the grid of the 12nd FET, the grid and the described 14th of the 13rd FET
The grid of FET connects jointly；The drain electrode phase of the source class and the 16th FET of 15th FET
Even.
The grid of 16th FET, grid, the 18th FET of the 17th FET
Grid, the grid of the 19th FET and the grid of the 20th FET connect jointly；Described 19th
The drain electrode of FET is connected with the source class of the 21st FET and the other end of second electric capacity.
The source class of 6th FET, the source class of the 7th FET, the 8th FET source class,
The source class of 9th FET, the source class of the tenth FET, the other end and the described 5th of first electric capacity
The source class of FET connects power end jointly；The source class of 16th FET, the source of the 17th FET
Level, the source class of the 18th FET, the source class of the 19th FET and the source of the 20th FET
The common connection ground terminal of level.
First FET, second FET, the 5th FET, the 6th FET,
7th FET, the 8th FET, the 9th FET, the tenth FET, the described tenth
One FET, the 12nd FET, the 13rd FET, the 14th FET are imitated for p-type field
Ying Guan, the 3rd FET, the 4th FET, the 15th FET, the 16th FET,
17th FET, the 18th FET, the 19th FET, the 20th FET,
21st FET is N-type FET.
The beneficial effects of the invention are as follows：The PSRR of the high band part of operational amplification circuit is improved, is computing
Amplifying circuit is applied to provide solution in High Speed System.
Brief description of the drawings
Fig. 1 is the structured flowchart of high PSRR operational amplification circuit of the present invention；
Fig. 2 is the particular circuit configurations figure of high PSRR operational amplification circuit of the present invention.
Embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to
It is as described below.
As shown in figure 1, high PSRR operational amplification circuit of the present invention includes current offset sub-circuit and current offset
The connected first order amplification sub-circuit of sub-circuit, the second level amplification sub-circuit being connected with first order amplification sub-circuit, it is connected to
The first order amplifies the high PSRR sub-circuit between sub-circuit and second level amplification sub-circuit and is connected to first order amplification
Compensating electric capacity between sub-circuit and second level amplification sub-circuit.
Wherein, current offset sub-circuit is used to provide bias current, the first order for high PSRR operational amplification circuit
Amplification sub-circuit is used to receive the differential signal of input and amplification sub-circuit in the second level is sent to after being amplified, and can be high power supply
Rejection ratio operational amplification circuit provides high gain, and second level amplification sub-circuit exports after being amplified to the signal received,
And enough output voltage swings are provided for high PSRR operational amplification circuit, high PSRR sub-circuit is used to improve high electricity
The PSRR of source rejection ratio operational amplification circuit, compensating electric capacity are the compensating electric capacity for control loop stability.
Please refer to Fig. 2, Fig. 2 is the particular circuit configurations figure of high PSRR operational amplification circuit of the present invention.
In the present invention, first order amplification sub-circuit includes the first FET M1, the second field-effect being connected with the first FET M1
Pipe M2, the 3rd FET M3, the 4th FET M4 being connected with the 3rd FET M3, the first FET M1, second
FET M2, the 3rd FET M3 and the 4th FET M4 have collectively constituted the first order amplification of Foldable cascade
Sub-circuit, wherein, the first FET M1 and the second FET M2 be Differential Input to pipe, for receiving the difference letter of input
Number；Second level amplification sub-circuit includes the 5th FET M5；Current offset sub-circuit includes the 6th FET M6 and the 6th
Connected FET M6 the 7th FET M7, the 8th FET M8 being connected with the 7th FET M7 and the 8th
Connected effect pipe M8 the 9th FET M9, the tenth FET M10 being connected with the 9th FET M9 and the 7th are imitated
The 11st FET M11 that should be connected pipe M7, the 12nd FET M12 and the 9th being connected with the 8th FET M8
Connected FET M9 the 13rd FET M13, the 14th FET M14 being connected with the tenth FET M10 and
Connected 11st FET M11 the 15th FET M15, the 16th to be connected with the 15th FET M15 are imitated
Should pipe M16, be connected with the 16th FET M16 the 17th FET M17, be connected with the 17th FET M17
18th FET M18, with the 18th FET M18 the 19th FET M19 being connected and the 20th FET
M20；High PSRR sub-circuit includes the tenth FET M10, the 14th FET M14, the 19th FET
M19, the 21st FET M21 and first being connected between the 14th FET M14 and the 19th FET M19
Electric capacity CAP1；Compensating electric capacity includes the second electric capacity CAP2.
The physical circuit annexation of high PSRR operational amplification circuit of the present invention is as follows：First FET M1's
Grid and the second FET M2 grid receive differential signal INP, INN of input, the first FET M1 source class respectively
With the common drain electrode for being connected the 6th FET M6 of the second FET M2 source class, the first FET M1 drain electrode and the 4th
FET M4 source class and the 18th FET M18 drain electrode are connected；Second FET M2 drain electrode and the 3rd effect
Should the pipe M3 drain electrode of source class and the 17th FET M17 be connected；3rd FET M3 grid, the 4th FET M4
Grid, the 15th FET M15 grid and the 21st FET M21 grid connect jointly, and receive biasing
Voltage VB3, the 3rd FET M3 drain electrode and the drain electrode of the 7th FET M7 grid, the 11st FET M11, the
12 FET M12 drain electrode and the 15th FET M15 drain electrode are connected；4th FET M4 drain electrode and the tenth
Three FET M13 drain electrode, the 14th FET M14 drain electrode, the first electric capacity CAP1 one end, the 5th FET M5
Grid and the 21st FET M21 drain electrode be connected；5th FET M5 drain electrode and the 20th FET M20
Drain electrode and the second electric capacity CAP2 one end be connected, and as the output end of high PSRR operational amplification circuit of the present invention
OUT output signals；6th FET M6 grid, the 8th FET M8 grid, the 9th FET M9 grid and
Tenth FET M10 grid connects jointly, and receives bias voltage VB1；7th FET M7 drain electrode and the 11st
FET M11 source class is connected；8th FET M8 drain electrode is connected with the 12nd FET M12 source class；9th
FET M9 drain electrode is connected with the 13rd FET M13 source class；Tenth FET M10 drain electrode with the 14th
Effect pipe M14 source class is connected；11st FET M11 grid, the 12nd FET M12 grid, the 13rd
Effect pipe M13 grid and the 14th FET M14 grid connect jointly, and receive bias voltage VB2；15th effect
Should pipe M15 source class be connected with the 16th FET M16 drain electrode；16th FET M16 grid, the 17th effect
Should pipe M17 grid, the 18th FET M18 grid, the 19th FET M19 grid and the 20th FET
M20 grid connects jointly, and receives bias voltage VB4；19th FET M19 drain electrode and the 21st FET
M21 source class and the second electric capacity CAP2 other end are connected；6th FET M6 source class, the 7th FET M7 source
Level, the 8th FET M8 source class, the 9th FET M9 source class, the tenth FET M10 source class, the first electric capacity
The CAP1 other end and the 5th FET M5 source class connect power end AVDD jointly；16th FET M16 source class,
17th FET M17 source class, the 18th FET M18 source class, the 19th FET M19 source class and second
Ten FET M20 source class connects ground terminal AGND jointly.
Wherein, in the present embodiment, the first FET M1, the second FET M2, the 5th FET M5, the 6th
Effect pipe M6, the 7th FET M7, the 8th FET M8, the 9th FET M9, the tenth FET M10, the 11st
FET M11, the 12nd FET M12, the 13rd FET M13, the 14th FET M14 are p-type field-effect
Pipe, the 3rd FET M3, the 4th FET M4, the 15th FET M15, the 16th FET M16, the 17th
Effect pipe M17, the 18th FET M18, the 19th FET M19, the 20th FET M20, the 21st effect
Should pipe M21 be N-type FET, in other embodiments, above-mentioned FET can be other structures can realize identical work(
The component of energy, however it is not limited to this.
The operation principle of high PSRR operational amplification circuit of the present invention is as follows：
Differential signal INP, INN are separately input into the first FET M1 and second effect in first order amplification sub-circuit
Should pipe M2, current offset sub-circuit produces the bias current needed for whole circuit, to ensure the field-effect in operational amplification circuit
Guan Jun works in normal zone of saturation, the first FET M1, the second FET M2, the 3rd FET M3 and the 4th effect
Should pipe M4 constitute folding cascade the first order amplification sub-circuit, input differential signal by the first order amplification son electricity
Road is exported after being amplified with second level amplification sub-circuit by output end OUT.First order amplification sub-circuit is operational amplification circuit
Provide high gain, the first electric capacity CAP1 in high PSRR sub-circuit ensure that the digital display circuit high frequency of analog circuit
The FET gate source voltage of section part does not change and changed with power supply signal, and high PSRR sub-circuit prevents circuit
Output coupling improves the PSRR of high PSRR operational amplification circuit to power supply, and compensating electric capacity CAP2 is improved
Loop stability, second level amplification sub-circuit provide enough output voltage swings for high PSRR operational amplification circuit.
High PSRR operational amplification circuit of the present invention is folded by the input pattern of differential pair tube, while using electric current
Technology carries high-tension output voltage swing, isolates the coupling of Compensation Feedback electricity on the common grid end of folding two identical roads in parallel
Hold path, so as to reach the purpose for improving PSRR, then the bias current source and drain by electric capacity from output coupling to folding
The phase margin of compensation loop is carried out at end, therefore the present invention can press down the power supply of the digital display circuit high band part of analog circuit
System ratio brings up to -30 to -40dB or so, is applied to provide solution in High Speed System for operational amplification circuit.
In summary, high PSRR operational amplification circuit of the present invention improves the high band part of operational amplification circuit
PSRR, for operational amplification circuit be applied to High Speed System in provide solution.
Claims (9)
- A kind of 1. high PSRR operational amplification circuit, it is characterised in that：The high PSRR operational amplification circuit bag Include current offset sub-circuit, the first order being connected with current offset sub-circuit amplification sub-circuit, amplify with the first order The connected second level amplification sub-circuit of sub-circuit, it is connected to the first order amplification sub-circuit and second level amplification sub-circuit Between be used for improve the high PSRR operational amplification circuit PSRR high PSRR sub-circuit and company It is connected to the compensation electricity for being used for control loop stability between the first order amplification sub-circuit and second level amplification sub-circuit Hold, the current offset sub-circuit provides bias current for the high PSRR operational amplification circuit, and the first order is put Big sub-circuit receives the differential signal of input and the second level amplification sub-circuit is sent to after being amplified, and the second level is put Big sub-circuit exports after being amplified to the signal received.
- 2. high PSRR operational amplification circuit according to claim 1, it is characterised in that：The first order amplification Circuit include the first FET, the second FET being connected with first FET, the 3rd FET, with it is described The 4th connected FET of 3rd FET, first FET are defeated for receiving with second FET The Differential Input of the differential signal entered includes the 5th FET, the current offset to pipe, the second level amplification sub-circuit Sub-circuit includes the 6th FET, the 7th FET being connected with the 6th FET and the 7th field-effect The 8th connected FET of pipe, the 9th FET being connected with the 8th FET and the 9th FET Connected the tenth FET, the 11st FET being connected with the 7th FET, with the 8th FET Connected the 12nd FET, the 13rd FET being connected with the 9th FET, with the tenth field-effect The 14th connected FET of pipe, the 15th FET and the described 15th being connected with the 11st FET The 16th connected FET of FET, the 17th FET being connected with the 16th FET, with it is described The 18th connected FET of 17th FET, the 19th FET being connected with the 18th FET and 20th FET, the high PSRR sub-circuit include the tenth FET, the 14th FET, 19th FET, the 21st be connected between the 14th FET and the 19th FET FET and the first electric capacity, the compensating electric capacity include the second electric capacity.
- 3. high PSRR operational amplification circuit according to claim 2, it is characterised in that：First FET The grid of grid and second FET receive the differential signal of input respectively, the source class of first FET with The source class of second FET connects the drain electrode of the 6th FET jointly, the drain electrode of first FET with The drain electrode of the source class and the 18th FET of 4th FET is connected.
- 4. high PSRR operational amplification circuit according to claim 3, it is characterised in that：Second FET Drain electrode be connected with the drain electrode of the source class and the 17th FET of the 3rd FET；3rd FET Grid, the grid of the 4th FET, the grid of the 15th FET and the 21st FET Grid connect jointly, drain electrode and the grid of the 7th FET, the 11st effect of the 3rd FET Should the draining of pipe, the drain electrode of the 12nd FET and the drain electrode of the 15th FET are connected.
- 5. high PSRR operational amplification circuit according to claim 4, it is characterised in that：4th FET Drain electrode and the draining of the 13rd FET, the draining of the 14th FET, one end of first electric capacity, The drain electrode of the grid and the 21st FET of 5th FET is connected；The drain electrode of 5th FET One end of drain electrode and second electric capacity with the 20th FET is connected, and suppresses as the high power supply of the present invention Than the output end output signal of operational amplification circuit；The grid of 6th FET, the grid of the 8th FET, The grid of 9th FET and the grid of the tenth FET connect jointly.
- 6. high PSRR operational amplification circuit according to claim 5, it is characterised in that：7th FET Drain electrode be connected with the source class of the 11st FET；The drain electrode of 8th FET and the 12nd field-effect The source class of pipe is connected；The drain electrode of 9th FET is connected with the source class of the 13rd FET；Described ten The drain electrode of effect pipe is connected with the source class of the 14th FET；The grid of 11st FET, the described tenth The grid of the grid of two FETs, the grid of the 13rd FET and the 14th FET connects jointly； The source class of 15th FET is connected with the drain electrode of the 16th FET.
- 7. high PSRR operational amplification circuit according to claim 6, it is characterised in that：16th field-effect The grid of pipe, the grid of the 17th FET, grid, the 19th FET of the 18th FET Grid and the grid of the 20th FET connect jointly；The drain electrode and the described 20th of 19th FET The other end of the source class of one FET and second electric capacity is connected.
- 8. high PSRR operational amplification circuit according to claim 7, it is characterised in that：6th FET Source class, the source class of the 7th FET, the source class of the 8th FET, the 9th FET source class, The source class of the source class of tenth FET, the other end of first electric capacity and the 5th FET connects electricity jointly Source；The source class of 16th FET, the source class of the 17th FET, the source of the 18th FET The source class of level, the source class of the 19th FET and the 20th FET connects ground terminal jointly.
- 9. high PSRR operational amplification circuit according to claim 2, it is characterised in that：First field-effect Pipe, second FET, the 5th FET, the 6th FET, the 7th FET, described It is eight FETs, the 9th FET, the tenth FET, the 11st FET, described 12nd Effect pipe, the 13rd FET, the 14th FET are p-type FET, the 3rd FET, institute State the 4th FET, the 15th FET, the 16th FET, the 17th FET, described 18th FET, the 19th FET, the 20th FET, the 21st FET are N Type FET.
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|---|---|---|---|
| CN201610825131.2A CN107819446A (en) | 2016-09-14 | 2016-09-14 | High PSRR operational amplification circuit |
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| CN201610825131.2A CN107819446A (en) | 2016-09-14 | 2016-09-14 | High PSRR operational amplification circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112821875A (en) * | 2019-11-15 | 2021-05-18 | 北京兆易创新科技股份有限公司 | Amplifier circuit |
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