CN107743101B - Data forwarding method and device - Google Patents
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Abstract
The invention provides a data forwarding method and a device, wherein the method comprises the following steps: if the first storage module needs to forward data, a request instruction is sent to the control module through the first storage module; if the control module receives the request instruction, determining a first output port and a first index value for a first input port corresponding to the first storage module through the control module; sending a response instruction carrying a first index value to a first storage module through a control module; if the first storage module receives the response instruction, the first storage module sends data to be forwarded and a first index value to the control module; determining, by the control module, a first egress port based on the first index value; and forwarding the data to a second storage module corresponding to the first output port through the control module. By applying the embodiment of the invention, the parallel processing of a plurality of data forwarding processing processes can be realized through the control module, the overall processing performance of the FPGA chip is greatly improved, and the processing efficiency is high.
Description
Technical Field
The present invention relates to the field of network communication technologies, and in particular, to a data forwarding method and apparatus.
Background
Generally, an FPGA chip includes a plurality of memory modules, and data needs to be forwarded between different memory modules. Due to the large number of memory modules, how to efficiently forward data among different memory modules becomes a crucial issue.
In the prior art, data to be forwarded stored in a plurality of storage modules is sequentially stored in a transition module, and the transition module sequentially forwards the data to be forwarded to the corresponding storage module. The forwarding speed of the FPGA chip depends on the processing speed of the transition module. Due to the limitation of the processing speed of the transition module, the overall processing performance of the FPGA chip is greatly reduced, and the processing efficiency is low.
Disclosure of Invention
In view of this, the present invention provides a method and an apparatus for forwarding data, where a control module determines a first output port for a first input port, and a processing procedure of forwarding multiple data can implement parallel processing through the control module, so as to solve the problems of low processing efficiency and overall processing performance of an FPGA chip.
In order to achieve the purpose, the invention provides the following technical scheme:
according to a first aspect of the present invention, a method for forwarding data is provided, where the method includes:
if a first storage module needs to forward data, a request instruction is sent to the control module through the first storage module, and the first storage module is one of the storage modules;
if the control module receives the request instruction, determining a first output port and a first index value for a first input port corresponding to the first storage module through the control module;
sending a response instruction carrying the first index value to the first storage module through the control module;
if the first storage module receives the response instruction, sending data to be forwarded and the first index value to the control module through the first storage module;
determining, by the control module, the first egress port based on the first index value;
and forwarding the data to a second storage module corresponding to the first output port through the control module, where the second storage module is one of the plurality of storage modules.
According to a second aspect of the present invention, there is provided a data forwarding apparatus, including: the device comprises a control module and a plurality of storage modules;
the first storage module is configured to send a request instruction to the control module if the first storage module needs to forward data, and the first storage module is one of the plurality of storage modules;
the control module is configured to determine a first output port and a first index value for a first input port corresponding to the first storage module if the request instruction is received, and send a response instruction carrying the first index value to the first storage module;
the first storage module is further configured to send data to be forwarded and the first index value to the control module if the response instruction is received;
the control module is further configured to determine the first egress port based on the first index value, and forward the data to a second storage module corresponding to the first egress port, where the second storage module is one of the plurality of storage modules.
According to the technical scheme, the FPGA chip determines a corresponding first output port and a first index value for the first input port through the control module, the FPGA chip sends the first index value to the first storage module corresponding to the first input port through the control module to trigger the first storage module to start sending data to the control module, when the control module receives the data, the FPGA chip finds the first output port through the control module based on the first index value, and sends the data to the second storage module corresponding to the first output port through the control module. The control module determines a first output port for the first input port, and the processing processes of multiple data forwarding can be processed in parallel through the control module, so that the overall processing performance of the FPGA chip is greatly improved, and the processing efficiency is high.
Drawings
Fig. 1A is a flowchart of an embodiment of a data forwarding method provided in the present invention;
FIG. 1B is an exemplary scene diagram of the embodiment shown in FIG. 1A;
FIG. 2 is a flow chart of another embodiment of a data forwarding method provided in the present invention;
fig. 3 is a flowchart of an embodiment of a forwarding method of data according to the present invention;
FIG. 4 is a hardware structure diagram of an FPGA chip provided by the present invention;
fig. 5 is a block diagram of an embodiment of a data forwarding apparatus provided in the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present invention. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Fig. 1A is a flowchart of an embodiment of a data forwarding method provided in the present invention; FIG. 1B is an exemplary scene diagram of the embodiment shown in FIG. 1A. The data forwarding method can be applied to an FPGA chip, and the FPGA chip comprises the following steps: the device comprises a control module and a plurality of storage modules. The control module may be a module having a control function in an FPGA chip, and the storage module may be an FIFO memory, as shown in fig. 1A, including the following steps:
step 101: and if the first storage module needs to forward the data, sending a request instruction to the control module through the first storage module, wherein the first storage module is one of the plurality of storage modules.
Step 102: if the control module receives the request instruction, the control module determines a first output port and a first index value for a first input port corresponding to the first storage module.
Step 103: and sending a response instruction carrying the first index value to the first storage module through the control module.
Step 104: and if the first storage module receives the response instruction, sending the data to be forwarded and the first index value to the control module through the first storage module.
Step 105: determining, by the control module, a first egress port based on the first index value.
Step 106: and forwarding data to a second storage module corresponding to the first output port through the control module, wherein the second storage module is one of the plurality of storage modules.
In step 101, in an embodiment, it is understood by those skilled in the art that the storage module and the data stored in the storage module need to be forwarded to each other. If one of the plurality of memory modules needs to forward data, the one of the plurality of memory modules is the first memory module. The FPGA chip sends a request instruction for forwarding data to the control module through the first storage module.
In step 102, in an embodiment, if the control module receives the request instruction, the FPGA chip determines, through the control module, a first output port for a first input port corresponding to the first storage module, where the first output port is used to subsequently forward data to be forwarded in the first storage module, the first input port is, for example, 00, and the first output port is, for example, 55; the FPGA chip determines a corresponding first index value for the first storage module through the control module, where the first index value is used for corresponding to the first input port and the first output port, and the first index value is, for example, 2. Specifically, the step of determining the first output port and the first index value for the first input port corresponding to the first storage module by the FPGA chip through the control module is described in the following related description of step 201 to step 202, which is not repeated herein. It should be noted that, when the first index value determines the corresponding relationship between the first input port and the first output port, the control module stops receiving the request command from the first input port, so as to avoid a conflict caused by the plurality of memory modules sending the request command to the control module through the first input port at the same time.
In step 103, in an embodiment, the FPGA chip sends a response instruction carrying the first index value to the first storage module through the control module, which indicates that the FPGA chip has already established the first input port and the first output port corresponding to the first index value through the control module.
In step 104, in an embodiment, if the first storage module receives the response instruction, which indicates that the FPGA chip has already determined the first output port for the first input port corresponding to the first storage module through the control module and can perform data forwarding, the FPGA chip sends the data to be forwarded and the first index value to the control module through the first storage module.
In step 105, in an embodiment, in combination with step 102, the FPGA chip determines, by the control module, the first egress port 55 corresponding to the first ingress port 00 based on the first index value 2.
In step 106, in an embodiment, the second storage module is a storage module corresponding to the first egress port, and the second storage module is one of the plurality of storage modules. The FPGA chip forwards data to a second storage module corresponding to the first output port through the control module, and the second storage module stores the data. The FPGA chip forwards data through the control module, so that the forwarding speed of the data and the forwarding sequence of the data can be controlled to a certain extent.
Specifically, in combination with the exemplary scenario diagram shown in fig. 1B, taking the storage module as a FIFO register, the FPGA chip 11 includes 6 storage modules in total, namely, the control module 111, the FIFO register 112, the FIFO register 113, the FIFO register 114, the FIFO register 115, the FIFO register 116, and the FIFO register 117. The control module 111 includes an ingress port 1111, an ingress port 1112, an ingress port 1113, an egress port 1114, and an egress port 1115. If the FIFO register 112 (which can be regarded as the first memory module in this application) needs to forward data, the FIFO register 112 requests the control module 111 to establish a data forwarding path for the FIFO register 112 through the request instruction sent from the ingress port 1111 (which can be regarded as the first ingress port in this application) to the control module 111. The control module 111 determines an egress port and a first index value for the ingress port 1111 from the egress port 1114 and the egress port 1115, for example, determines the port 1114 (which may be referred to as a first egress port in this application) and the first index value 2, and the control module 111 establishes a forwarding path from the ingress port 1111 to the egress port 1114 for data forwarding in the FIFO register 112, where the first index value 2 corresponds to the forwarding path. The control module 111 sends a response instruction carrying the first index value 2 to the FIFO register 112, which indicates that the data forwarding path is determined and data can be transmitted. The FIFO register 112 receives the response instruction, and sends the data to be forwarded and the first index value 2 to the control module 111. The control module 111 determines the corresponding egress port 1114 based on the first index value of 2. The control module 111 forwards data to the FIFO register 116 (which may be considered a second storage module in this application) corresponding to the egress port 1114.
In the embodiment of the invention, the FPGA chip determines a corresponding first output port and a first index value for a first input port through a control module, the FPGA chip sends the first index value to a first storage module corresponding to the first input port through the control module to trigger the first storage module to start sending data to the control module, when the control module receives the data, the FPGA chip finds the first output port through the control module based on the first index value, and the FPGA chip sends the data to a second storage module corresponding to the first output port through the control module. The control module determines a first output port for the first input port, and the processing processes of multiple data forwarding can be processed in parallel through the control module, so that the overall processing performance of the FPGA chip is greatly improved, and the processing efficiency is high.
Fig. 2 is a flowchart of another embodiment of a data forwarding method provided by the present invention, which exemplarily illustrates how an FPGA chip determines a first egress port and a first index value for a first ingress port corresponding to a first storage module through a control module, as shown in fig. 2, the method includes the following steps:
step 201: determining, by the control module, a first index value from at least one second index value recorded in the first preset list based on a first preset rule.
Step 202: and determining, by the control module, the first egress port from the at least one second egress port recorded in the second preset list based on a second preset rule.
Step 203: and establishing a corresponding relation among the first input port, the first output port and the first index value through the control module.
In step 201, at least one second index value is recorded in the first preset list, and each second index value may be used to correspond to a corresponding relationship between a pair of ingress/egress ports, so that the control module may provide support for port corresponding relationship for forwarding multiple data at the same time. The first preset rule may be: and preferentially selecting the second index value which does not record the corresponding relation. As shown in table 1, a structure example of the first preset list is:
TABLE 1
| Second index value | Input port | Output port |
| 1 | 44 | 33 |
| 2 | - | - |
| 3 | - | - |
The second index values in table 1 include three second index values 1, 2, and 3, where the second index value 1 corresponds to the ingress port 44 and the egress port corresponds to the egress port 33. "-" indicates that the corresponding ingress/egress port has not been determined. The FPGA chip is based on a first preset rule through the control module: the second index value with no recorded correspondence is preferentially selected, and the first index value is determined to be 2 from the second index values 1, 2, and 3 recorded in the first preset list shown in table 1.
In step 202, the FPGA chip determines, through the control module, the first output port from at least one second output port recorded in the second preset list based on the second preset rule. Each of the at least one second egress port recorded in the second preset list corresponds to a state identifier, each second egress port also corresponds to a called number, and the control module determines the first egress port based on the state identifier corresponding to each second egress port and the called number of the port, specifically, the state identifier is used to indicate an occupation situation of the port, for example, the state identifier "1" indicates that the port is occupied, and the state identifier "0" indicates that the port is idle. The second preset rule may be: and preferentially selecting ports in an idle state and ports with less called times. As shown in table 2, a structure example of the second preset list is:
TABLE 2
| Second output port | Status identification | Number of |
| 55 | 0 | 1 |
| 77 | 1 | 4 |
| 22 | 0 | 3 |
The second egress port in table 2 includes 22, 55, 77, where the state identifier corresponding to the second egress port 55 is "0", and the number of calls is "1"; the state identifier corresponding to the second egress port 77 is "1", and the number of calls is "4"; the state flag corresponding to the second egress port "22" is "0", and the number of calls is "3". According to a second preset rule: if the port in the idle state and the port with the smaller number of times of being called are selected preferentially, the second egress port 55 is determined as the first egress port.
In step 203, the FPGA chip establishes a corresponding relationship among the first input port, the first output port, and the first index value through the control module, where the corresponding relationship may be recorded in a first preset list shown in table 1. With reference to steps 201 to 202, taking the first ingress port as 00, the first egress port as 55, and the first index value as 2 as an example, the FPGA chip records the first ingress port 00, the first egress port 55, and the first index value as 2 in the first preset list through the control module, as shown in table 3, which is an example after the corresponding relationship is recorded in the first preset list:
TABLE 3
| Second index value | Input port | Output port |
| 1 | 44 | 33 |
| 2 | 00 | 55 |
| 3 | - | - |
In table 3, the FPGA chip records the correspondence between the first input port 00, the first output port 55, and the first index value of 2 in the first preset list through the control module.
In the embodiment of the invention, the FPGA chip determines a first index value based on a first preset rule through the control module, determines a first output port based on a second preset rule through the control module, and can select different ports according to requirements by adjusting the first preset rule and the second preset rule; the control module establishes the corresponding relation among the first input port, the first output port and the first index value, can record the corresponding relation of the input/output ports in the first preset list, and can master the service condition of the input/output ports and adjust the number of the input/output ports in time by acquiring the first preset list.
Fig. 3 is a flowchart of an embodiment of a further data forwarding method provided by the present invention, and in the embodiment of the present invention, with reference to fig. 1A and fig. 2, on the basis of steps 101 to 106, a processing situation after the FPGA chip executes a step of forwarding data to a second storage module corresponding to a first egress port through a control module is exemplarily described, as shown in fig. 3, the method includes the following steps:
step 301: and detecting whether the data carries an end identifier for marking the end of the data or not through a second storage module.
Step 302: and when the second storage module detects that the data carries the ending mark, ending the storage of the data.
Step 303: and sending an ending instruction for ending forwarding to the control module through the second storage module.
Step 304: if the control module receives the end instruction, the control module releases the corresponding relation among the first input port, the first output port and the first index value.
Step 305: and judging whether the residual storage space of the second storage module is less than or equal to the preset storage space through the control module.
Step 306: and when the residual storage space of the second storage module is less than or equal to the preset storage space, setting the state of the first output port to be idle through the control module.
In step 301, the FPGA chip detects whether the received data carries an end identifier for marking the end of the data through the second storage module. As will be understood by those skilled in the art, each packet has an end flag, which may be, for example: 1111. 0000, and the like.
In step 302, when the FPGA chip detects that the data carries the end identifier through the second storage module, the storage of the data is ended.
In step 303, the FPGA chip sends an end instruction for ending forwarding to the control module through the second storage module, so that the control module stops sending data to the second storage module.
In step 304, if the control module receives the end instruction, the FPGA chip releases the corresponding relationship between the first input port, the first output port, and the first index value through the control module. Specifically, referring to table 3 in fig. 2, on the basis of table 3, as shown in table 4, a first preset list example after the correspondence relationship between the first ingress port, the first egress port, and the first index value is released is shown:
TABLE 4
| Second index value | Input port | Output port |
| 1 | 44 | 33 |
| 2 | - | - |
| 3 | - | - |
In table 4, the first egress port 55 of the first ingress port 00 in the first preset list is deleted.
In step 305, after the step of removing the corresponding relationship between the first input port, the first output port, and the first index value by the FPGA chip through the control module, the FPGA chip determines whether the remaining storage space of the second storage module is less than or equal to the preset storage amount through the control module. The preset storage amount is the lowest threshold value at which the second storage module can continue to receive data, that is, the second storage module is larger than the preset storage amount, so that the data can be ensured to continue to be received and stored.
In step 306, when the remaining storage space of the second storage module is greater than the preset storage amount, it indicates that the second storage module has sufficient storage space and can continue to receive and store data, so that the FPGA chip sets the state of the first egress port to idle through the control module, specifically, in combination with the related description of step 202, for example, the state identifier "1" indicates that the port is occupied, the state identifier "0" indicates that the port is idle, and the state identifier corresponding to the first egress port is set to "0".
In the embodiment of the invention, if the second storage module finishes storing data, the FPGA chip releases the corresponding relation among the first input port, the first output port and the first index value through the control module, and when the residual storage space of the second storage module is less than or equal to the preset storage space, the FPGA chip sets the state of the first output port to be idle through the control module, so that the input/output ports can be multiplexed, the port resources are released as soon as possible, and the overall processing efficiency of the FPGA chip is improved.
Corresponding to the above data forwarding method, the present invention also provides a hardware structure diagram of the FPGA chip shown in fig. 4. Referring to fig. 4, at the hardware level, the FPGA chip includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, but may also include hardware required for other services. The processor reads the corresponding computer program from the nonvolatile memory into the memory and then runs the computer program to form the forwarding device of the data on the logic level. Of course, besides the software implementation, the present invention does not exclude other implementations, such as logic devices or combination of software and hardware, and the like, that is, the execution subject of the following processing flow is not limited to each logic unit, and may be hardware or logic devices.
Fig. 5 is a block diagram of an embodiment of a forwarding apparatus for data provided in the present invention, and as shown in fig. 5, the forwarding apparatus for data may include: the control module 51 and the plurality of memory modules, for example, the plurality of memory modules include four memory modules, namely a memory module 52, a memory module 53, a memory module 54, and a memory module 55, it should be noted that the four memories in the embodiment shown in fig. 5 are only exemplary and do not form a limitation to the present application, and the plurality of memory modules in the present application may be any number of two or more memory modules, where the memory module 52 is a first memory module described in the present application, and the memory module 53 is a second memory module described in the present application as an example;
the storage module 52 is configured to send a request instruction to the control module 51 if the storage module 52 needs to forward data, where the storage module 52 is one of the plurality of storage modules;
the control module 51 is configured to determine a first output port and a first index value for a first input port corresponding to the storage module 52 and send a response instruction carrying the first index value to the storage module 52 if the request instruction is received;
the storage module 52 is further configured to send the data to be forwarded and the first index value to the control module 51 if the response instruction is received;
the control module 51 is further configured to determine a first egress port based on the first index value, and forward data to a storage module 53 corresponding to the first egress port, where the storage module 53 is one of the plurality of storage modules.
In an embodiment, the control module 51 is further configured to determine a first index value from at least one second index value recorded in the first preset list based on a first preset rule, and determine a first egress port from at least one second egress port recorded in the second preset list based on a second preset rule.
In an embodiment, the control module 51 is further configured to establish a corresponding relationship between the first ingress port, the first egress port and the first index value.
In an embodiment, the storage module 53 is configured to detect whether the data carries an end identifier for marking the end of the data after receiving the data forwarded by the control module 51 through the first output port, and when it is detected that the data carries the end identifier through the storage module 53, end storing the data, and send an end instruction for ending the forwarding to the control module 51;
the control module 51 is further configured to release the corresponding relationship between the first ingress port, the first egress port, and the first index value if the control module 51 receives the ending instruction.
In an embodiment, the control module 51 is further configured to determine whether the remaining storage space of the storage module 53 is less than or equal to a preset storage amount after the step of releasing the correspondence relationship between the first ingress port, the first egress port and the first index value, and set the state of the first egress port to idle when the remaining storage space of the storage module 53 is less than or equal to the preset storage amount.
The implementation process of the functions and actions of each unit in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.
For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the invention. One of ordinary skill in the art can understand and implement it without inventive effort.
As can be seen from the above embodiments, the FPGA chip determines a corresponding first output port and a first index value for the first input port through the control module, the FPGA chip sends the first index value to the first storage module corresponding to the first input port through the control module to trigger the first storage module to start sending data to the control module, when the control module receives the data, the FPGA chip finds the first output port through the control module based on the first index value, and sends the data to the second storage module corresponding to the first output port through the control module. The control module determines a first output port for the first input port, and the processing processes of multiple data forwarding can be processed in parallel through the control module, so that the overall processing performance of the FPGA chip is greatly improved, and the processing efficiency is high.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A data forwarding method is applied to an FPGA chip, and the FPGA chip comprises: a control module, a plurality of memory modules, wherein the method comprises:
if a first storage module needs to forward data, a request instruction is sent to the control module through the first storage module, and the first storage module is one of the storage modules;
if the control module receives the request instruction, determining a first output port and a first index value for a first input port corresponding to the first storage module through the control module; the first output port is a port which is selected by the control module from at least one output port, is in an idle state and has the least number of times of being called;
sending a response instruction carrying the first index value to the first storage module through the control module;
if the first storage module receives the response instruction, sending data to be forwarded and the first index value to the control module through the first storage module;
determining, by the control module, the first egress port based on the first index value;
and forwarding the data to a second storage module corresponding to the first output port through the control module, where the second storage module is one of the plurality of storage modules.
2. The method of claim 1, wherein the determining, by the control module, a first egress port and a first index value for a first ingress port corresponding to the first storage module comprises:
determining, by the control module, a first index value from at least one second index value recorded in a first preset list based on a first preset rule;
and determining, by the control module, a first egress port from at least one second egress port recorded in a second preset list based on a second preset rule.
3. The method of claim 1 or claim 2, wherein prior to the step of determining, by the control module, the first egress port based on the first index value, the method further comprises:
and establishing a corresponding relation among the first input port, the first output port and the first index value through the control module.
4. The method of claim 3, wherein after the step of forwarding the data to the second storage module corresponding to the first egress port by the control module, the method further comprises:
detecting whether the data carries an end identifier for marking the end of the data or not through the second storage module;
when the second storage module detects that the data carries the ending mark, ending storing the data;
sending an ending instruction for ending forwarding to the control module through the second storage module;
and if the control module receives the ending instruction, the control module releases the corresponding relation among the first input port, the first output port and the first index value.
5. The method according to claim 4, wherein after the step of releasing, by the control module, the correspondence among the first ingress port, the first egress port, and the first index value, further comprising:
judging whether the residual storage space of the second storage module is smaller than or equal to a preset storage amount through the control module;
and when the residual storage space of the second storage module is less than or equal to a preset storage space, setting the state of the first output port to be idle through the control module.
6. An apparatus for forwarding data, the apparatus comprising: the device comprises a control module and a plurality of storage modules;
the first storage module is configured to send a request instruction to the control module if the first storage module needs to forward data, and the first storage module is one of the plurality of storage modules;
the control module is configured to determine a first output port and a first index value for a first input port corresponding to the first storage module if the request instruction is received, and send a response instruction carrying the first index value to the first storage module; the first output port is a port which is selected by the control module from at least one output port, is in an idle state and has the least number of times of being called;
the first storage module is further configured to send data to be forwarded and the first index value to the control module if the response instruction is received;
the control module is further configured to determine the first egress port based on the first index value, and forward the data to a second storage module corresponding to the first egress port, where the second storage module is one of the plurality of storage modules.
7. The apparatus of claim 6,
the control module is further configured to determine a first index value from at least one second index value recorded in the first preset list based on a first preset rule, and determine a first egress port from at least one second egress port recorded in the second preset list based on a second preset rule.
8. The apparatus of claim 6 or claim 7,
the control module is further configured to establish a correspondence between the first ingress port, the first egress port, and the first index value.
9. The apparatus of claim 8,
the second storage module is configured to detect whether the data carries an end identifier for marking data end after receiving the data forwarded by the control module through the first output port, end storing the data when detecting that the data carries the end identifier through the second storage module, and send an end instruction for ending forwarding to the control module;
the control module is further configured to release a corresponding relationship between the first ingress port, the first egress port, and the first index value if the control module receives the end instruction.
10. The apparatus of claim 9,
the control module is further configured to determine whether a remaining storage space of the second storage module is less than or equal to a preset storage amount after the corresponding relationship among the first ingress port, the first egress port, and the first index value is released, and set the state of the first egress port to idle when the remaining storage space of the second storage module is less than or equal to the preset storage amount.
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