CN107733568B - Method and device for realizing CRC parallel computation based on FPGA - Google Patents
Method and device for realizing CRC parallel computation based on FPGA Download PDFInfo
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- CN107733568B CN107733568B CN201710864655.7A CN201710864655A CN107733568B CN 107733568 B CN107733568 B CN 107733568B CN 201710864655 A CN201710864655 A CN 201710864655A CN 107733568 B CN107733568 B CN 107733568B
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- H—ELECTRICITY
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/091—Parallel or block-wise CRC computation
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Abstract
The invention discloses a method and a device for realizing CRC parallel computation based on FPGA, wherein the method comprises the following steps: at an interface sending end, inputting a message to be calculated into a corresponding CRC generator polynomial according to an input effective data bit width, obtaining different direct arithmetic expressions according to the CRC generator polynomial and different parallel input effective data bit widths, performing CRC calculation, aligning the message to be calculated and a calculated CRC code, integrating the message to be calculated into a message to be sent, and sending the message to an interface receiving end; and at an interface receiving end, inputting the message to be sent into a corresponding CRC generator polynomial according to the bit width of the received effective data, obtaining different direct arithmetic expressions according to the CRC generator polynomial and different parallel input effective data bit widths, performing CRC calculation, and comparing the calculated CRC code with the CRC code carried in the message to be sent to obtain a CRC check result. The invention supports real-time change of valid data bit width and has better compatibility.
Description
Technical Field
The invention relates to the technical field of Ethernet, in particular to a method and a device for realizing CRC parallel computation based on FPGA.
Background
Cyclic Redundancy Check (CRC) is a hash function that generates a short fixed bit Check code from data, and is used primarily to detect or verify errors that may occur after data transmission or storage. The CRC check is widely applied to the field of ethernet technology, and is used for detecting the correctness of the contents of the transmitted ethernet packet at the receiving end.
The core of the CRC algorithm is a generator polynomial including multiple generator polynomials such as CRC8, CRC16, CRC32, and the like, and is applicable to multiple interface protocols such as ethernet, video, USB, and the like, the implementation of the CRC check is divided into a serial manner and a parallel manner, a direct equation can be generated according to the generator polynomial for the parallel CRC check, and the generated direct equations are different for the same generator polynomial if the valid data bit width is different.
In the logic implementation in the field of ethernet technology, the CRC of the ethernet packet needs to be checked based on the interface format of the internal MAC layer. The minimum unit of the Ethernet message length is byte, the data bit width of the Ethernet MAC layer interface with the rate of 1Gbps and below is 4 bits or 8 bits, namely the effective data bit width of the interface is unchanged; the data bit width of the ethernet MAC layer interface with the rate of 10Gbps or more is greater than 32 bits, that is, the effective data bit width of the interface may change in real time.
In view of this, a CRC parallel computation implementation method capable of supporting real-time change of valid data bit width is urgently needed.
Disclosure of Invention
The invention aims to solve the technical problem of providing a CRC parallel computation implementation method capable of supporting real-time change of valid data bit width.
In order to solve the technical problems, the technical scheme adopted by the invention is to provide a method for realizing CRC parallel computation based on an FPGA, which comprises the following steps:
at an interface sending end, inputting a message to be calculated into a corresponding CRC generator polynomial according to an input effective data bit width, obtaining different direct arithmetic expressions according to the CRC generator polynomial and different parallel input effective data bit widths, performing CRC calculation, aligning the message to be calculated and a calculated CRC code, integrating the message to be calculated into a message to be sent, and sending the message to an interface receiving end;
and at an interface receiving end, inputting the message to be sent into a corresponding CRC generator polynomial according to the bit width of the received effective data, obtaining different direct arithmetic expressions according to the CRC generator polynomial and different parallel input effective data bit widths, performing CRC calculation, and comparing the calculated CRC code with the CRC code carried in the message to be sent to obtain a CRC check result.
In the above technical solution, performing CRC calculation at the interface sending end or the interface receiving end specifically includes the following steps:
when a message header indicating signal is received, carrying out initialization configuration and carrying out CRC calculation on the message header, wherein the initialization configuration supports all 0 or all 1;
when the effective data is received and the message head indicating signal and the message tail indicating signal are invalid, performing CRC calculation on the effective data;
and when a message tail indicating signal is received, performing CRC calculation on the message tail and latching the calculated CRC code as a CRC calculation result.
In the above technical solution, the message header indication signal and the message tail indication signal adopt a back-to-back input mode.
In the above technical solution, when invalid data is received, CRC calculation is not performed.
In the above technical solution, when the CRC code calculated by the interface receiving end is the same as the CRC code carried in the message to be transmitted, the CRC check is correct, otherwise, the CRC check is incorrect.
The invention also provides a device for realizing CRC parallel computation based on FPGA, comprising:
the CRC checker comprises a CRC generator arranged at an interface sending end and a CRC checker arranged at an interface receiving end, wherein the CRC generator comprises a first CRC calculator, a data delay module and a data aggregation module; the CRC checker comprises a second CRC calculator and a magic number detection module;
the interface sending end inputs the message to be calculated into a corresponding CRC generator polynomial according to the input effective data bit width and sends the message to be calculated to the first CRC calculator; the first CRC calculator obtains different direct expressions according to the CRC generator polynomial and different parallel input effective data bit widths, performs CRC calculation, latches the calculated CRC code and sends the CRC code to the data delay module; the data delay module aligns the message to be calculated and the CRC code calculated by the first CRC calculator; the data aggregation module integrates the message to be calculated and the CRC code which are aligned by the data delay module into a message to be sent and sends the message to be sent to an interface receiving end;
the interface receiving end inputs the message to be sent into a corresponding CRC generator polynomial according to the bit width of the received effective data and sends the message to be sent to the second CRC calculator; the second CRC calculator obtains different direct arithmetic expressions according to the CRC generator polynomial and different parallel input effective data bit widths, performs CRC calculation, latches the calculated CRC code and sends the CRC code to the magic number detection module; and the magic number detection module compares the CRC code calculated by the second CRC calculator with the CRC code carried in the message to be sent to obtain a CRC check result.
In the above technical solution, the first CRC calculator or the second CRC calculator performs initialization configuration according to the received message header indication signal, and performs CRC calculation on the message header, where the initialization configuration supports all 0 s or all 1 s; performing CRC calculation on the effective data according to the received effective data and invalid message head indication signals and message tail indication signals; and according to the received message tail indication signal, performing CRC calculation on the message tail and latching the calculated CRC code as a CRC calculation result.
In the above technical solution, the first CRC calculator and the second CRC calculator receive the header indication signal and the tail indication signal in a back-to-back input manner.
The invention inputs the message into the corresponding CRC generator polynomial according to the input effective data bit width, obtains different direct equations according to the CRC generator polynomial and different parallel input effective data bit widths and carries out CRC calculation, supports the real-time change of the effective data bit width, has better compatibility, and can be compatible with the interfaces with the unchanged effective data bit width of 1Gbps rate or less and the interfaces with the changeable effective data bit width of 10Gbps rate or more.
Drawings
Fig. 1 is a flowchart of a method for implementing CRC parallel computation based on an FPGA according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an apparatus for implementing CRC parallel computation based on an FPGA according to an embodiment of the present invention;
fig. 3 is a timing diagram of an input/output interface according to an embodiment of the present invention.
Detailed Description
The invention is described in detail below with reference to the drawings and the detailed description.
The embodiment of the invention provides a method for realizing CRC parallel computation based on an FPGA, which comprises the following steps as shown in figure 1:
and S1, at the Ethernet interface sending end, inputting the message to be calculated into a corresponding CRC generator polynomial according to the input effective data bit width, and obtaining different direct arithmetic expressions according to the CRC generator polynomial and different parallel input effective data bit widths and performing CRC calculation.
The message to be calculated comprises a message head indicating signal, a message tail indicating signal, a message effective data bit width indicating signal and message effective data.
And S2, aligning the message to be calculated and the calculated CRC code, integrating the message to be transmitted into a message to be transmitted, and selecting a corresponding data path to transmit the integrated message to be transmitted to the Ethernet interface receiving end.
And S3, at the receiving end of the Ethernet interface, inputting the message to be sent to a corresponding CRC generator polynomial according to the bit width of the received effective data, and obtaining different direct arithmetic expressions according to the CRC generator polynomial and different parallel input effective data bit widths and performing CRC calculation.
And S4, comparing the calculated CRC code with the CRC code carried in the message to be sent, if the calculated CRC code is the same as the CRC code, the CRC check is correct, otherwise, the CRC check is wrong.
The embodiment of the present invention further provides a device for implementing CRC parallel computation based on an FPGA, as shown in fig. 2, including:
the CRC checker comprises a CRC generator arranged at the sending end of the Ethernet interface and a CRC checker arranged at the receiving end of the Ethernet interface, wherein the CRC generator comprises a first CRC calculator 10, a data delay module 11 and a data aggregation module 12; the CRC checker includes a second CRC calculator 20 and a magic number detection module 21;
the ethernet interface sending end inputs the message to be calculated into a corresponding CRC generator polynomial according to the input valid data bit width, and sends the message to be calculated to the first CRC calculator 10; the first CRC calculator 10 obtains different direct equations according to the CRC generator polynomial and different parallel input valid data bit widths, performs CRC calculation, latches the calculated CRC code, and sends the latched CRC code to the data delay module 11; the data delay module 11 aligns the message to be calculated and the CRC code calculated by the first CRC calculator 10; the data aggregation module 12 integrates the message to be calculated and the CRC code aligned by the data delay module 11 into a complete message to be sent, and selects a corresponding data path to send the message to be sent to the ethernet interface receiving end;
the ethernet interface receiving end inputs the message to be sent into the corresponding CRC generator polynomial according to the bit width of the received valid data, and sends the message to be sent to the second CRC calculator 20; the second CRC calculator 20 obtains different direct arithmetic expressions according to the CRC generator polynomial and different parallel input valid data bit widths, performs CRC calculation, latches the calculated CRC code, and sends the CRC code to the magic number detection module 21; the magic number detection module 21 compares the CRC code calculated by the second CRC calculator 20 with the CRC code carried in the message to be sent, and if the CRC codes are the same, the CRC check is correct, otherwise, the CRC check is wrong.
The magic number detection module 21 realizes that the integrated message to be sent does not need to be sent to the second CRC calculator 20 after being separated into CRC codes, and the processing efficiency is greatly improved.
The following describes in further detail the implementation principle of the first CRC calculator 10 or the second CRC calculator 20 in this embodiment with reference to the input/output interface timing diagram of fig. 3:
when the first CRC calculator 10 or the second CRC calculator 20 receives the header indication signal, performing initialization configuration and performing CRC calculation on the header, where the initialization configuration supports all 0 s or all 1 s; when the effective data is received and the message head indicating signal and the message tail indicating signal are invalid, carrying out normal CRC calculation on the effective data; when a message tail indicating signal is received, performing CRC calculation on the message tail and latching the calculated CRC code as the CRC calculation result of the message. When invalid data is received, no CRC calculation is performed.
In this embodiment, the first CRC calculator 10 and the second CRC calculator 20 are based on a pipeline architecture, have good performance, support back-to-back input of a packet header indication signal and a packet tail indication signal of a packet, have small and constant transmission delay, and do not consume cache resources. In addition, the embodiment also supports the 'gap transmission' of the message, namely, CRC calculation is carried out only when the message data is effectively indicated, otherwise, the CRC calculation is maintained.
The embodiment supports real-time variable bit width of effective data of the message, and because the minimum transmission unit of the Ethernet is bytes, the bit width of large-bit-width parallel input can be adjusted in real time by adopting fewer direct calculation formulas. Therefore, the compatibility is better, and the Ethernet MAC layer interface with the unchanged effective data bit width of 1Gbps rate or below and the Ethernet MAC layer interface with the variable effective data bit width of 10Gbps rate or above can be compatible.
The embodiment is not limited to be applied to an ethernet interface, and can be applied to various interface protocols using CRC check by flexibly configuring the arithmetic expression, the input initial value, the output exclusive or and the line sequence, so that the application scenarios are wide.
The embodiment is applied to IPRAN and PTN equipment, has flexible configuration and excellent performance, and can be applied to various application scenes needing CRC calculation.
The present invention is not limited to the above-mentioned preferred embodiments, and any structural changes made by anyone in the light of the present invention, all the technical solutions similar or similar to the present invention, fall within the protection scope of the present invention.
Claims (7)
1. A method for realizing CRC parallel computation based on FPGA is characterized by comprising the following steps:
at an interface sending end, inputting a message to be calculated into a corresponding CRC generator polynomial according to an input effective data bit width, obtaining different direct arithmetic expressions according to the CRC generator polynomial and different parallel input effective data bit widths, performing CRC calculation, aligning the message to be calculated and a calculated CRC code, integrating the message to be calculated into a message to be sent, and sending the message to an interface receiving end;
at an interface receiving end, inputting a message to be sent into a corresponding CRC generator polynomial according to the bit width of the received effective data, obtaining different direct arithmetic expressions according to the CRC generator polynomial and different parallel input effective data bit widths, performing CRC calculation, and comparing the calculated CRC code with a CRC code carried in the message to be sent to obtain a CRC check result;
performing CRC calculation at an interface sending end or an interface receiving end, specifically comprising the following steps:
when a message header indicating signal is received, carrying out initialization configuration and carrying out CRC calculation on the message header, wherein the initialization configuration supports all 0 or all 1;
when the effective data is received and the message head indicating signal and the message tail indicating signal are invalid, performing CRC calculation on the effective data;
and when a message tail indicating signal is received, performing CRC calculation on the message tail and latching the calculated CRC code as a CRC calculation result.
2. The method of claim 1, wherein the header indicator and the footer indicator are input back-to-back.
3. The method of claim 1, wherein when invalid data is received, no CRC calculation is performed.
4. The method of claim 1, wherein when the CRC code calculated by the receiving end of the interface is the same as the CRC code carried in the message to be transmitted, the CRC check is correct, otherwise, the CRC check is incorrect.
5. An apparatus for implementing CRC parallel computation based on FPGA, comprising:
the CRC checker comprises a CRC generator arranged at an interface sending end and a CRC checker arranged at an interface receiving end, wherein the CRC generator comprises a first CRC calculator, a data delay module and a data aggregation module; the CRC checker comprises a second CRC calculator and a magic number detection module;
the interface sending end inputs the message to be calculated into a corresponding CRC generator polynomial according to the input effective data bit width and sends the message to be calculated to the first CRC calculator; the first CRC calculator obtains different direct expressions according to the CRC generator polynomial and different parallel input effective data bit widths, performs CRC calculation, latches the calculated CRC code and sends the CRC code to the data delay module; the data delay module aligns the message to be calculated and the CRC code calculated by the first CRC calculator; the data aggregation module integrates the message to be calculated and the CRC code which are aligned by the data delay module into a message to be sent and sends the message to be sent to an interface receiving end;
the interface receiving end inputs the message to be sent into a corresponding CRC generator polynomial according to the bit width of the received effective data and sends the message to be sent to the second CRC calculator; the second CRC calculator obtains different direct arithmetic expressions according to the CRC generator polynomial and different parallel input effective data bit widths, performs CRC calculation, latches the calculated CRC code and sends the CRC code to the magic number detection module; and the magic number detection module compares the CRC code calculated by the second CRC calculator with the CRC code carried in the message to be sent to obtain a CRC check result.
6. The apparatus of claim 5, wherein the first CRC calculator or the second CRC calculator performs initial configuration according to the received header indication signal, and performs CRC calculation on the header, the initial configuration supporting all 0 s or all 1 s; performing CRC calculation on the effective data according to the received effective data and invalid message head indication signals and message tail indication signals; and according to the received message tail indication signal, performing CRC calculation on the message tail and latching the calculated CRC code as a CRC calculation result.
7. The apparatus of claim 6, wherein the header indicator and the trailer indicator received by the first CRC calculator and the second CRC calculator are input back-to-back.
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| CN112579547B (en) * | 2021-01-27 | 2024-01-23 | 深圳市亿联无限科技有限公司 | Image file compression method and device for embedded system |
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