CN107731751A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN107731751A CN107731751A CN201610662867.2A CN201610662867A CN107731751A CN 107731751 A CN107731751 A CN 107731751A CN 201610662867 A CN201610662867 A CN 201610662867A CN 107731751 A CN107731751 A CN 107731751A
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- fin
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- barrier layer
- separation layer
- area
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 127
- 238000000926 separation method Methods 0.000 claims abstract description 103
- 230000004888 barrier function Effects 0.000 claims abstract description 86
- 239000000463 material Substances 0.000 claims abstract description 76
- 238000002955 isolation Methods 0.000 claims abstract description 70
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims description 28
- 230000008569 process Effects 0.000 claims description 22
- 239000012530 fluid Substances 0.000 claims description 19
- 239000007789 gas Substances 0.000 claims description 15
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 6
- 229910018557 Si O Inorganic materials 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 238000003851 corona treatment Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000007711 solidification Methods 0.000 claims description 2
- 230000008023 solidification Effects 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 125000004430 oxygen atom Chemical group O* 0.000 abstract description 16
- 238000009792 diffusion process Methods 0.000 abstract description 13
- 230000005669 field effect Effects 0.000 description 10
- 238000011049 filling Methods 0.000 description 9
- 238000000151 deposition Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- -1 oxonium ion Chemical class 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910007991 Si-N Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910006294 Si—N Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000001272 nitrous oxide Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, wherein forming method includes：Substrate is provided, the multiple fins formed on substrate；Isolated material is filled between adjacent fin；Remove the second fin and the second separation layer forms opening；Barrier layer is formed in the side wall of opening, the density on barrier layer is more than the density of the first separation layer；Isolation structure is formed in the opening.The present invention forms barrier layer after the second fin and the second separation layer formation opening is removed, in the side wall of opening, and the density on barrier layer is more than the density of the first separation layer.Because the density on barrier layer is larger, diffusion of the oxygen atom in the first separation layer can effectively be stopped, so as to reduce contact of the oxygen atom with the first fin, the oxidized possibility of the first fin is reduced, so as to effectively improve the uniformity of fin in formed semiconductor structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
As integrated circuit is to super large-scale integration development, the current densities of IC interior are increasing, institute
Comprising component number it is also more and more, the size of component also reduces therewith.With the reduction of MOS device size, MOS devices
The raceway groove of part shortens therewith.Due to channel shortening, the gradual channel approximation of MOS device is no longer set up, and highlight it is various unfavorable
Physical effect (particularly short-channel effect), this causes device performance and reliability to degenerate, and limits device size
Further reduce.
In order to further reduce the size of MOS device, people have developed multiaspect grid field effect transistor structure, to improve
The control ability of MOS device grid, suppress short-channel effect.Wherein fin formula field effect transistor is exactly a kind of common multiaspect grid
Structure transistor.
Fin formula field effect transistor is stereochemical structure, including substrate, formed with one or more protrusion on the substrate
Fin, it is provided between fin and is dielectrically separated from part；Grid is across on fin and the top of the covering fin and side wall.Due to this vertical
The transistor of body structure and conventional planar structure has larger difference, if some processes misoperation may be to forming device
Electric property makes a big impact.
Source region, drain region and the raceway groove of fin formula field effect transistor are respectively positioned in fin, and the formation process of fin directly affects
The performance of formed transistor.But the semiconductor structure formed in the prior art, the problem of fin uniformity deficiency be present.
The content of the invention
The present invention is solved the problems, such as to be to provide a kind of semiconductor structure and forming method thereof, to improve the fin uniformity, changed
The kind performance for forming semiconductor structure.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided, the substrate includes multiple first areas and the second area between adjacent first regions；
The multiple fins formed on the substrate, the fin on the first area substrate is the first fin, positioned at described
Fin on second area substrate is the second fin；Isolated material is filled between adjacent fin, separation layer is formed, positioned at first
Separation layer on area substrate is the first separation layer, and the separation layer on second area substrate is the second separation layer；Remove institute
State the second fin and second separation layer forms opening, the side wall of the opening exposes first separation layer and bottom is exposed
The substrate of the second area；Form barrier layer in the side wall of the opening, the density on the barrier layer be more than described first every
The density of absciss layer；Isolation structure is formed in said opening.
Optionally, include the step of the opening sidewalls form barrier layer：The mode of using plasma processing is formed
The barrier layer.
Optionally, in the step of mode of using plasma processing forms the barrier layer, the corona treatment
Using nitrogenous gas.
Optionally, the nitrogenous gas includes nitric oxide, nitrous oxide or ammonia.
Optionally, using nitrogenous gas in the step of side wall of the opening forms barrier layer, technological parameter includes：Work
Skill gas pressure intensity is in the range of 1mTorr to 500mTorr, and process gas flow is in the range of 10sccm to 1000sccm, technique
Temperature is in the range of 20 DEG C to 300 DEG C, and the process time is in the range of 2s to 500s.
Optionally, in the step of forming separation layer, the material of the separation layer is silica；The step of forming barrier layer
In, the barrier layer is nitrogenous barrier layer.
Optionally, in the step of forming barrier layer, the material on the barrier layer is silicon oxynitride.
Optionally, in the step of side wall of the opening forms barrier layer, the thickness on the barrier layer existsArrive
In the range of.
Optionally, the step of forming isolation structure in said opening includes：Isolated material is filled into the opening；It is right
The isolated material is made annealing treatment to form isolation structure.
Optionally, the step of being made annealing treatment to the isolated material includes：Institute is carried out by way of steam annealing
State annealing.
Optionally, the step of forming separation layer and one or two step formed in isolation structure include：Pass through stream
The mode of body chemical vapor phase growing fills isolated material.
Optionally, in the step of filling isolated material by way of fluid chemistry vapour deposition, the isolated material is
The isolated material of fluid state；In the step of being made annealing treatment the isolated material to form isolation structure, the annealing
Processing solidifies the isolated material of the fluid state.
Optionally, the isolated material is containing polymer one or more in Si -- H bond, Si -- H bond and Si-O keys.
Optionally, remove second fin and second separation layer forms the step of being open and included：Carved by dry method
The mode of erosion removes second fin and second separation layer, expose the second area substrate and described first every
The side wall of absciss layer, form the opening.
Optionally, there is provided in the step of substrate, the substrate of the first area is used to form the semiconductor device with fin
Part, the substrate of the second area are used to form isolation structure.
Optionally, after the step of forming the isolation structure, the forming method also includes：Remove the isolation junction
The segment thickness of structure, first separation layer and the barrier layer, expose the part table with side wall at the top of first fin
Face..
Accordingly, the present invention also provides a kind of semiconductor structure, including：
Substrate, the substrate include multiple first areas and the second area between adjacent first regions；It is located at
Multiple fins on the substrate of first area and the separation layer being filled between adjacent fin；On second area substrate every
From structure；Barrier layer between the isolation structure and the separation layer, the density on the barrier layer are more than the isolation
The density of layer.
Optionally, the barrier layer is nitrogenous barrier layer；The material of the separation layer is oxide.
Optionally, the material on the barrier layer is silicon oxynitride.
Optionally, the thickness on the barrier layer existsArriveIn the range of.
Compared with prior art, technical scheme has advantages below：
The present invention is after second fin and second separation layer formation opening is removed, in the side wall of the opening
Barrier layer is formed, and the density on the barrier layer is more than the density of first separation layer.Due to the barrier layer density compared with
Greatly, diffusion of the oxygen atom in first separation layer can effectively be stopped, so as to reduce contact of the oxygen atom with the first fin,
The oxidized possibility of first fin is reduced, so as to effectively improve the uniformity of fin in formed semiconductor structure.
Brief description of the drawings
Fig. 1 to Fig. 3 is diagrammatic cross-section corresponding to a kind of each step of method for forming semiconductor structure；
Fig. 4 to Figure 13 is that cross-section structure corresponding to each step of the embodiment of method for forming semiconductor structure one of the present invention is illustrated
Figure；
Figure 14 is the cross-sectional view of the embodiment of semiconductor structure one of the present invention.
Embodiment
From background technology, there is the problem of uniformity deficiency in the formation process of fin of the prior art.In conjunction with
In the prior art the reason for the forming process analysis uniformity deficiency problem of fin：
Referring to figs. 1 to Fig. 3, diagrammatic cross-section corresponding to a kind of each step of method for forming semiconductor structure is shown.
As shown in figure 1, providing substrate 10 first, the surface of substrate 10 has multiple fins 11；In the adjacent fin
Separation layer 12 is formed between 11.The substrate 10 include multiple first area 10a and between the 10a of adjacent first regions the
Two region 10b, the first area 10a are used to form semiconductor devices, and the second area 10b is used to form isolation structure.
As shown in Fig. 2 remove positioned at the fin 11 on the surface of second area 10b substrates 10 and served as a contrast positioned at second area 10b
The separation layer 12 on the surface of bottom 10, form the first opening 13.
With reference to figure 3, presoma is filled into the described first opening 13, and presoma is made annealing treatment, forms isolation
Structure 14.
With the reduction of dimensions of semiconductor devices, the distance between adjacent described fin 11 is gradually reduced, and described first opens
The size of mouth 13 is also gradually reduced.In order to improve the filling effect of the separation layer 12 and the isolation structure 14, cavity is reduced
Appearance, often through fluid chemistry be vapor-deposited mode form the separation layer 12 and isolation structure 14.
Therefore the isolated material filled into the described first opening 13 is fluid state, by being carried out to the isolated material
Make annealing treatment and the isolated material is formed by curing isolation structure 14.The annealing has been usually contained at steam annealing
Reason, the consistency for the separation layer 12 that another aspect fluid chemistry vapour deposition mode is formed is relatively low, and barrier properties are poor.Cause
This, in annealing process, oxygen atom is easy to through the separation layer 12 with being located at first area 10a close to described second
Fin 11 (as shown in Fig. 3 centre circles 15) contact of region 10b adjacent edges, is oxidized the fin 11.Subsequently reduce every
The height of absciss layer 12 and isolation structure 14, when exposing the top of the fin 11 and sidewall surfaces, the easy quilt of oxidized fin 11
Part removes, thus size can diminish, and so as to have impact on the dimensional homogeneity of formed fin 11, have impact on formed semiconductor
The performance of device.
To solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided, the substrate includes multiple first areas and the second area between adjacent first regions；
The multiple fins formed on the substrate, the fin on the first area substrate is the first fin, positioned at described
Fin on second area substrate is the second fin；Isolated material is filled between adjacent fin, separation layer is formed, positioned at first
Separation layer on area substrate is the first separation layer, and the separation layer on second area substrate is the second separation layer；Remove institute
State the second fin and second separation layer forms opening, the side wall of the opening exposes first separation layer and bottom is exposed
The substrate of the second area；Form barrier layer in the side wall of the opening, the density on the barrier layer be more than described first every
The density of absciss layer；Isolation structure is formed in said opening.
The present invention is after second fin and second separation layer formation opening is removed, in the side wall of the opening
Barrier layer is formed, and the density on the barrier layer is more than the density of first separation layer.Due to the barrier layer density compared with
Greatly, diffusion of the oxygen atom in first separation layer can effectively be stopped, so as to reduce contact of the oxygen atom with the first fin,
The oxidized possibility of first fin is reduced, so as to effectively improve the uniformity of fin in formed semiconductor structure.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
With reference to figure 4 to Figure 13, show and cutd open corresponding to each step of the embodiment of method for forming semiconductor structure one of the present invention
Face structural representation.
With reference to figure 4, there is provided substrate 100, the substrate 100 include multiple first area 100a and positioned at adjacent firstth areas
Second area 100b between the 100a of domain.
The substrate 100 is the operating platform of Subsequent semiconductor technique；The substrate 100 of the first area 100a is used for shape
Into the semiconductor devices with fin, the substrate 100 of the second area 100b is used to form isolation structure.
In the present embodiment, the substrate 100 includes being used to form the PMOS area of PMOS transistor and for forming NMOS
The NMOS area of transistor and the isolated area for being used for realization electric isolution between PMOS area and NMOS area.
The PMOS area is used to form p-type fin formula field effect transistor, and the NMOS area is used to form N-type fin field
Effect transistor, the isolated area are used to form the isolation structure realized and be electrically isolated between PMOS area and NMOS area.So
The first area 100a includes the PMOS area and the NMOS area, and the second area 100b includes the isolation
Area.
With reference to figure 5, the multiple fins 110 formed on the substrate 100, positioned at the first area 100a substrates
Fin on 100 is the first fin 110a, and the fin on the second area 100b substrates 100 is the second fin 110b.
Because the second area 100b is used to form isolation structure, so the second fin 110b need to subsequently be gone
Remove.Specifically, the second fin 110b quantity positioned at the surface of substrate 100 of the second area 100b is more than or equal to 1.
It should be noted that in the present embodiment, the substrate 100 and the fin 110 are formed by etching substrate
's.So combine with reference to figure 4 and Fig. 5, there is provided the substrate 100 includes with the step of forming fin 110：Substrate is provided
sub；The substrate sub is etched, forms the substrate 100 and multiple fins 110 positioned at the surface of substrate 100.
Specifically, with reference to figure 4, there is provided substrate sub.
The substrate sub is used to provide operating platform for subsequent technique, and etching forms fin 110.The substrate sub
Material be selected from monocrystalline silicon, polysilicon or non-crystalline silicon；The substrate sub can also be selected from silicon, germanium, GaAs or SiGe chemical combination
Thing；The substrate sub can also be other semi-conducting materials.In the present embodiment, the substrate sub materials are monocrystalline silicon, therefore
The material of the substrate 100 and the fin 110 is monocrystalline silicon.
In other embodiments of the invention, the substrate is also selected from epitaxial layer or epitaxial layer silicon-on.
Specifically, the substrate can include substrate and the semiconductor layer positioned at the substrate surface.The semiconductor layer can be adopted
The substrate surface is formed at selective epitaxial depositing operation.The substrate can be silicon substrate, germanium silicon substrate, carborundum lining
Bottom, silicon-on-insulator substrate, germanium substrate on insulator, glass substrate or III-V substrate, such as gallium nitride substrate
Or gallium arsenide substrate etc.；The material of the semiconductor layer is silicon, germanium, carborundum or SiGe etc..The substrate and semiconductor layer
Selection it is unrestricted, can choose suitable for process requirements or the substrate being easily integrated and the material for suitably forming fin.
And the thickness of the semiconductor layer can be by the control to epitaxy technique, so as to accurately control the affiliated height for forming fin
Degree.
Afterwards, with reference to reference to figure 5, the substrate sub is etched, forms the substrate 100 and positioned at the table of substrate 100
The fin 110 in face.
The substrate sub is etched to form substrate 100 and include positioned at the step of fin 110 on the surface of substrate 100：Institute
State substrate sub surfaces and form patterned mask 102；It is mask with the patterned mask 102, etches the substrate sub,
Form substrate 100 and the fin 110 positioned at the surface of substrate 100.
The patterned mask 102 is used for the positions and dimensions for defining the fin 110.Form patterned mask
102 the step of, includes：The first mask layer is formed on the substrate sub surfaces；In the first mask material layer surface shape
Into patterned layer；Using the patterned layer as the first mask layer described in mask etching until exposing the substrate sub surfaces,
Form the mask 102.Specifically, the material of the mask 102 is silicon nitride.
It should be noted that in the present embodiment, before the step of forming patterned mask 102, the formation
Method is additionally included in the substrate sub surfaces and forms cushion 101, to reduce between the mask 102 and the substrate sub
Lattice mismatch.Specifically, the material of cushion 101 described in the present embodiment is oxide.
The patterned layer can be patterned photoresist layer, be formed using coating process and photoetching process.In addition it is
The characteristic size of the diminution fin, and the distance between adjacent fin, the patterned layer can also use multigraph
Shape masking process is formed.The multiple graphical masking process includes：Self-alignment duplex pattern (Self-aligned
Double Patterned, SaDP) triple graphical (the Self-aligned Triple Patterned) works of technique, autoregistration
Skill or graphical (Self-aligned Double Double Patterned, the SaDDP) technique of autoregistration quadruple.
The technique for etching the substrate sub is anisotropic dry etch process.Therefore the fin 110 of the formation
Side wall is vertical or tilt relative to the surface of the substrate 100, and when the side wall of the fin 110 is relative to the substrate 100
When surface tilts, the bottom size of the fin 110 is more than top dimension.
It should be noted that during fin 110 is formed, the semiconductor substrate surface being etched there may be damage
Or it is small uneven, in order to the damage to the semiconductor substrate surface or it is uneven repair, the shape to improve
Into the performance of semiconductor structure, in the present embodiment, after the step of forming fin 110, the forming method also includes：Institute
The surface for stating substrate 100 and fin 110 forms reparation oxide layer (Liner oxide) (not shown).The reparation oxygen
Changing layer can be with the round and smooth substrate 100 and the wedge angle on the surface of fin 110, and serves as the film layer subsequently formed and the lining
Cushion between bottom 100 and fin 110, to reduce lattice mismatch.Specifically, chemical vapor deposition or hot oxygen can be passed through
The mode of change forms the reparation oxide layer.But in other embodiments of the invention, the reparation oxygen can not also be formed
Change layer, damage is repaired by being made annealing treatment to the substrate and the fin.
With reference to figure 6 and Fig. 7, isolated material is filled between adjacent fin 110, separation layer 120 is formed, positioned at first area
Separation layer 120 on 100a substrates 100 is the first separation layer 120a, the separation layer 120 on second area 100b substrates 100
For the second separation layer 120b.
The separation layer 120 is used to realize the electric isolution between adjacent fin 110.In the present embodiment, first isolation
Layer 120a is used to realize the electric isolution between the first fin 110a.The second separation layer 120b need to be subsequently removed.
The material of the separation layer 120 can be silica.Specifically, the step of forming separation layer 120 includes：Such as
Shown in Fig. 6, isolated material is filled between the adjacent fin 110, the top surface of the isolated material is higher than the mask
102 top surface；As shown in fig. 7, planarization process is carried out to the isolated material untill the mask 102 is exposed.
In order that the separation layer 120 is sufficient filling with the gap between the adjacent fin 110, the separation layer is reduced
The generation of 120 inside apertures, the step of filling separation layer 120, include：It is vapor-deposited (Flowable by fluid chemistry
Chemical Vapor Deposition, FCVD) mode fill isolated material.
Specifically, in the step of filling isolated material by way of fluid chemistry vapour deposition, the isolated material is
The isolated material of fluid state, and the surface of the isolated material is higher than the surface of the mask 102.So formed it is described every
The step of absciss layer 120, also includes：The isolated material is made annealing treatment to form separation layer 120.
The isolated material is the condensate containing one or more polymer in Si -- H bond, Si-N keys and Si-O keys.Cause
This makes the consistency of the formed separation layer 120 of the isolated material solidification of the fluid state relatively low by annealing process, stops
Poor-performing.
It should be noted that as shown in fig. 7, in the present embodiment, after the separation layer 120 is formed, the formation side
Method also includes：The separation layer 120 is planarized, makes the top surface of the separation layer 120 and the top surface of the mask 102
Flush.
With reference to figure 8, the second fin 110b (as shown in Figure 7) and the second separation layer 120b are removed (such as Fig. 7 institutes
Show) opening 140 is formed, the side wall of the opening 140 exposes the first separation layer 120a and the second area is exposed in bottom
100b substrate 100.
Because the second area 100b is used to form isolation structure.Therefore the second fin 110b needs to be removed.
In addition, therefore the second isolated area 120b positioned at the surface of second area 100b substrates 100 is also removed in the lump.
Specifically, the second fin 110b and second isolation can be removed by way of mask dry etching
Layer 120b, exposes the surface of substrate 100 of the second area 100b and the side wall of the first separation layer 120a.
Because in the step of forming substrate 100, the quantity positioned at the second fin 110b is more than or equal to 1.Therefore
In the step of removing the second fin 110b, the quantity for the second fin 110b being removed is more than or equal to 1.Specifically
, in the present embodiment, removal is located at 2,100 surface of second area 100b substrates the second fin 110b.
In the present embodiment, isolated area is between PMOS area and NMOS area, that is to say, that second area 100b is located at
Between two first area 100a.Therefore after the second fin 110b and the second separation layer 120b is removed, expose
The first separation layer 120a side wall and the surface of second area 100b substrates 100 surround opening 140.
With reference to figure 9, barrier layer 150 is formed in the side wall of the opening 140, the density on the barrier layer 150 is more than described
First separation layer 120a density.
The barrier layer 150 is used to stop diffusion of the oxonium ion in the first separation layer 120a in subsequent technique,
So as to reduce the possibility that oxonium ion contacts with the first fin 110a, the oxidized probabilities of the first fin 110a are reduced, are improved
The uniformity coefficient of fin in formed semiconductor structure.
The density on the barrier layer 150 is more than the density of the first separation layer 120a, therefore the resistance on the barrier layer 150
Gear ability is stronger, can effectively stop the diffusion of oxonium ion, reduces the oxidized possibility of the first fin 110a, improves institute's shape
The uniformity coefficient of fin into semiconductor structure.
The step of forming barrier layer 150 includes：Side wall of the mode of using plasma processing in the opening 140
Form the barrier layer 150.In the present embodiment, in mode the step of forming barrier layer 150 of using plasma processing,
The corona treatment is carried out using nitrogenous gas, so the barrier layer formed is nitrogenous barrier layer.Wherein, it is described nitrogenous
Gas includes nitric oxide, nitrous oxide or ammonia
Specifically, using nitrogenous gas in the step of side wall of the opening forms barrier layer 150, technological parameter bag
Include：Process gas pressure in the range of 1mTorr to 500mTorr, process gas flow in the range of 10sccm to 1000sccm,
Technological temperature is in the range of 20 DEG C to 300 DEG C, and the process time is in the range of 2s to 500s.
Specifically, in the present embodiment, the material of the separation layer 120 is silica, that is to say, that first separation layer
120a material is silica, and the material on the barrier layer 150 is silicon oxynitride.Fine and close silicon oxynitride barrier layer, Neng Gouyou
Effect stops the diffusion of oxonium ion.
If it should be noted that the thickness on the barrier layer 150 is too small, the work(for stopping oxygen atom diffusion is difficult to
Energy；If the thickness on the barrier layer 150 is too big, waste of material is easily caused, the problem of increasing technology difficulty.The present embodiment
In, the thickness on the barrier layer 150 existsArriveIn the range of.
With reference to figures 10 to Figure 13, isolation structure 160 is formed in 140 (as shown in Figure 9) of the opening.
The isolation structure 160 is used for the electric isolution for realizing the semiconductor-on-insulator device of adjacent first regions 100a substrates 100.Tool
Body, in the present embodiment, the isolation structure 160 is located at as between first area 100a PMOS areas and nmos area, therefore
The isolation structure 160 is used to realize the electric isolution between two first area 100a (i.e. described PMOS areas and nmos area).
The material of the isolation structure 160 is silica, can be formed by way of chemical vapor deposition.In addition, it is
The guarantee isolation structure 160 is sufficient filling with to the opening 140, and that reduces that the internal pore of isolation structure 160 formed can
Can, the isolation structure 160 can be formed by way of fluid chemistry vapour deposition.
Specifically, the step of forming isolation structure 160 includes：
With reference to figure 10, the filling isolated material 160f into 140 (as shown in Figure 9) of the opening.
Specifically, in the step of filling the isolated material 160f, filled by way of fluid chemistry vapour deposition every
From material 160f.So in the step of isolated material 160f is filled by way of being vapor-deposited fluid chemistry, the isolation
Material 160f is the isolated material of fluid state.
The isolated material 160f is the polymerization containing one or more polymer in Si -- H bond, Si-N keys and Si-O keys
Body.It is filled using the isolated material 160f of fluid state, the isolated material 160f can be effectively improved to the opening
140 filling extent, reduce the formation in space.
It should be noted that in the present embodiment, also there is mask 102 on the top surface of fin 110, thus it is described every
Top surface from material 160f is higher than the top surface of the mask 102.
Then, with reference to reference to figure 11, the isolated material 160f is made annealing treatment to form isolation structure 160.
The annealing solidifies the isolation structure 160f of fluid state, forms the isolation structure 160.Specifically,
In the present embodiment, the isolation structure 160 for being used for isolating PMOS and NMOS is formed by making annealing treatment.
Specifically, the step of being made annealing treatment to the isolated material 160f includes：Entered by way of steam annealing
The row annealing.During being made annealing treatment, particularly during steam annealing is carried out, oxygen atom can be sent out
Raw diffusion.
But because the first separation layer 120a side walls are formed with barrier layer 150, the barrier layer 150 is finer and close, energy
Enough effective diffusions for suppressing oxygen atom in the first separation layer 120a, avoid the oxygen atom of diffusion and first fin
110a contact and aoxidize the first fin 110a, so as to effectively reduce the first fin 110a be oxidized can
Can, and then effective raising forms the uniformity of fin in semiconductor structure.
With reference to figure 12 and Figure 13, in the present embodiment, the substrate 100 of the first area 100a is used to form fin field effect
Transistor, therefore need to expose with the part surface of side wall at the top of the first fin 110a, so that the grid subsequently formed
Structure can cover the side wall and top surface of the first fin 110a.So after the isolation structure 160 is formed,
The forming method also includes：Remove the isolation structure 160, the first separation layer 120a and the barrier layer 150
Segment thickness, expose the part surface with side wall at the top of the first fin 110a.
Specifically, remove the part of the isolation structure 160, the first separation layer 120a and the barrier layer 150
The step of thickness, includes：
It should be noted that in the present embodiment, the isolation structure 160 is also located at the first separation layer 120a and described
First fin 110a top surface, cushion 101 and mask are also sequentially formed with the first fin 110a top surfaces
102.Therefore the isolation structure 160 also covers the top surface of the first separation layer 120a and the mask 102.
With reference first to Figure 12, planarization process is carried out to the isolation structure 160, removes the isolation structure of segment thickness
160。
In the present embodiment, planarization process is carried out to the isolation structure 160 by way of cmp.It is described
Cmp stops when exposing the top surface of the mask 102, to remove the isolation structure on the top of fin 110
160 and mask 102 and cushion 101, expose the top surface of the fin 110.
With reference to reference to figure 13, then, return and carve isolation structure 160, the first separation layer 120a and the barrier layer
150, expose the surface with partial sidewall at the top of the first fin 110a.
Isolation structure 160, the first separation layer 120a and the anti oxidation layer 150 are removed by returning carving technology
Segment thickness, expose at the top of the first fin 110a and the surface of partial sidewall.Return and carve the isolation structure 160 and described
The concrete technology of separation layer 120 is same as the prior art, and the present invention will not be repeated here.
Accordingly, the present invention also provides a kind of semiconductor structure.
With reference to figure 14, the cross-sectional view of the embodiment of semiconductor structure one of the present invention is shown.
As shown in figure 14, the semiconductor structure includes：
Substrate 200, the substrate 200 include multiple first area 200a and between the 200a of adjacent first regions
Second area 200b；Multiple fins 210 on first area 200a substrates 200 and it is filled between adjacent fin 210
Separation layer 220；Isolation structure 260 on second area 200b substrates 200；Positioned at the isolation structure 260 and described
Barrier layer 250 between separation layer 220, the density on the barrier layer 250 are more than the density of the separation layer 220.
The substrate 200 is the operating platform of Subsequent semiconductor technique；The first area 200a is used to be formed with fin
The semiconductor structure in portion, the second area 200b are used to form the semiconductor structure without fin.The fin 210 is used for
Form fin formula field effect transistor.
In the present embodiment, the substrate 200 includes PMOS area, NMOS area and positioned at the PMOS area and NMOS
Isolated area between region.Wherein, the PMOS area is used to form PMOS transistor, and the NMOS area is used to form NMOS
Transistor, the isolated area are used to realize the electric isolution between the PMOS area and NMOS area.
The PMOS area is used to form p-type fin formula field effect transistor, and the NMOS area is used to form N-type fin field
Effect transistor, the isolated area are used to form the isolation structure realized and be electrically isolated between PMOS area and NMOS area.So
The first area 200a includes the PMOS area and the NMOS area, and the second area 200b includes the isolation
Area.
The separation layer 220 and the isolation structure 260, which are used to realize, to be electrically isolated.Specifically, the separation layer 220 is used for
Realize the electric isolution between adjacent fin 210；The isolation structure 260 is used to realize adjacent first regions 200a substrates 200
Electric isolution between semiconductor devices.
In the present embodiment, the second area 200b is isolated area, positioned at the PMOS areas as first area 200a and
Between nmos area, therefore the isolation structure 260 on the surface of second area 200b substrates 200 is used to realize two first area 200a
Electric isolution between (i.e. described PMOS areas and nmos area).Specifically, the material of the separation layer 220 and the isolation structure 260
Expect for silica.
The barrier layer 250 is used to prevent during the isolation structure 260 is formed oxygen atom to the separation layer 220
Interior diffusion, contact of the oxygen atom with the fin 210 is avoided, reduce the oxidized possibility of fin 210, improve the fin
210 uniformity.In the present embodiment, the barrier layer 250 is nitrogenous barrier layer.Specifically, the material on the barrier layer 250 is
Silicon oxynitride.
If it should be noted that the thickness on the barrier layer 250 is too small, the work(for stopping oxygen atom diffusion is difficult to
Energy；If the thickness on the barrier layer 250 is too big, waste of material is easily caused, the problem of increasing technology difficulty.The present embodiment
In, the thickness on the barrier layer 250 existsArriveIn the range of.
To sum up, the present invention is after second fin and second separation layer formation opening is removed, in the opening
Side wall formed barrier layer, and the density on the barrier layer be more than first separation layer density.Due to the barrier layer
Density is larger, can effectively stop diffusion of the oxygen atom in first separation layer, so as to reduce oxygen atom and the first fin
Contact, the oxidized possibility of first fin is reduced, so as to effectively improve fin in formed semiconductor structure
Uniformity.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (20)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including：Substrate is provided, the substrate includes multiple first areas and the second area between adjacent first regions；The multiple fins formed on the substrate, the fin on the first area substrate is the first fin, is located at Fin on the second area substrate is the second fin；Fill isolated material between adjacent fin, form separation layer, the separation layer on the substrate of first area for first every Absciss layer, the separation layer on second area substrate are the second separation layer；Remove second fin and second separation layer forms opening, the side wall of the opening exposes first separation layer And the substrate of the second area is exposed in bottom；Barrier layer is formed in the side wall of the opening, the density on the barrier layer is more than the density of first separation layer；Isolation structure is formed in said opening.
- 2. forming method as claimed in claim 1, it is characterised in that wrapped the step of the opening sidewalls form barrier layer Include：The mode of using plasma processing forms the barrier layer.
- 3. forming method as claimed in claim 2, it is characterised in that the mode of using plasma processing forms the stop In the step of layer, the corona treatment uses nitrogenous gas.
- 4. forming method as claimed in claim 3, it is characterised in that the nitrogenous gas includes nitric oxide, an oxidation two Nitrogen or ammonia.
- 5. forming method as claimed in claim 3, it is characterised in that resistance is formed using side wall of the nitrogenous gas in the opening In the step of barrier, technological parameter includes：In the range of 1mTorr to 500mTorr, process gas flow exists process gas pressure In the range of 10sccm to 1000sccm, technological temperature is in the range of 20 DEG C to 300 DEG C, and the process time is in the range of 2s to 500s.
- 6. forming method as claimed in claim 1, it is characterised in that in the step of forming separation layer, the material of the separation layer Expect for silica；In the step of forming barrier layer, the barrier layer is nitrogenous barrier layer.
- 7. forming method as claimed in claim 6, it is characterised in that in the step of forming barrier layer, the material on the barrier layer Expect for silicon oxynitride.
- 8. forming method as claimed in claim 1, it is characterised in that the opening side wall formed barrier layer the step of In, the thickness on the barrier layer existsArriveIn the range of.
- 9. forming method as claimed in claim 1, it is characterised in that the step of forming isolation structure in said opening is wrapped Include：Isolated material is filled into the opening；The isolated material is made annealing treatment to form isolation structure.
- 10. forming method as claimed in claim 9, it is characterised in that the step of being made annealing treatment to the isolated material Including：The annealing is carried out by way of steam annealing.
- 11. forming method as claimed in claim 9, it is characterised in that the step of forming separation layer and formation isolation structure In one or two step include：Isolated material is filled by way of fluid chemistry vapour deposition.
- 12. forming method as claimed in claim 11, it is characterised in that fluid chemistry vapour deposition by way of fill every From in the step of material, the isolated material is the isolated material of fluid state；In the step of being made annealing treatment the isolated material to form isolation structure, the annealing makes the flow-like The isolated material solidification of state.
- 13. forming method as claimed in claim 9, it is characterised in that the isolated material be containing Si -- H bond, Si -- H bond and One or more polymer in Si-O keys.
- 14. forming method as claimed in claim 1, it is characterised in that remove second fin and second separation layer The step of forming opening includes：Second fin and second separation layer are removed by way of dry etching, exposes institute The substrate of second area and the side wall of first separation layer are stated, forms the opening.
- 15. forming method as claimed in claim 1, it is characterised in that in the step of substrate is provided, the lining of the first area Bottom is used to form the semiconductor devices with fin, and the substrate of the second area is used to form isolation structure.
- 16. forming method as claimed in claim 1, it is characterised in that after the step of forming the isolation structure, the shape Also include into method：The segment thickness of the isolation structure, first separation layer and the barrier layer is removed, is exposed described First fin top and the part surface of side wall.
- A kind of 17. semiconductor structure, it is characterised in that including：Substrate, the substrate include multiple first areas and the second area between adjacent first regions；Multiple fins on the substrate of first area and the separation layer being filled between adjacent fin；Isolation structure on second area substrate；Barrier layer between the isolation structure and the separation layer, the density on the barrier layer are more than the separation layer Density.
- 18. semiconductor structure as claimed in claim 17, it is characterised in that the barrier layer is nitrogenous barrier layer；It is described every The material of absciss layer is oxide.
- 19. semiconductor structure as claimed in claim 18, it is characterised in that the material on the barrier layer is silicon oxynitride.
- 20. semiconductor structure as claimed in claim 17, it is characterised in that the thickness on the barrier layer existsArriveModel In enclosing.
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| CN113921396A (en) * | 2020-07-10 | 2022-01-11 | 泉芯集成电路制造(济南)有限公司 | Fin-structured transistor and manufacturing method thereof |
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| CN102074572A (en) * | 2009-10-28 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
| US20130037886A1 (en) * | 2011-08-10 | 2013-02-14 | Teng-Chun Tsai | Semiconductor device and method of making the same |
| US20140203376A1 (en) * | 2013-01-18 | 2014-07-24 | Globalfoundries Inc. | Finfet integrated circuits with uniform fin height and methods for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074572A (en) * | 2009-10-28 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
| US20130037886A1 (en) * | 2011-08-10 | 2013-02-14 | Teng-Chun Tsai | Semiconductor device and method of making the same |
| US20140203376A1 (en) * | 2013-01-18 | 2014-07-24 | Globalfoundries Inc. | Finfet integrated circuits with uniform fin height and methods for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113921396A (en) * | 2020-07-10 | 2022-01-11 | 泉芯集成电路制造(济南)有限公司 | Fin-structured transistor and manufacturing method thereof |
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