CN107729039B - Loading mode selection circuit of embedded operating system - Google Patents
Loading mode selection circuit of embedded operating system Download PDFInfo
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- CN107729039B CN107729039B CN201710834099.9A CN201710834099A CN107729039B CN 107729039 B CN107729039 B CN 107729039B CN 201710834099 A CN201710834099 A CN 201710834099A CN 107729039 B CN107729039 B CN 107729039B
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
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Abstract
The invention provides a loading mode selection circuit of an embedded operating system. The invention is realized by the following technical scheme: the bus reader-writer of the CPLD is respectively connected with GPP through parallel buses; the Ethernet link state register is connected with a link establishment indication pin of the PHY; the peripheral reset control generator is connected with a reset pin of FLASH and a reset pin of PHY; the CPU reset control generator is connected with a reset pin of GPP; after receiving the access signal of GPP, the bus reader-writer outputs the value of the Ethernet link state register to GPP; the Ethernet link state register is used for judging whether the link is effective or not through the link establishment indication pin level of the PHY, the Ethernet link state register is changed into 1 if the link is effective, and the Ethernet link state register is changed into 0 if the link is ineffective. The method solves the problems that in the prior art, a scheme for realizing loading mode selection through serial port commands needs to wait for user input overtime and influences loading speed.
Description
Technical Field
The invention relates to the field of embedded system design, in particular to a loading mode selection circuit and a loading mode selection method.
Background
An embedded operating system (Embedded Operating System, simply referred to as EOS) refers to an operating system for an embedded system. An embedded operating system is a widely used system software, and support of the embedded operating system is generally required in a complex application system. Before the embedded operating system works, the BootLoader needs to be started to be operated firstly to finish the initialization of the hardware of the embedded operating system, then the image file of the embedded operating system is loaded into the memory from the local storage or the network server, and the embedded operating system starts to work. According to the storage position of the image file, the loading mode of the embedded operating system can be divided into two loading modes, namely a local memory loading mode and an Ethernet remote loading mode. In the debugging stage or the later maintenance stage, the embedded operating system image is usually loaded remotely by using the Ethernet so as to facilitate debugging. However, when delivered for use by a user, the embedded operating system typically loads an embedded operating system image using a local memory loading mode to speed up boot time and reduce network equipment.
Currently, embedded operating system loading mode selection is typically through serial commands. The scheme for realizing the loading mode selection through the serial port command is that a user selects a loading mode in a medium period, and if the loading mode is not selected after the timeout, a default loading mode and an embedded operating system image file are selected. In a scenario of delivering user usage, a fixed loading mode is usually required to be a local memory loading mode, and although the local memory loading can be set to a default loading mode, the user must wait for the input of a timeout, and the timeout time must not be too short (typically 7 s), and too short is not enough to input the loading mode selection serial port command.
The existing scheme has the following defects:
the scheme of selecting the loading mode is realized through a serial port command, and in a scene of delivering users, the user input timeout needs to be waited, so that the loading speed is influenced.
Disclosure of Invention
The invention aims to provide an embedded operating system loading mode selection circuit and method without sacrificing loading speed and increasing extra hardware cost.
In order to achieve the above object, the present invention provides an embedded operating system loading mode selection circuit, comprising: the CPU comprises a processor GPP, an Ethernet physical layer device PHY, a parallel Flash chip and a complex programmable logic device CPLD, wherein a circuit inside the CPLD comprises a bus reader-writer, an Ethernet link state register, a peripheral reset control generator and a CPU reset control generator, and is characterized in that: the bus reader-writer of the CPLD is respectively connected with the processor GPP through parallel buses; the Ethernet link state register is connected with a link establishment indication pin of the PHY through a discrete line; the peripheral reset control generator is connected with a reset pin of FLASH through one discrete wire, and the other discrete wire is connected with a reset pin of PHY; the CPU reset control generator is connected with a reset pin of GPP through a discrete line; after receiving the access signal of GPP, the bus reader-writer outputs the value of the Ethernet link state register to GPP; the Ethernet link state register is used for judging whether the link is effective or not through the link establishment indication pin level of the PHY, if so, the Ethernet link state register is changed into 1, and if not, the Ethernet link state register is changed into 0.
The invention provides a method for selecting loading modes of an embedded operating system based on the circuit, which comprises the following steps: A. after the embedded system is powered on and reset, a peripheral reset control generator and a CPU reset control generator of the CPLD generate peripheral reset signals and CPU reset signals in sequence, and reset the FLASH and the PHY respectively, and reset the GPP; B. after the PHY is reset, trying to establish a link connection, and the Ethernet link state register receives a link establishment indication signal of the PHY and changes the value of the Ethernet link state register in real time; C. after GPP reset, the value of the Ethernet link state register read by the running BootLoader, bootLoader through a bus reader is selected to be in an embedded operating system loading mode; D. if the value is 1, selecting an Ethernet remote loading mode, and executing Ethernet remote loading of the embedded operating system; if the value is 0, selecting a local memory loading mode, and executing parallel Flash loading of the embedded operating system.
Compared with the prior art, the invention has the following beneficial effects:
the invention adopts the CPLD bus reader-writer to be connected with GPP through control line, data line and address line respectively; the Ethernet link state register is connected with a link establishment indication pin of the PHY through a discrete line; the peripheral reset control generator is connected with a reset pin of FLASH through one discrete wire, and the other discrete wire is connected with a reset pin of PHY; the CPU reset control generator is connected with a reset pin of GPP through a discrete line to form an embedded operating system loading mode selection circuit; the loading mode selection of the embedded operating system is realized through the link state information, the additional hardware cost is not increased, the loading speed is not sacrificed, and the problems that in the prior art, the loading mode selection is realized through a serial port command, the loading speed is influenced by waiting for the overtime of user input in a scene of delivering the user use are solved.
Drawings
The following further describes the technical solution of the present invention with reference to the accompanying drawings, but the protected contents of the present invention are not limited to the following description.
FIG. 1 is a diagram illustrating a loading mode selection circuit of an embedded operating system according to the present invention.
FIG. 2 is a flow chart illustrating the selection of the loading mode of the embedded operating system of FIG. 1.
Detailed Description
See fig. 1. In the embodiments described below, an embedded operating system loading mode selection circuit includes: the system comprises a processor GPP, an Ethernet physical layer device PHY, a parallel Flash chip and a complex programmable logic device CPLD, wherein a circuit inside the CPLD comprises a bus reader-writer, an Ethernet link state register, a peripheral reset control generator and a CPU reset control generator, and the GPP is respectively connected with the FLASH through a parallel bus and connected with the PHY through a medium access control MAC interface. The bus reader-writer of the CPLD is respectively connected with GPP through parallel buses; the Ethernet link state register is connected with a link establishment indication pin of the PHY through a discrete line; the peripheral reset control generator is connected with a reset pin of FLASH through one discrete wire, and the other discrete wire is connected with a reset pin of PHY; the CPU reset control generator is connected with a reset pin of GPP through a discrete line; after receiving the access signal of GPP, the bus reader-writer outputs the value of the Ethernet link state register to GPP; the Ethernet link state register is used for judging whether the link is effective or not through the link establishment indication pin level of the PHY, if so, the Ethernet link state register is changed into 1, and if not, the Ethernet link state register is changed into 0. The CPU reset control generator generates a CPU reset signal to reset GPP. The peripheral reset control generator generates peripheral reset signals to reset FLASH and PHY respectively. The parallel bus includes control lines, data lines, and address lines.
See fig. 2. Based on the loading mode selection circuit of the embedded operating system, the loading mode of the embedded operating system is selected, after the embedded operating system is powered on, the CPLD is powered on to reset, normal operation is started, a peripheral reset control generator generates peripheral reset signals for respectively resetting FLASH and PHY, a CPU reset control generator generates CPU reset signals for resetting GPP, after GPP is reset, the operation BootLoader, bootLoader performs initialization, link connection of PHY is established, an Ethernet link state register establishes an indication pin level through the link of PHY, whether the link is effective or not is judged, the Ethernet link state register is changed into 1, and is invalid, and the Ethernet link state register is changed into 0; and the BootLoader judges whether the value of the Ethernet link state register is 0, if so, the local memory loading mode is selected to execute the parallel Flash loading of the embedded operating system, and otherwise, the Ethernet remote loading mode is selected to execute the Ethernet remote loading of the embedded operating system.
In the loading mode of selecting the embedded operating system, a BootLoader reads the value of an Ethernet link state register through a bus reader-writer, and selects the loading mode of the embedded operating system; when the value read by the bus reader-writer is 1, the network link is successfully established, an Ethernet remote loading mode is selected, and an Ethernet remote loading embedded operating system is executed; if the read value is 0, the network link is not established, a local memory loading mode is selected, and the parallel Flash loading embedded operating system is executed.
The circuit and method provided by the present invention are described in detail below by way of 2 examples.
Example 1
And when debugging or later maintenance is performed, connecting a network cable, and accessing the GPP to a network through the PHY.
After the embedded system is powered on and the CPLD is powered on and self-reset, the embedded system starts to normally run, and a peripheral reset signal is generated through a peripheral reset control generator to reset the parallel Flash and the Ethernet PHY equipment respectively; after the ethernet PHY device is reset, a link connection is established, and since the connection has been established successfully, the value of the ethernet link state register is changed to 1. The CPLD generates a CPU reset signal through a CPU reset control generator to reset GPP. After the GPP is reset, bootLoader starts to be executed. After the BootLoader is initialized, the value of the Ethernet link state register is read through the bus reader-writer, and the value is 1 because the network link is successfully established. And the BootLoader judges whether the value of the Ethernet link state register is 0, the value is 1, the value is not 0, the BootLoader selects an Ethernet remote loading mode, and the Ethernet remote loading embedded operating system is executed.
Example 2
When the user normally uses, the network cable is unplugged, and the network is disconnected.
And after the embedded system is powered on and the CPLD is powered on and reset, the embedded system starts to normally operate. The CPLD generates peripheral reset signals through a peripheral reset control generator, and resets the parallel Flash and Ethernet PHY devices respectively. After the ethernet PHY device is reset, a link connection is established, and the value of the ethernet link state register will be changed to 0 due to the network disconnection and connection establishment failure. The CPLD generates a CPU reset signal through a CPU reset control generator to reset GPP. After the GPP is reset, bootLoader starts to be executed. After the BootLoader is initialized, the value of the Ethernet link state register is read through the bus reader-writer, and is 0 due to failure of network link establishment. And the BootLoader judges whether the value of the Ethernet link state register is 0, the value is 0, the BootLoader selects a local memory loading mode, and the parallel Flash loading embedded operating system is executed.
The invention is not limited to the embodiments described above, but a number of modifications and adaptations can be made by a person skilled in the art without departing from the principle of the invention, which modifications and adaptations are also considered to be within the scope of the invention. What is not described in detail in this specification is prior art known to those skilled in the art.
Claims (8)
1. An embedded operating system loading mode selection circuit comprising: the CPU comprises a processor GPP, an Ethernet physical layer device PHY, a parallel Flash chip and a complex programmable logic device CPLD, wherein a circuit inside the CPLD comprises a bus reader-writer, an Ethernet link state register, a peripheral reset control generator and a CPU reset control generator, and is characterized in that: the bus reader-writer of the CPLD is respectively connected with GPP through parallel buses; the Ethernet link state register is connected with a link establishment indication pin of the PHY through a discrete line; the peripheral reset control generator is connected with a reset pin of FLASH through one discrete wire, and the other discrete wire is connected with a reset pin of PHY; the CPU reset control generator is connected with a reset pin of GPP through a discrete line; after receiving the access signal of GPP, the bus reader-writer outputs the value of the Ethernet link state register to GPP;
the Ethernet link state register establishes an indication pin level through a link of the PHY, judges whether the link is effective, changes the Ethernet link state register into 1 if the link is effective, and changes the Ethernet link state register into 0 if the link is ineffective;
and the GPP judges whether the value of the Ethernet link state register is 0, if so, the local memory loading mode is selected to execute the parallel Flash loading of the embedded operating system, and otherwise, the Ethernet remote loading mode is selected to execute the Ethernet remote loading of the embedded operating system.
2. The embedded operating system loading mode selection circuit of claim 1, wherein: GPP connects FLASH through parallel bus, PHY through medium access control MAC interface.
3. The embedded operating system loading mode selection circuit of claim 1, wherein: the CPU reset control generator generates a peripheral reset signal, and the reset GPP peripheral reset control generator generates a peripheral reset signal to reset FLASH and PHY respectively.
4. The embedded operating system loading mode selection circuit of claim 1, wherein: the parallel bus includes control lines, data lines, and address lines.
5. A method of selecting a loading mode based on the embedded operating system loading mode selection circuit of claim 1, comprising the steps of: based on the loading mode selection circuit of the embedded operating system, the loading mode of the embedded operating system is selected, after the embedded operating system is powered on, the CPLD is powered on to reset, normal operation is started, a peripheral reset control generator generates peripheral reset signals for respectively resetting FLASH and PHY, a CPU reset control generator generates CPU reset signals for resetting GPP, after GPP is reset, the operation BootLoader, bootLoader performs initialization, link connection of PHY is established, an Ethernet link state register establishes an indication pin level through a link of PHY, whether the link is effective or not is judged, the Ethernet link state register is changed into 1 and ineffective, and the Ethernet link state register is changed into 0; and the BootLoader judges whether the value of the Ethernet link state register is 0, if so, the local memory loading mode is selected to execute the parallel Flash loading of the embedded operating system, and otherwise, the Ethernet remote loading mode is selected to execute the Ethernet remote loading of the embedded operating system.
6. The method of selecting a load mode as claimed in claim 5, wherein: in the loading mode of selecting the embedded operating system, a BootLoader reads the value of an Ethernet link state register through a bus reader-writer, and selects the loading mode of the embedded operating system; when the value read by the bus reader-writer is 1, the network link is successfully established, an Ethernet remote loading mode is selected, and an Ethernet remote loading embedded operating system is executed; if the read value is 0, the network link is not established, a local memory loading mode is selected, and the parallel Flash loading embedded operating system is executed.
7. The method of selecting a load mode as claimed in claim 5, wherein: after the embedded system is powered on and the CPLD is powered on and self-reset, the embedded system starts to normally run, and a peripheral reset signal is generated through a peripheral reset control generator to reset the parallel Flash and the Ethernet PHY equipment respectively; after the ethernet PHY device is reset, a link connection is established, the connection is established successfully, and the value of the ethernet link state register is changed to 1.
8. The method of selecting a load mode as claimed in claim 5, wherein: the CPLD generates a CPU reset signal through a CPU reset control generator to reset GPP; after the GPP is reset, the execution is started BootLoader, bootLoader, and after the initialization is completed, the network link is successfully established, and the value of the Ethernet link state register is read by the BootLoader through the bus reader-writer to be 1.
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| CN113504773A (en) * | 2021-07-29 | 2021-10-15 | 安徽江淮汽车集团股份有限公司 | Ethernet test method and Ethernet test system of vehicle-mounted controller |
| CN114124663B (en) * | 2021-11-16 | 2023-12-01 | 太原市华纳方盛科技有限公司 | Method, device and equipment for reconnecting Ethernet chip in disconnected mode |
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| US9185641B2 (en) * | 2013-07-16 | 2015-11-10 | Qualcomm Innovation Center, Inc. | Using discoverable peer-to-peer services to allow remote onboarding of headless devices over a Wi-Fi network |
| CN103389669B (en) * | 2013-07-26 | 2016-06-29 | 中国船舶重工集团公司第七一五研究所 | A kind of processor program Remote Dynamic loading system based on FPGA/CPLD controller and method |
| US9053216B1 (en) * | 2013-08-09 | 2015-06-09 | Datto, Inc. | CPU register assisted virtual machine screenshot capture timing apparatuses, methods and systems |
| CN104156289B (en) * | 2014-07-09 | 2017-10-27 | 中国电子科技集团公司第三十二研究所 | Synchronous control method and system based on detection circuit |
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| CN101132287A (en) * | 2007-09-26 | 2008-02-27 | 中兴通讯股份有限公司 | Method and apparatus for implementing Ethernet link building and package receiving and sending indication |
| CN102932357A (en) * | 2012-11-07 | 2013-02-13 | 中国科学院近代物理研究所 | Accelerator high-frequency digital low-level Ethernet communication system and communication method |
| CN102984059A (en) * | 2012-11-22 | 2013-03-20 | 中国电子科技集团公司第三十二研究所 | Gigabit Ethernet redundant network card and link switching condition determination result control method thereof |
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