CN107707492B

CN107707492B - Method and device for reporting and issuing message

Info

Publication number: CN107707492B
Application number: CN201711171930.3A
Authority: CN
Inventors: 秦永刚
Original assignee: Hangzhou DPTech Technologies Co Ltd
Current assignee: Hangzhou DPtech Information Technology Co Ltd
Priority date: 2017-11-22
Filing date: 2017-11-22
Publication date: 2020-05-12
Anticipated expiration: 2037-11-22
Also published as: CN107707492A

Abstract

The application provides a method for reporting and issuing a message, which comprises the following steps: when a message sent by the FPGA is received, a message header of the message sent by the FPGA is analyzed; searching an interface of the switching equipment connected with the CPU in a prestored forwarding table item according to the message header information of the message sent by the FPGA; reporting the message sent by the FPGA to the CPU through the searched interface connected with the CPU by the switching equipment so that the CPU processes the message sent by the FPGA; when a processed message sent by the CPU is received, the message header of the processed message is analyzed; searching an interface of the switching equipment connected with the FPGA in the prestored forwarding table item according to the message header information of the processed message obtained by analysis; and issuing the processed message to the FPGA through an interface connected with the FPGA by the switching equipment.

Description

Method and device for reporting and issuing message

Technical Field

The present application relates to the field of communications, and in particular, to a method and an apparatus for reporting and issuing a message.

Background

An FPGA (Field-Programmable Gate Array) chip is a Programmable logic chip, and high-speed service processing capability can be realized by writing different program codes, which has obvious advantages compared with the processing capability realized by a traditional CPU. Therefore, the existing high-performance network device basically adopts an FPGA chip as a main service processing chip, and a CPU as a control terminal to realize auxiliary functions. For example, the network protocol message is processed on the CPU, and is reported to the CPU in order to make the CPU process the network protocol message received by the FPGA chip. At present, after receiving a message, an FPGA chip enters a message parsing query flow of the FPGA chip, and if a network protocol message of the network device is queried, the FPGA chip sends the message to a CPU through a PCIE bus through a specified message output interface. However, the bandwidth of the PCIE bus between the FPGA chip and the CPU is limited, and the PCIE bus also needs to bear a channel function of issuing a control instruction to the FPGA chip by the CPU, and if a large number of messages are received and sent between the CPU and the FPGA chip, the CPU is influenced to issue the control instruction to the FPGA chip. On the other hand, the message sent to the CPU by the FPGA chip needs to be encapsulated in a specific header format so that the CPU can correctly analyze the message, and the message sent to the FPGA chip by the CPU also needs to be encapsulated in a specific header format, which increases development effort and makes it impossible to locate the message after a problem occurs.

Disclosure of Invention

In view of this, the present application provides a method and an apparatus for reporting and issuing a message.

Specifically, the method is realized through the following technical scheme:

a method for reporting and sending a message comprises the following steps:

the method comprises the steps that switching equipment analyzes a message header of a message sent by an FPGA under the condition that the message sent by the FPGA is received;

searching an interface of the switching equipment connected with the CPU in a prestored forwarding table item according to the message header information of the message sent by the FPGA;

reporting the message sent by the FPGA to the CPU through the searched interface connected with the CPU by the switching equipment so that the CPU processes the message sent by the FPGA;

the switching equipment analyzes the message header of the processed message under the condition of receiving the processed message sent by the CPU;

searching an interface of the switching equipment connected with the FPGA in the prestored forwarding table item according to the message header information of the processed message obtained by analysis;

and issuing the processed message to the FPGA through an interface connected with the FPGA by the switching equipment.

An apparatus for reporting and issuing a message, the apparatus comprising:

the first message analysis unit is used for analyzing a message header of a message sent by the FPGA under the condition that the switching equipment receives the message sent by the FPGA;

the first interface searching unit is used for searching an interface, connected with the CPU, of the switching equipment in a pre-stored forwarding table item according to the message header information of the message sent by the FPGA;

a first message reporting unit, configured to report the message sent by the FPGA to the CPU through the interface where the found switching device is connected to the CPU, so that the CPU processes the message sent by the FPGA;

a second message parsing unit, configured to, when the switching device receives a processed message sent by the CPU, parse a message header of the processed message;

a second interface searching unit, configured to search, according to the message header information of the processed message obtained through analysis, an interface, where the switching device is connected to the FPGA, in the pre-stored forwarding table entry;

and the second message issuing unit is used for issuing the processed message to the FPGA through an interface connected with the FPGA by the switching equipment.

By adopting the technical scheme of the application, the message is reported and issued by the switching equipment, the development workload of the FPGA and the CPU can be reduced, the complexity of the network equipment is reduced, and the CPU can normally issue the control instruction to the FPGA through the PCIE bus, so that the overall stability of the network equipment is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.

Fig. 1 is a schematic diagram of a connection relationship between an FPGA and a CPU through a PCIE bus according to an exemplary embodiment of the present application;

fig. 2 is a schematic diagram illustrating a connection relationship between a switching device and an FPGA and a CPU according to an exemplary embodiment of the present application;

fig. 3 is a flowchart illustrating an implementation of a method for reporting and issuing a message according to an exemplary embodiment of the present application;

fig. 4 is a schematic diagram illustrating an application scenario in which an FPGA checks a packet according to a packet checking policy to determine whether to upload a CPU according to an exemplary embodiment of the present application;

fig. 5 is a schematic structural diagram of a device for reporting and issuing a message according to an exemplary embodiment of the present application.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

First, a method for reporting and issuing a message provided in an embodiment of the present application is described, where the method may include the following steps:

In the background art, as shown in fig. 1, an FPGA chip is connected to a CPU through a PCIE bus, and after receiving a message, the FPGA chip enters a message parsing query flow of the FPGA chip, and if a network protocol message of the network device is queried, the FPGA chip sends the message to the CPU through a PCIE bus through a designated message output interface, and after the CPU completes processing the network protocol message, the CPU sends the processed network protocol message to the FPGA through the PCIE bus. The technical scheme provided by the application is as an application scene shown in fig. 2, and the application is applied to a system comprising a switching device, an FPGA and a CPU, wherein the connection relationship of the switching device, the FPGA and the CPU is shown in fig. 2, the switching device is connected with the FPGA, and the switching device is connected with the CPU, wherein the FPGA can send messages to the switching device and also can receive messages sent by the switching device; the switching equipment can receive the messages sent by the FPGA and the CPU and can also send the messages to the FPGA and the CPU at the same time; the CPU may receive the message reported by the switching device, or may issue the processed message to the switching device.

After the FPGA receives the message and triggers the flow of reporting the CPU, the message is sent to the switching equipment through an interface connected with the switching equipment; when receiving a message sent by an FPGA, the switching equipment analyzes a message header of the message sent by the FPGA; searching an interface of the switching equipment connected with the CPU in a preset forwarding table item according to the message header information of the message sent by the FPGA; reporting the message sent by the FPGA to the CPU through the searched interface connected with the CPU by the switching equipment so that the CPU processes the message sent by the FPGA; after the CPU finishes processing the message sent by the FPGA, the processed message is sent to the switching equipment, and the switching equipment analyzes the message header of the processed message when receiving the processed message sent by the CPU; searching an interface of the switching equipment connected with the FPGA in the prestored forwarding table item according to the message header information of the processed message obtained by analysis; and issuing the processed message to the FPGA through an interface connected with the FPGA by the switching equipment so that the FPGA forwards the processed message. For further explanation of the present application, the following embodiments are provided, and the switching device is exemplified by a switching chip in the embodiments provided:

as shown in fig. 3, an implementation flowchart of the method for reporting and issuing a message according to the present application may specifically include the following steps:

s101, under the condition that the switching equipment receives a message sent by the FPGA, analyzing a message header of the message sent by the FPGA;

in an embodiment, as shown in fig. 4, when the FPGA receives a message, a network protocol message is taken as an example for description, and when the FPGA checks that the received message is a network protocol message according to a message check policy issued in advance, a flow of reporting to the CPU is triggered, where the message check policy may be set according to its own requirements, for example, a message in a check packet format may be issued, and the FPGA omits the check message according to the policy, and when the flow of reporting to the CPU is triggered, the FPGA sends the received message to the Switch through a

message output interface

3 or 4 of the FPGA, where the Switch takes a Switch chip as an example. When the FPGA sends the message to the Switch through the

message output interface

3 or 4 of the FPGA, a specific message header format needs to be encapsulated, the message header format is suitable for message transmission between chips, and is temporarily named as hig message header, the source input interface of the message is encapsulated as the input interface of the FPGA, such as the input interface 1 of the FPGA, and the destination input interface is encapsulated as the input interface of the CPU, such as the input interface 0 of the CPU. When receiving a message sent by the FPGA, the switch chip parses the header of the message sent by the FPGA, that is, parses the header in a specific format, and parses a source input interface and a destination input interface of the message, for example, parses hig the source input interface of the header being an input interface 1 of the FPGA, and the destination input interface being an input interface 0 of the CPU.

S102, searching an interface of the switching equipment connected with the CPU in a prestored forwarding table item according to the message header information of the message sent by the FPGA;

in an embodiment, as described above, the source input interface is an input interface 1 of the FPGA, and the destination input interface is an input interface 0 of the CPU, and the interface where the switch chip is connected to the CPU is searched in a pre-stored forwarding table entry according to the header information obtained by the analysis. As shown in table 1 below, the message output interface of the switch chip can be queried according to the source input interface and the destination input interface, and the message output interface of the switch chip is connected to the message input interface of the CPU.

Source-in interface	Destination entry interface	Message output interface
			FPGA-1	CPU-0	Switch-0
FPGA-2	CPU-0	Switch-0

TABLE 1

The pre-stored forwarding table entry is generated and pre-stored in the switching chip based on the connection relationship between the switching chip and the FPGA, the CPU, and the physical structure, and the purpose defined when the chip pins are shipped, for example, the interface 3 of the FPGA is connected to the interface 3 of the switching chip, the interface 4 of the FPGA is connected to the interface 2 of the switching chip, the interface 0 of the switching chip is connected to the interface 0 of the CPU, and the forwarding table entry is pre-stored in the switching chip based on the connection relationship between the source interface and the destination interface and the connection relationship between the interfaces.

S103, reporting the message sent by the FPGA to the CPU through the searched interface connected with the CPU by the switching equipment so that the CPU processes the message sent by the FPGA;

in an embodiment, according to the found interface where the switch chip is connected to the CPU, determining a packet sending function corresponding to the found interface where the switch chip is connected to the CPU, calling the determined packet sending function according to destination entry interface information carried in the message sent by the FPGA obtained through the analysis, and reporting the message sent by the FPGA to the CPU through the found interface where the switch device is connected to the CPU, so that the CPU processes the message sent by the FPGA. For example, the found message output interface Switch-0 of the Switch chip is connected to the CPU-0 input interface of the CPU, then the packet sending function a corresponding to the message output interface Switch-0 is determined, the packet sending function a is called according to the destination input interface CPU-0 carried by the message sent by the FPGA, and the message sent by the FPGA is reported to the CPU through the found message output interface Switch-0, so that the CPU processes the message.

When the CPU receives the message reported by the switch chip, it reads the message into the memory first, and analyzes the hig message header of the message, so as to know that the message is the message reported by the FPGA, and at this time, the incoming interface of the message needs to be replaced by the incoming interface 1 of the FPGA, and the message is sent to the protocol stack for protocol processing. After the protocol stack processes the message, the output interface of the FPGA is directly appointed to transmit, the FPGA receives the message through the input interface 1 of the FPGA, the output interface of the message appointed by the protocol stack is the output interface 1 of the FPGA, and the input interface 1 of the FPGA and the output interface 1 of the FPGA are both the interface 1 of the FPGA. At this time, an hig message header is also required to be encapsulated for the processed message, the destination output interface of the message is modified into the output interface 1 of the FPGA, and then the processed message is issued to the CPU.

S104, the switching equipment analyzes the message header of the processed message under the condition of receiving the processed message sent by the CPU;

in an embodiment, when the switch chip receives the processed packet sent by the CPU, it parses hig packet header of the processed packet, and parses a source output interface and a destination output interface carried by the processed packet sent by the CPU, that is, the source output interface in the hig packet header is encapsulated as the output interface of the CPU, the destination output interface is encapsulated as the output interface of the FPGA, for example, in the hig packet header, the destination output interface of the packet is encapsulated as the output interface 1 of the FPGA, and the source output interface of the packet is encapsulated as the output interface 0 of the CPU.

S105, searching an interface of the switching equipment connected with the FPGA in the prestored forwarding table item according to the message header information of the processed message obtained by analysis;

in an embodiment, whether the processed message is a message issued to the FPGA is determined according to the source output interface and destination output interface information carried by the processed message obtained through analysis, and when the processed message is the message issued to the FPGA, an interface connecting the switching device and the FPGA is searched in the pre-stored forwarding table entry. The switching chip can receive messages sent by other devices, so when receiving a message issued by the CPU, it needs to determine whether the message issued by the CPU is a message issued to the FPGA, and if not, it also needs to search a message output interface of the switching chip in a pre-stored forwarding table entry, and issue the message to other devices. For example, the destination output interface of the message is packaged into the output interface 1 of the FPGA, the source output interface of the message is packaged into the output interface 0 of the CPU, and the destination output interface (the output interface 1 of the FPGA) carried by the message can determine that the processed message is a message issued to the FPGA, as shown in table 2 below, an interface where the switch chip is connected to the FPGA is searched in a pre-stored forwarding table entry.

Source-out interface	Destination outlet interface	Message output interface
			CUP-0	FPGA-1	Switch-1
CUP-0	FPGA-2	Switch-2

TABLE 2

As can be seen from table 2, the message output interface of the Switch chip can be known according to the source output interface and the destination output interface, where when the Switch chip receives a message sent by the FPGA, the

message input interface

1 or 2 and the

message output interface

1 or 2 may be Switch-1 or Switch-2 shown in table 2. The destination output interface (FPGA-1) can know that the message output interface is Switch-1, wherein Switch-1 is connected with FPGA-3, and Switch-2 is connected with FPGA-4.

And S106, issuing the processed message to the FPGA through an interface connected with the FPGA by the switching equipment.

In an embodiment, a packet sending function corresponding to an interface of the switching device connected to the FPGA is determined according to the interface of the switching chip connected to the FPGA, the determined packet sending function is called according to destination output interface information carried by the processed packet obtained through analysis, and the processed packet is sent to the FPGA through the interface of the switching device connected to the FPGA. For example, according to the interface Switch-1 connected with the switching chip and the FPGA found, the packet sending function b corresponding to the interface Switch-1 can be determined, the packet sending function b is called according to the destination output interface information FPGA-1 carried by the processed packet obtained through analysis, and the processed packet is sent to the FPGA through the interface Switch-1 connected with the switching chip and the FPGA found. When the FPGA receives the processed message issued by the switching chip through the FPGA-3 interface, the hig message header is firstly analyzed, namely the destination output interface FPGA-1 is analyzed, then the hig message header of the processed message is removed, a packet sending function corresponding to the FPGA-1 is called, and the message with the hig message header removed is sent out through the FPGA-1 interface.

Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Corresponding to the embodiment of the method for reporting and issuing the message, the application also provides an embodiment of a device for reporting and issuing the message. As shown in fig. 5, the apparatus includes a first packet parsing unit 210, a first interface searching unit 220, a first packet reporting unit 230, a second packet parsing unit 240, a second interface searching unit 250, and a second packet issuing unit 260.

The first message parsing unit 210 is configured to, when receiving a message sent by an FPGA, a switching device parses a message header of the message sent by the FPGA;

the first interface searching unit 220 is configured to search, according to the analyzed message header information of the message sent by the FPGA, an interface, where the switching device is connected to the CPU, in a pre-stored forwarding table entry;

the first message reporting unit 230 is configured to report the message sent by the FPGA to the CPU through the found interface where the switching device is connected to the CPU, so that the CPU processes the message sent by the FPGA;

the second message parsing unit 240 is configured to, when receiving a processed message sent by the CPU, the switching device parses a message header of the processed message;

the second interface searching unit 250 is configured to search, according to the analyzed message header information of the processed message, an interface, where the switching device is connected to the FPGA, in the pre-stored forwarding table entry;

the second packet issuing unit 260 is configured to issue the processed packet to the FPGA through an interface connected to the switching device and the FPGA.

In a specific embodiment of the present application, the first interface searching unit 220 is specifically configured to:

and searching an interface of the switching equipment connected with the CPU in a prestored forwarding table item according to the source input interface and the destination input interface information carried by the message sent by the FPGA.

In a specific embodiment of the present application, the first packet reporting unit 230 is specifically configured to:

determining a packet sending function corresponding to the interface of the searched switching equipment connected with the CPU according to the interface of the searched switching equipment connected with the CPU, calling the determined packet sending function according to destination interface information carried by the message sent by the FPGA, and reporting the message sent by the FPGA to the CPU through the interface of the searched switching equipment connected with the CPU so that the CPU processes the message sent by the FPGA.

In a specific embodiment of the present application, the second interface searching unit 250 is specifically configured to:

and searching an interface of the switching equipment connected with the FPGA in the pre-stored forwarding table entry according to the source output interface and the destination output interface information carried by the processed message obtained by analysis.

In a specific embodiment of the present application, the second interface searching unit 250 includes: judging subunit and second interface searching subunit

The judging subunit is configured to judge whether the processed packet sent by the CPU is a packet sent to the FPGA, according to the source output interface and the destination output interface information carried by the processed packet obtained through analysis;

and the second interface searching subunit is used for searching the interface, connected with the FPGA, of the switching equipment in the pre-stored forwarding table entry under the condition that the processed message issued by the CPU is a message issued to the FPGA.

In a specific embodiment of the present application, the second packet issuing unit 260 is specifically configured to:

determining a packet sending function corresponding to the interface of the switching equipment connected with the FPGA according to the interface of the switching equipment connected with the FPGA, calling the determined packet sending function according to the analyzed destination output interface information carried by the processed message, and sending the processed message to the FPGA through the interface of the switching equipment connected with the FPGA.

The implementation process of the functions of each unit in the system is specifically described in the implementation process of the corresponding step in the method, and is not described herein again.

For the system embodiment, since it basically corresponds to the method embodiment, reference may be made to the partial description of the method embodiment for relevant points. The above-described system embodiments are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.

The invention may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

The foregoing is directed to embodiments of the present invention, and it is understood that various modifications and improvements can be made by those skilled in the art without departing from the spirit of the invention.

Claims

1. A method for reporting and sending messages is characterized in that the method is applied to a system comprising an FPGA, a switching device and a CPU, wherein the switching device is connected with the FPGA and the CPU, and the method comprises the following steps:

reporting the message sent by the FPGA to the CPU through an interface connected with the CPU through the switching equipment so that the CPU processes the message sent by the FPGA;

2. The method according to claim 1, wherein the searching for the interface between the switching device and the CPU in a pre-stored forwarding table entry according to the header information of the packet sent by the FPGA obtained through parsing comprises:

3. The method according to claim 2, wherein the reporting the message sent by the FPGA to the CPU through the interface between the found switching device and the CPU so that the CPU processes the message sent by the FPGA comprises:

4. The method according to claim 1, wherein the searching for the interface between the switching device and the FPGA in the pre-stored forwarding table entry according to the analyzed header information of the processed packet comprises:

5. The method according to claim 4, wherein the searching for the interface, which is connected to the FPGA, of the switching device in the pre-stored forwarding table entry according to the source output interface and the destination output interface information carried in the processed packet obtained by the parsing includes:

judging whether the processed message sent by the CPU is a message sent to the FPGA or not according to the analyzed source output interface and destination output interface information carried by the processed message;

and searching an interface of the switching equipment connected with the FPGA in the pre-stored forwarding table entry under the condition that the processed message issued by the CPU is a message issued to the FPGA.

6. The method of claim 5, wherein issuing the processed message to the FPGA via the interface of the switching device connected to the FPGA comprises:

7. An apparatus for reporting and issuing a message, the apparatus comprising:

the first message reporting unit is used for reporting the message sent by the FPGA to the CPU through an interface connected with the CPU through the switching equipment so that the CPU processes the message sent by the FPGA;

8. The apparatus according to claim 7, wherein the first interface lookup unit is specifically configured to:

9. The apparatus of claim 7, wherein the first packet reporting unit is specifically configured to:

10. The apparatus according to claim 7, wherein the second interface lookup unit is specifically configured to: