CN107682126A - A kind of ethernet network transmission performance test device - Google Patents
A kind of ethernet network transmission performance test device Download PDFInfo
- Publication number
- CN107682126A CN107682126A CN201711177802.XA CN201711177802A CN107682126A CN 107682126 A CN107682126 A CN 107682126A CN 201711177802 A CN201711177802 A CN 201711177802A CN 107682126 A CN107682126 A CN 107682126A
- Authority
- CN
- China
- Prior art keywords
- circuit
- test
- frame
- configurable
- markers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
- H04L43/0817—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
- H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Quality & Reliability (AREA)
- Environmental & Geological Engineering (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a kind of ethernet network transmission performance test device, belongs to network service testing field, including send with receiving two parts；Transmitting portion is mainly inserted circuit, verification insertion circuit and output circuit by test frame data-storing circuit, frame period control circuit, burst control circuitry, time control circuit, transmission state machine, markers sequence number and formed；Receiving portion is mainly extracted circuit, test frame statistical circuit, pseudo-random sequence and is extracted circuit, resetting time test circuit, delay testing circuit, recovery time test circuit, packet loss test circuit, testing throughput circuit, error code testing circuit and test result memory and formed by input circuit, test frame identification circuit, error checking circuit, transmission markers extraction circuit, reception markers latch cicuit, sequence number.The present invention can once complete the test of over-all properties parameter, improve testing efficiency, shorten the testing time.
Description
Technical field
The invention belongs to network service testing field, and in particular to a kind of ethernet network transmission performance test device.
Background technology
Network technology is used widely, speed more and more higher transmission rate.It is very high to network communication equipment testing requirement.
How to simulate the data of real network is one of key technology of network transmission test.In ethernet test typically now
All it is to edit a kind of static data frame respectively, carries out single parameter test, and the test frame of each producer is incompatible, it is impossible to mutually
Tested.
The content of the invention
For above-mentioned technical problem present in prior art, the present invention proposes a kind of ethernet network transmission performance and surveyed
Trial assembly is put, and edits a kind of test frame, can once complete the test of all-network transmission performance parameter.It is reasonable in design, overcome existing
There is the deficiency of technology, improve testing efficiency, there is good application effect.
To achieve these goals, the present invention adopts the following technical scheme that：
A kind of ethernet network transmission performance test device, the form of ethernet test frame is defined first：
One or more test frames are edited, each test frame includes source MAC, target MAC (Media Access Control) address, source IP address, mesh
IP address, test flag of frame, test data and time marks；Wherein, source MAC, target MAC (Media Access Control) address, source in test frame
IP address, purpose IP address determine according to test scene；Test frame length value in test frame according to the frame length that user sets and
It is fixed, the test frame length value=byte of frame length -46；Test data in test frame is set by the user, test data length=test
The byte of frame length angle value -12；Pseudo-random sequence in test frame is continuous；Time mark in test frame passes through FPGA circuitry certainly
Dynamic generation is simultaneously synthesized in test frame when sending；
Ethernet network transmission performance test device, specifically includes transmitting portion and receiving portion；
Transmitting portion, it is configurable for completing construction test frame and sends test frame；Mainly by test frame number
It is electromechanical according to storage circuit, frame period control circuit, burst control circuitry, time control circuit, address control circuit, transmission state
Road, markers sequence number insertion circuit, send sequence number with markers occur circuit, send markers latch cicuit, verification insertion circuit with it is defeated
Go out circuit composition；
Test frame data-storing circuit, it is configurable for the frame data of storage test frame definition；
Frame period control circuit, it is configurable for controlling the interval time length between every frame；
Burst control circuitry, it is configurable for the quantity that control continuously transmits frame；
Time control circuit, it is configurable for controlling the sending duration of test frame；
Address control circuit, it is configurable for carrying out the RFC2544 tests of multiport, needs to reach by test frame automatically
MAC destination addresses, IP destination addresses and the channel recognition number of port are inserted into test frame；
State machine circuit is sent, is configurable for generating test frame；
Markers sequence number inserts circuit, is configurable for the sequence number of currently transmitted frame and markers being inserted into currently transmitted
In frame；
Send sequence number and circuit occurs with markers, marked for producing to send sequence number with the time, electricity is inserted using markers sequence number
Road, which is inserted into, to be sent in frame；
Send markers latch cicuit, be configurable for test system recovery time, when by overload speed sent test
Last markers is latched during the cycle, then resends test frame by normal speed, and continue time test period with
Threshold time sum；
Verification insertion circuit, it is configurable for last four bytes of CRC32 check values insertion frame that will be calculated
Position；
Output circuit is configurable for sending whole test frame；
Receiving portion, it is configurable for completing reception, identification and the measurement of each parameter of test frame；Mainly by inputting
Circuit, test frame identification circuit, test Framing Error Detection circuit, transmission markers extraction circuit, reception markers latch cicuit, sequence number
Extract circuit, test frame statistical circuit, pseudo-random sequence extraction circuit, resetting time test circuit, delay testing circuit, recovery
Time test circuit, packet loss test circuit, testing throughput circuit, error code testing circuit and test result memory form；
Input circuit, it is configurable for the ethernet frame that reception processing reaches the port, including test frame and non-test
Frame；
Test frame identification circuit, it is configurable for continuing detection test frame flag, and length byte will be latched into thereafter
In one RAM, and judge whether actually detected test frame length is consistent with the length of latch in frame end；
Framing Error Detection circuit is tested, is configurable for carrying out error detection to the test frame identified, predominantly detects
Whether correct test frame check, if incorrect, directly give up, no longer carry out following operation；
Markers extraction circuit is sent, is configurable for extracting the transmission markers in effective markers test frame；
Markers latch cicuit is received, is configurable for latching the due in of all test frames；
Sequence number extracts circuit, is configurable for extracting sending sequence number in test frame；
Test frame statistical circuit, it is configurable for counting the number of all effective markers test frames, it is flat for calculating
Equal interval time (interval time=this frame arrival time-upper frame arrival time), i.e. jitter value；
Pseudo-random sequence extracts circuit, is configurable for separating puppet from the test frame received
Random sequence data, it is sent to error code testing circuit and carries out error code testing；
Resetting time test circuit, it is configurable for continuously latching two adjacent lost frames due ins, its difference
As system recovery time；
Delay testing circuit, is configurable for continuously counting the time delay of all delay testing frames, and locks
Deposit maximum delay time and minimum delay time；
Recovery time test circuit, it is configurable for latching the delay testing reached when exceeding time threshold after LOF
At the time of frame, the transmission markers that the moment latches with sender is subtracted each other, you can obtain system recovery time；
Packet loss test circuit, is configurable for the test number of frames received after statistical test starts, and with transmission
Frame data be compared, calculate packet loss；
Testing throughput circuit, it is configurable for after statistical test starts, the full test received in the unit interval
Number of frames, and compared with the frame data of transmission, calculate handling capacity；
Error code testing circuit, it is configurable for from test frame sharing caused by the pseudo-random sequence and receiving terminal
Pseudo-random sequence carries out bit synchronous, and detection makes mistake, and calculates the bit error rate；
Test result memory, it is configurable for storing whole test results.
Advantageous effects caused by the present invention：
(1) the test frame format suitable for whole parameter testings is defined, reduces the species of test frame, have is made using programming
With, reduction programing work amount, raising efficiency.
(2) whole parameter testings of network transmission performance can be disposably completed, shorten the testing time；
(3) the Ethernet transmission performance test being applied to below 10Gbps speed；
Brief description of the drawings
Fig. 1 is test frame definition format schematic diagram.
Fig. 2 is the theory diagram of transmitting portion of the present invention.
Fig. 3 is the theory diagram of receiving portion of the present invention.
Embodiment
Below in conjunction with the accompanying drawings and embodiment is described in further detail to the present invention：
The present invention proposes a kind of ethernet network transmission performance test device, edits a kind of test frame, can once complete
The test of all-network transmission performance parameter.
As shown in figure 1, invention defines a kind of ethernet test frame.Test includes source MAC (6 byte), mesh
MAC Address (6 byte), type (2 byte), IP heads (20 byte), UDP heads (8 byte), test data part (N words
Section) and CRC check (4 byte).Source MAC therein, target MAC (Media Access Control) address, source IP address, purpose IP address can preset one
Individual fixed value, if test needs, hardware circuit that can be as shown in Figure 2 automatically generates dynamic address.CRC check is as shown in Figure 2
Hardware circuit automatically generates.
Test data part by test frame ID (4 byte), test frame length (2 byte), test data (N-12 bytes) with
Time mark (6 byte) composition.Test frame ID is to be fixed as a character, and test frame length value is determined according to test data partial-length
It is fixed.The hardware circuit of time mark as shown in Figure 2 automatically generates.The hardware circuit of test data part as shown in Figure 2 is given birth to automatically
Into for a certain pseudo-random sequence (such as 2 of settingn- 1 sequence, n=11,13,15,17,20,23,31) in a part.Often
It is exactly a complete pseudo-random sequence that this data in one frame, which connect,.
The use of frame format is tested shown in Fig. 1 is that each sending port sets one or more test frames.Each test frame number
According to the frame data memory of write-in transtation mission circuit.Each frame maximum length is 16384 bytes.
As shown in Fig. 2 transmitting portion is mainly by test frame data-storing circuit, frame period control circuit, burst control electricity
Road, time control circuit, address control circuit, transmission state machine circuit, markers sequence number insertion circuit, transmission markers latch electricity
Road, verification insertion circuit and output circuit form.
Test the frame data write-in test frame data memory of frame definition；According to frame period control circuit and burst control electricity
Timing generation test frame caused by road；The sending duration of test frame is realized by time control circuit；Address control circuit is used
Tested in the RFC2544 of multiport, it automatically by test frame need to reach the MAC destination addresses of port, IP destination addresses and
Channel recognition number is inserted into test frame；Send state machine circuit and generate test frame according to these information；Markers is inserted with sequence number
The sequence number of currently transmitted frame and markers are inserted into currently transmitted frame by circuit；Marking of control circuit is used to test time delay, when
, it is necessary to insert a delay testing mark when test frame sends half, identify that extraction sends markers for receiving portion；During transmission
Mark latch cicuit is used for test system recovery time, and last markers is latched when having sent test period by overload speed,
Then test frame is resend by normal speed, and continues time test period and threshold time sum；Terminal check is inserted
Enter last four byte locations that circuit inserts the CRC32 check values being calculated frame, output circuit sends out whole test frame
See off.
As shown in figure 3, receiving portion, is configurable for completing reception, identification and the measurement of each parameter of test frame；
Mainly by input circuit, test frame identification circuit, test Framing Error Detection circuit, transmission markers extraction circuit, reception markers lock
Circuit, sequence number extraction circuit, test frame statistical circuit, pseudo-random sequence extraction circuit, resetting time test circuit, time delay is deposited to survey
Try circuit, recovery time test circuit, packet loss test circuit, testing throughput circuit, error code testing circuit and test result
Memory forms.
The input circuit reception processing of receiving terminal reaches the ethernet frame of the port, including test frame and non-test frame.Survey
Frame identification circuit, lasting detection test frame flag are tried, and length byte will be latched into a RAM thereafter, and in frame end
Judge whether actually detected test frame length is consistent with the length of latch.The design supports the nesting of test frame, and always opens
With last effective test frame.Test Framing Error Detection circuit carries out error detection, main inspection to the test frame identified
Whether test frame check is correct, if incorrect, directly gives up, no longer carries out following operation.
Input circuit, it is configurable for the ethernet frame that reception processing reaches the port, including test frame and non-test
Frame；
Test frame identification circuit, it is configurable for continuing detection test frame flag, and length byte will be latched into thereafter
In one RAM, and judge whether actually detected test frame length is consistent with the length of latch in frame end；
Framing Error Detection circuit is tested, is configurable for carrying out error detection to the test frame identified, predominantly detects
Whether correct test frame check, if incorrect, directly give up, no longer carry out following operation；
Markers extraction circuit is sent, is configurable for extracting the transmission markers in effective markers test frame；
Markers latch cicuit is received, is configurable for latching the due in of all test frames；
Sequence number extracts circuit, is configurable for extracting sending sequence number in test frame；
Test frame statistical circuit, it is configurable for counting the number of all effective markers test frames, it is flat for calculating
Equal interval time (interval time=this frame arrival time-upper frame arrival time), i.e. jitter value；
Pseudo-random sequence extracts circuit, is configurable for separating puppet from the test frame received
Random sequence data, it is sent to error code testing circuit and carries out error code testing；
Resetting time test circuit, it is configurable for continuously latching two adjacent lost frames due ins, its difference
As system recovery time；
Delay testing circuit, is configurable for continuously counting the time delay of all delay testing frames, and locks
Deposit maximum delay time and minimum delay time；
Recovery time test circuit, it is configurable for latching the delay testing reached when exceeding time threshold after LOF
At the time of frame, the transmission markers that the moment latches with sender is subtracted each other, you can obtain system recovery time；
Packet loss test circuit, is configurable for the test number of frames received after statistical test starts, and with transmission
Frame data be compared, calculate packet loss；
Testing throughput circuit, it is configurable for after statistical test starts, the full test received in the unit interval
Number of frames, and compared with the frame data of transmission, calculate handling capacity；
Error code testing circuit, it is configurable for from test frame sharing caused by the pseudo-random sequence and receiving terminal
Pseudo-random sequence carries out bit synchronous, and detection makes mistake, and calculates the bit error rate；
Test result memory, it is configurable for storing whole test results, and timing is sent to master by data/address bus
Machine, form test report or test curve figure.
Certainly, described above is not limitation of the present invention, and the present invention is also not limited to the example above, this technology neck
The variations, modifications, additions or substitutions that the technical staff in domain is made in the essential scope of the present invention, it should also belong to the present invention's
Protection domain.
Claims (1)
- A kind of 1. ethernet network transmission performance test device, it is characterised in that：The form of ethernet test frame is defined first：One or more test frames are edited, each test frame includes source MAC, target MAC (Media Access Control) address, source IP address, purpose IP Address, test flag of frame, test data and time mark；Wherein, source MAC, target MAC (Media Access Control) address, source IP in test frame Location, purpose IP address determine according to test scene；Depending on the frame length that test frame length value in test frame is set according to user, survey Try frame length angle value=byte of frame length -46；Test data in test frame is set by the user, test data length=test frame length It is worth -12 bytes；Pseudo-random sequence in test frame is continuous；Time mark in test frame is automatically generated by FPGA circuitry And it is synthesized to when sending in test frame；Ethernet network transmission performance test device, specifically includes transmitting portion and receiving portion；Transmitting portion, it is configurable for completing construction test frame and sends test frame；Mainly deposited by test frame data Store circuit, frame period control circuit, burst control circuitry, time control circuit, address control circuit, send state machine circuit, Markers sequence number insertion circuit, sending sequence number occurs circuit with markers, sends markers latch cicuit, verification insertion circuit and output electricity Road forms；Test frame data-storing circuit, it is configurable for the frame data of storage test frame definition；Frame period control circuit, it is configurable for controlling the interval time length between every frame；Burst control circuitry, it is configurable for the quantity that control continuously transmits frame；Time control circuit, it is configurable for controlling the sending duration of test frame；Address control circuit, is configurable for carrying out the RFC2544 tests of multiport, automatically needs test frame to reach port MAC destination addresses, IP destination addresses and channel recognition number be inserted into test frame；State machine circuit is sent, is configurable for generating test frame；Markers sequence number inserts circuit, is configurable for for the sequence number of currently transmitted frame and markers being inserted into currently transmitted frame In；Send sequence number and circuit occurs with markers, marked for producing to send sequence number with the time, inserted using markers sequence number insertion circuit Enter into transmission frame；Send markers latch cicuit, be configurable for test system recovery time, when by overload speed sent test period Last markers of Shi Suocun, then resends test frame by normal speed, and continues time test period and thresholding Time sum；Verification insertion circuit, it is configurable for last four byte locations of CRC32 check values insertion frame that will be calculated；Output circuit is configurable for sending whole test frame；Receiving portion, it is configurable for completing reception, identification and the measurement of each parameter of test frame；Mainly by input electricity Road, test frame identification circuit, test Framing Error Detection circuit, transmission markers extraction circuit, reception markers latch cicuit, sequence number carry When sense circuit, test frame statistical circuit, pseudo-random sequence extraction circuit, resetting time test circuit, delay testing circuit, recovery Between test circuit, packet loss test circuit, testing throughput circuit, error code testing circuit and test result memory form；Input circuit, it is configurable for the ethernet frame that reception processing reaches the port, including test frame and non-test frame；Test frame identification circuit, it is configurable for continuing detection test frame flag, and one will be latched into by length byte thereafter In RAM, and judge whether actually detected test frame length is consistent with the length of latch in frame end；Framing Error Detection circuit is tested, is configurable for carrying out error detection to the test frame identified, predominantly detects test Whether frame check is correct, if incorrect, directly gives up, and no longer carries out following operation；Markers extraction circuit is sent, is configurable for extracting the transmission markers in effective markers test frame；Markers latch cicuit is received, is configurable for latching the due in of all test frames；Sequence number extracts circuit, is configurable for extracting sending sequence number in test frame；Test frame statistical circuit, it is configurable for counting the number of all effective markers test frames, between calculating averagely Every time, i.e. jitter value；Pseudo-random sequence extracts circuit, is configurable for separating pseudorandom from the test frame received Sequence data, it is sent to error code testing circuit and carries out error code testing；Resetting time test circuit, it is configurable for continuously latching two adjacent lost frames due ins, its difference is System recovery time；Delay testing circuit, it is configurable for continuously counting the time delay of all delay testing frames, and latches most Big time delay and minimum delay time；Recovery time test circuit, it is configurable for latching the delay testing frame that is reached after LOF when exceeding time threshold At the moment, the transmission markers that the moment latches with sender is subtracted each other, you can obtain system recovery time；Packet loss test circuit, is configurable for the test number of frames received after statistical test starts, and with the frame of transmission Data are compared, and calculate packet loss；Testing throughput circuit, it is configurable for after statistical test starts, the full test frame number received in the unit interval Amount, and compared with the frame data of transmission, calculate handling capacity；Error code testing circuit, be configurable for from test frame sharing puppet caused by the pseudo-random sequence and receiving terminal with Machine sequence carries out bit synchronous, and detection makes mistake, and calculates the bit error rate；Test result memory, it is configurable for storing whole test results.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711177802.XA CN107682126B (en) | 2017-11-23 | 2017-11-23 | Ethernet network transmission performance testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711177802.XA CN107682126B (en) | 2017-11-23 | 2017-11-23 | Ethernet network transmission performance testing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107682126A true CN107682126A (en) | 2018-02-09 |
| CN107682126B CN107682126B (en) | 2020-10-09 |
Family
ID=61150523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711177802.XA Active CN107682126B (en) | 2017-11-23 | 2017-11-23 | Ethernet network transmission performance testing device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107682126B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111934820A (en) * | 2020-07-29 | 2020-11-13 | 烽火通信科技股份有限公司 | Management information transmission method, system and readable storage medium |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11994938B2 (en) | 2021-11-11 | 2024-05-28 | Samsung Electronics Co., Ltd. | Systems and methods for detecting intra-chip communication errors in a reconfigurable hardware system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040208129A1 (en) * | 2003-04-17 | 2004-10-21 | Agilent Technologies, Inc. | Testing network communications |
| CN103078767A (en) * | 2012-12-31 | 2013-05-01 | 中国电子科技集团公司第四十一研究所 | Method and device for testing throughput of WAN (Wide Area Network) at single port and at full wire speed |
| CN106375161A (en) * | 2016-12-06 | 2017-02-01 | 中国电子科技集团公司第四十研究所 | 10-gigabit Ethernet tester |
| CN107241238A (en) * | 2017-06-09 | 2017-10-10 | 中国电子科技集团公司第四十研究所 | A kind of network testing device of hand-held 10,000,000,000 |
-
2017
- 2017-11-23 CN CN201711177802.XA patent/CN107682126B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040208129A1 (en) * | 2003-04-17 | 2004-10-21 | Agilent Technologies, Inc. | Testing network communications |
| CN103078767A (en) * | 2012-12-31 | 2013-05-01 | 中国电子科技集团公司第四十一研究所 | Method and device for testing throughput of WAN (Wide Area Network) at single port and at full wire speed |
| CN106375161A (en) * | 2016-12-06 | 2017-02-01 | 中国电子科技集团公司第四十研究所 | 10-gigabit Ethernet tester |
| CN107241238A (en) * | 2017-06-09 | 2017-10-10 | 中国电子科技集团公司第四十研究所 | A kind of network testing device of hand-held 10,000,000,000 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111934820A (en) * | 2020-07-29 | 2020-11-13 | 烽火通信科技股份有限公司 | Management information transmission method, system and readable storage medium |
| CN111934820B (en) * | 2020-07-29 | 2022-08-05 | 烽火通信科技股份有限公司 | Management information transmission method, system and readable storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107682126B (en) | 2020-10-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103765823B (en) | Method and system for the OAM that the controller of open flows encourages | |
| US7594159B2 (en) | Signature field in a latency measurement frame | |
| US20180241586A1 (en) | Path Detection Method in VxLAN, Controller, and Network Device | |
| CN103490961B (en) | Network equipment | |
| CN105279254B (en) | The implementation method of format data streamed file system and its operating device and its operating device | |
| CN107682126A (en) | A kind of ethernet network transmission performance test device | |
| CN102291272A (en) | Method of remote active testing of a device or network | |
| CN104836705A (en) | Method for performing calibration time delay error testing on time delay calibration switch of intelligent substation | |
| CN101800671B (en) | Method for detecting packet loss of H.264 video file | |
| CN102916759B (en) | Method for calibrating E1 data frame precision time and processing time mark information | |
| CN104219122A (en) | Detection method for quickly positioning far-end ONU (optical network unit) loop ports by OLT (optical line terminal) local sides | |
| CN106375158A (en) | Packet loss detection method, network device and system | |
| CN106375161A (en) | 10-gigabit Ethernet tester | |
| CN105162649B (en) | For the test method and its system of npp safety grade network performance index | |
| CN103428227A (en) | IP covert communication method based on Huffman encoding | |
| CN107659537A (en) | The apparatus and method of the swapping data of physically-isolated network | |
| CN110868458B (en) | Communication method and device for stable control system | |
| CN102143155B (en) | Covert communication method based on IPID (Internet Protocol Identification) bit delta modulation | |
| CN103746868B (en) | A kind of method, device and test equipment for sending and receiving test packet | |
| CN104009982B (en) | File grouping group sending device and file grouping method for group sending based on ultrashort wave radio set | |
| CN105933094A (en) | Covert communication detection method specific to multilink arrival sequence coding | |
| CN104993976A (en) | Method and system for evaluating PLC safety protection equipment | |
| CN106406793B (en) | The identity configuration method and system and IP address distribution method and system of Node station | |
| RU2622788C1 (en) | Method for protecting information-computer networks against cyber attacks | |
| CN104135439A (en) | Method for rapidly generating an ICMP error message |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |