CN107679009A - Generalization hardware and software platform based on heterogeneous polynuclear framework - Google Patents
Generalization hardware and software platform based on heterogeneous polynuclear framework Download PDFInfo
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- CN107679009A CN107679009A CN201711041804.6A CN201711041804A CN107679009A CN 107679009 A CN107679009 A CN 107679009A CN 201711041804 A CN201711041804 A CN 201711041804A CN 107679009 A CN107679009 A CN 107679009A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
Abstract
The invention discloses a kind of generalization hardware and software platform based on heterogeneous polynuclear framework, comprising isomerization hardware platform, intermediate layer CORBA modules and application program module, isomerization hardware platform includes the first hardware platform being made up of GPP, the second hardware platform being made up of ARM and DSP, the 3rd hardware platform being made up of ARM and FPGA；Application program module is separately operable in the first hardware platform, the second hardware platform and the 3rd hardware platform, completes respective wave data processing；Intermediate layer CORBA modules are separately operable and in the first hardware platform, the second hardware platform and the 3rd hardware, form the logic interaction that general hardware driving interface makes Wave data between the first hardware platform, the second hardware platform and the 3rd hardware.The present invention realizes GPP+DSP+FPGA indifference data transfer.
Description
Technical field
The present invention relates to the design method of the physical layer in software communication architectural framework, particularly relates to software communication system frame
The design of hardware and software method of multinuclear heterogeneous processor in structure.
Background technology
According to the definition of SCA standard criterions, SCA equipment is divided into bottom physical equipment, device drives, operating system, core
Framework (CF), CORBA middlewares, waveform application etc..By CORBA middlewares and core frame, by waveform application correlation and bottom
Layer hardware device is separated, so as to realize the separation of software and hardware.However, CORBA middlewares can only be run in GPP, Wu Fayun
Row in DSP and FPGA, it is necessary to design the device drives MHAL unrelated with hardware to reach purpose communicate with mechanical floor so that
Certain difficulty is brought to design.Hardware abstraction layer software is by shielding the related low level communication mechanism of hardware platform, encapsulation
The communication interface of standard, the separation of communication mode and particular hardware platform between waveform components is realized, keep waveform components bottom to lead to
Believe the uniformity of access interface, the design of SCA hardware abstraction layers is related to tri- components of GPP, DSP and FPGA.Wherein, GPP
(General PurposeProcessor) represents that CORBA general processor, DSP (DigitalSignal can be run
Processor) represent that c program can be run but do not support CORBA processor, FPGA represents that HDL program can be run but do not support C
The processor of program and CORBA.
The hardware design of main flow or GPP+DSP+FPGA design method at present, this design method have it certain
Drawback：
1st, GPP, DSP and FPGA develop interlinking disunity, and system interface is inconsistent, and development language and hardware structure are not
Same, it is necessary to be developed accordingly to each functional module respectively, development difficulty is big, debugging cycle is grown, exploitation poor universality；
2nd, SCA standard criterions are by the shielding of isomery between CORBA Middleware implementation hardware, however, DSP and FPGA systems
Unite no unified interface, it is impossible to realized with GPP hardware interfaces it is general, so as to which DSP and FPGA can not run CORBA middlewares,
Therefore need to spend extra time and energy to develop corresponding hardware abstraction layer to shield bottom hardware equipment, realize physical equipment
Logically；
3rd, absolute separation of the waveform application in data processing can not be realized, application developer still needs to drive bottom hardware
Dynamic and data interaction related development.
The content of the invention
The goal of the invention of the present invention is to provide a kind of generalization hardware and software platform based on heterogeneous polynuclear framework, Ke Yiyun
Row CORBA middlewares, to solve the design challenges that existing CORBA middlewares can not run on DSP and FPGA, shorten software system
The construction cycle of system, carry out the indifference designed between software systems and distinguish.
The goal of the invention of the present invention is achieved through the following technical solutions：
A kind of generalization hardware and software platform based on heterogeneous polynuclear framework, include isomerization hardware platform, intermediate layer CORBA moulds
Block and application program module；
Isomerization hardware platform include the first hardware platform being made up of GPP, the second hardware platform being made up of ARM and DSP,
The 3rd hardware platform being made up of ARM and FPGA；
Application program module is separately operable in the first hardware platform, the second hardware platform and the 3rd hardware platform, is completed each
From wave data processing；
Intermediate layer CORBA modules are separately operable in the first hardware platform, the second hardware platform and the 3rd hardware platform, are formed
General hardware driving interface hands over logic of the Wave data between the first hardware platform, the second hardware platform and the 3rd hardware
Mutually.
According to features described above, on the second hardware platform, application program module is operated on DSP, intermediate layer CORBA modules
Operate on ARM, the inside for being transmitted Wave data between DSP and ARM with EDMA by internal memory mapping interacts, hard with first
Wave data interaction between part platform, the 3rd hardware platform is realized by ARM.
According to features described above, on the 3rd hardware platform, application program module is operated on FPGA, intermediate layer CORBA moulds
Block is operated on ARM, and ripple is realized in the DMA shared drives of FPGA and ARM AXI buses by carry between FPGA and ARM
The inside interaction of graphic data, the Wave data between the first hardware platform, the second hardware platform are interacted by ARM to realize.
Compared with prior art, the DSP in the present invention, FPGA components by the external interactive waveform data of ARM platforms, this
Sample, DSP and FPGA are uniformly packaged into unified GPP components.Whole platform is all general into a unified processing platform, passes through
Encapsulation to bottom hardware driving layer, calls unified high-level interface, completes the CORBA transmission of waveform application component.Meanwhile this
The software development of invention waveform and hardware developers can depart from the difference of platform, and the corresponding hardware driving of unified calling
Interface completes the transmission of Wave data.Furthermore the present invention can make waveform software designer more pay close attention to waveform application itself
Transmission, without paying close attention to the exploitation of waveform underlying device.Platform development need not pay close attention to the hardware details of waveform interface, and more close
Note raising and the platform maintenance of hardware platform efficiency.Therefore, the present invention not only maintains the exploitation week of equipment platform in time
Phase, more spatially optimize the exploitation problem of waveform software application.
Brief description of the drawings
Fig. 1 is the structural representation of the generalization hardware and software platform based on heterogeneous polynuclear framework.
Fig. 2 is the structural representation of the second hardware platform of DSP and ARM compositions.
Fig. 3 is the structural representation of the 3rd hardware platform of FPGA and ARM compositions.
Fig. 4 is the application schematic diagram of the generalization hardware and software platform based on heterogeneous polynuclear framework.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.
Referring to Fig. 1.According to software design idea, a kind of generalization hardware and software platform based on heterogeneous polynuclear framework, comprising
Isomerization hardware platform, intermediate layer CORBA modules and application program module；
Isomerization hardware platform include the first hardware platform being made up of GPP, the second hardware platform being made up of ARM and DSP,
The 3rd hardware platform being made up of ARM and FPGA；
Application program module is separately operable in the first hardware platform, the second hardware platform and the 3rd hardware platform, is completed each
From wave data processing；
Intermediate layer CORBA modules are separately operable in the first hardware platform, the second hardware platform and the 3rd hardware platform, are formed
General hardware driving interface hands over logic of the Wave data between the first hardware platform, the second hardware platform and the 3rd hardware
Mutually.
Referring to Fig. 2.Davinci architecture processors complete heterogeneous polynuclear architecture processor by the way that ARM and DSP is integrated
Design philosophy.Dsp operation application program module, the processing function of Wave data is mainly realized, and ARM runs intermediate layer
CORBA modules, realize the outside interaction of Wave data.Here DSP is primarily upon processing data, and ARM mainly completes waveform number
According to interaction, data enter row data communication by the way of shared drive between DSP and ARM, pass through internal memory mapping with EDMA pass
It is defeated, complete the interaction of data.Interacted with external data by ARM to realize, ARM completes the function of GPP PERCOM peripheral communication, by connecing
The shared Wave datas of DSP are received, are completed Wave data with external data communication function.
Referring to Fig. 3.Zynq architecture processors complete heterogeneous polynuclear architecture processor by the way that ARM and FPGA is integrated
Design philosophy.FPGA need to only pay close attention to its data processing function, interact with external data and mainly completed by ARM.FPGA and
Realized between ARM by carry in the DMA shared drives of FPGA and ARM AXI buses.ARM is packaged into GPP and realized and outside
The function of communication.
Referring to Fig. 4.By by DSP and ARM encapsulation, FPGA and ARM encapsulation, foring GPP+GPP (DSP)+GPP
(FPGA) level encapsulating structure.Generalization hardware and software platform based on heterogeneous polynuclear framework can be abstracted into physical transport layer,
Hardware abstraction layer, logical transport layer, 4 layers of application transport layer.Four layers of system has separate working environment, and interface division is clearly
It is clear, it can complete different wave, different components, different hardware environment, different operating system, steadily have between different physical transfers
The operation of effect.Further it can be realized by following steps：
S1, on physical transport layer, can be with complete by calling (i2c, RapidIO, CAN, network) to common bus etc.
Into the interaction of bottom Wave data.Interacted by the bottom of different application physical interface, complete the data interaction of whole system.
S2, it is the uniformity for realizing hardware details, by encapsulating different waveform physics data exchange channels, design is general
Hardware abstraction layer complete the uniformity of data interaction.Hardware abstraction layer is packed by the encapsulation of hardware driving, is unified into logical
Hardware driving interface, operating system and upper layer data passage are by calling the bottom hardware interface of hardware abstraction layer, you can
Carry out the communication of data.
S3, operating system mainly maintain the even running of each functional hierarchy of system, system is had unified resource
Scheduling.Operating system can make Vxworks, Linux, Windows etc..On operating system, to ensure the logical transport number of plies
According to stable transmission in invoked procedure, it is necessary to the support of SCA core frames (CF), SCA core frames CF run on operating system it
On.
S4, meet hardware abstraction layer design on the premise of, upper layer data interaction both can be by unified CORBA among
Part realizes the transparent transmission of data, and CORBA middlewares realize turning for data by bottom hardware level of abstraction software encapsulation interface
Hair.And the developer of upper waveform application software, it need to only pay close attention to the transparent features of CORBA data transfers, it is not necessary to pay close attention to number
According to the detail of transmission.By the application package interface for calling CORBA to provide, external data and transmission can be obtained in real time
Waveform application data caused by this application.
S5, application transport layer mainly complete the realization of the upper layer application of waveform components, and application transport layer is mainly run on
The framework control interface of Interface Controller and the application environment description of description environment configurations.Waveform application component is connect by framework control
Mouthful and application environment two control items of configuration file are described, can both complete waveform with the exploitation and later maintenance of component.
It is understood that for those of ordinary skills, can be with technique according to the invention scheme and its hair
Bright design is subject to equivalent substitution or change, and all these changes or replacement should all belong to the guarantor of appended claims of the invention
Protect scope.
Claims (3)
1. a kind of generalization hardware and software platform based on heterogeneous polynuclear framework, include isomerization hardware platform, intermediate layer CORBA modules
And application program module, it is characterised in that：
The isomerization hardware platform include the first hardware platform being made up of GPP, the second hardware platform being made up of ARM and DSP,
The 3rd hardware platform being made up of ARM and FPGA；
The application program module is separately operable in the first hardware platform, the second hardware platform and the 3rd hardware platform, is completed each
From wave data processing；
The intermediate layer CORBA modules are separately operable in the first hardware platform, the second hardware platform and the 3rd hardware platform, are formed
General hardware driving interface hands over logic of the Wave data between the first hardware platform, the second hardware platform and the 3rd hardware
Mutually.
2. a kind of generalization hardware and software platform based on heterogeneous polynuclear framework according to claim 1, it is characterised in that described
On second hardware platform, application program module is operated on DSP, and intermediate layer CORBA modules are operated on ARM, DSP and ARM it
Between mapped by internal memory and be transmitted with EDMA the inside of Wave data and interact, with the first hardware platform, the 3rd hardware platform it
Between Wave data interaction realized by ARM.
3. a kind of generalization hardware and software platform based on heterogeneous polynuclear framework according to claim 1, it is characterised in that described
On 3rd hardware platform, application program module is operated on FPGA, and intermediate layer CORBA modules are operated on ARM, FPGA and ARM
Between by carry realize that the inside of Wave data interacts in the DMA shared drives of FPGA and ARM AXI buses, with first
Wave data interaction between hardware platform, the second hardware platform is realized by ARM.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109412897A (en) * | 2018-11-15 | 2019-03-01 | 紫光测控有限公司 | System and method is realized based on the shared MAC of multi-core processor and FPGA |
| CN111159088A (en) * | 2019-11-29 | 2020-05-15 | 中国船舶重工集团公司第七0九研究所 | IIC bus communication method and system based on heterogeneous multi-core processor |
| CN112114969A (en) * | 2020-09-23 | 2020-12-22 | 北京百度网讯科技有限公司 | Data processing method and device, electronic equipment and storage medium |
| CN112506689A (en) * | 2020-12-10 | 2021-03-16 | 盛立金融软件开发（杭州）有限公司 | Heterogeneous counter system risk monitoring method, device, equipment and medium |
| CN113806106A (en) * | 2021-08-13 | 2021-12-17 | 中国航空无线电电子研究所 | Modem hardware abstraction layer facing VxWorks real-time process |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109412897A (en) * | 2018-11-15 | 2019-03-01 | 紫光测控有限公司 | System and method is realized based on the shared MAC of multi-core processor and FPGA |
| CN109412897B (en) * | 2018-11-15 | 2021-12-21 | 清能华控科技有限公司 | Shared MAC (media Access control) implementation system and method based on multi-core processor and FPGA (field programmable Gate array) |
| CN111159088A (en) * | 2019-11-29 | 2020-05-15 | 中国船舶重工集团公司第七0九研究所 | IIC bus communication method and system based on heterogeneous multi-core processor |
| CN112114969A (en) * | 2020-09-23 | 2020-12-22 | 北京百度网讯科技有限公司 | Data processing method and device, electronic equipment and storage medium |
| CN112506689A (en) * | 2020-12-10 | 2021-03-16 | 盛立金融软件开发（杭州）有限公司 | Heterogeneous counter system risk monitoring method, device, equipment and medium |
| CN112506689B (en) * | 2020-12-10 | 2023-08-11 | 盛立安元科技(杭州)股份有限公司 | Heterogeneous counter system risk monitoring method, device, equipment and medium |
| CN113806106A (en) * | 2021-08-13 | 2021-12-17 | 中国航空无线电电子研究所 | Modem hardware abstraction layer facing VxWorks real-time process |
| CN113806106B (en) * | 2021-08-13 | 2023-09-15 | 中国航空无线电电子研究所 | Communication system for VxWorks real-time process |
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