CN107613355B - Processing system for video and video processor - Google Patents
Processing system for video and video processor Download PDFInfo
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- CN107613355B CN107613355B CN201710868591.8A CN201710868591A CN107613355B CN 107613355 B CN107613355 B CN 107613355B CN 201710868591 A CN201710868591 A CN 201710868591A CN 107613355 B CN107613355 B CN 107613355B
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Abstract
The embodiment of the invention discloses a kind of processing system for video, including the first video processor and the second video processor, first video processor includes the first pluggable expanding unit and the first back board device, the first pluggable expanding unit is provided with the first connector and the first subtending port, which is provided with the first video input processing unit interface group, the first video output processing apparatus interface group, the first expanding unit interface, the first master control set interface and the first matrix switch module；Second video processor includes: the second pluggable expanding unit and the second back board device, the second pluggable expanding unit is provided with the second connector and the second subtending port, which is provided with the second video input processing unit interface group, the second video output processing apparatus interface group, the second expanding unit interface, the second master control set interface and the second matrix switch module；Wherein, the second subtending port connects the first subtending port by cable.
Description
Technical field
The present invention relates to video processing and field of display technology more particularly to a kind of processing system for video and a kind of video
Processor.
Background technique
Currently, common video processor can be by the video image of different type or format after scan picture
Become digital video signal to be exported with fixed format, and then the video is output in display device and shows.However, by existing
The limitation of the input/output channel quantity of video processor, single video processor is when handling more input/output signal sources
It has been increasingly difficult to meet demand.
Summary of the invention
The embodiment of the present invention provides a kind of processing system for video and a kind of video processor, to realize more multi input/defeated
The technical effect of access and the processing of signal source out.
On the one hand, a kind of processing system for video provided in an embodiment of the present invention, comprising:
First video processor, comprising:
First pluggable expanding unit, is provided with the first connector and the first subtending port；
First back board device is provided with the first video input processing unit interface group, the first video output processing apparatus connects
Mouth group, the first expanding unit interface, the first master control set interface and the first matrix switch module, wherein first matrix switch
Module connects the first video input processing unit interface group, the first video output processing apparatus interface group, described the
One expanding unit interface and the first master control set interface, the first video input processing unit interface group is for connecting view
Frequency input processing device, the first video output processing apparatus interface group is for connecting video output processing apparatus, and described the
One master control set interface connects first connector for connecting master control set, the first expanding unit interface；
Second video processor, comprising:
Second pluggable expanding unit, is provided with the second connector and the second subtending port；
Second back board device is provided with the second video input processing unit interface group, the second video output processing apparatus connects
Mouth group, the second expanding unit interface, the second master control set interface and the second matrix switch module, wherein second matrix switch
Module connects the second video input processing unit interface group, the second video output processing apparatus interface group, described the
Two expanding unit interfaces and the second master control set interface, the second video input processing unit interface group is for connecting view
Frequency input processing device, the second video output processing apparatus interface group is for connecting video output processing apparatus, and described the
Two master control set interfaces connect second connector for connecting master control set, the second expanding unit interface；
Wherein, second subtending port connects first subtending port by cable.
In one embodiment of the invention, data are formed between first connector and first subtending port
Access and control access are provided with relay repeater in the data path, and relay repeater connection described first connects
Plug-in unit and first subtending port.
In one embodiment of the invention, the relay repeater connects described the by serializer/deserializers bus
One connector and first subtending port.
In one embodiment of the invention, first back board device further include: first network physical layer transceiver group；
Second networked physics layer transceiver group；Third networked physics layer transceiver group；First programmable logic device, connection described first
Master control set interface connects the first video input processing unit interface by the first network physical layer transceiver group
Group connects the first video output processing apparatus interface group by the second networked physics layer transceiver group and passes through
The third networked physics layer transceiver group connects the first expanding unit interface.
In one embodiment of the invention, first programmable logic device further includes that the output of the first control sequential connects
Mouth group and the second control sequential output interface group, the first control sequential output interface group connect at first video input
Device interface group is managed, the second control sequential output interface group connects the first video output processing apparatus interface group.
In one embodiment of the invention, the first matrix switch module passes through multichannel serializer/deserializers bus
Connect the first expanding unit interface.
In one embodiment of the invention, first back board device further include: microcontroller circuit, including microcontroller
Device and the memory for connecting the microcontroller；Wherein, the microcontroller connects the first master control set interface, described the
One video input processing unit interface group and the first video output processing apparatus interface group.
In one embodiment of the invention, first programmable logic device connects institute by storage control bus
Master control set interface is stated, it is each in the first control sequential output interface group and the second control sequential output interface group
Road control sequential output interface is used to export comprising clock signal, data enable signal, line synchronising signal and field sync signal
Timing control signal；The first control sequential output interface group is believed for output multi-channel multisignal source premonitoring with timing control
Number, the second control sequential output interface group is used for the currently playing signal source timing control signal of output multi-channel.
In one embodiment of the invention, first back board device is additionally provided with the first genlock device and described
One synchronous phase locking unit connects the first expanding unit interface；Second backboard is additionally provided with the second genlock device and described
Second genlock device connects the second expanding unit interface.
On the other hand, a kind of video processor provided in an embodiment of the present invention, comprising:
Pluggable expanding unit, is provided with connector and subtending port；
Back board device is provided with video input processing unit interface group, video output processing apparatus interface group, expanding unit
Interface, master control set interface and matrix switch module, wherein the matrix switch module connects the video input processing unit
Interface group, the video output processing apparatus interface group, the expanding unit interface and the master control set interface, the video
Input processing device interface group is for connecting video input processing unit, and the video output processing apparatus interface group is for connecting
Video output processing apparatus, the master control set interface connect described in the expanding unit interface connection for connecting master control set
Plug-in unit；
Wherein, data path and control access are formed between the connector and the subtending port, the data are logical
Relay repeater is provided in road, and the relay repeater connects the connector and the subtending port.
In one embodiment of the invention, the back board device further include: first network physical layer transceiver group；Second
Networked physics layer transceiver group；Third networked physics layer transceiver group；Programmable logic device connects the master control set and connects
Mouth connects the video input processing unit interface group by the first network physical layer transceiver group, passes through described second
Networked physics layer transceiver group connects the video output processing apparatus interface group and is received by the third networked physics layer
It sends out device group and connects the expanding unit interface.
In one embodiment of the invention, the programmable logic device further includes the first control sequential output interface group
With the second control sequential output interface group, the first control sequential output interface group connects the video input processing unit and connects
Mouth group, the second control sequential output interface group connect the video output processing apparatus interface group；When the described first control
Being wrapped per control sequential output interface all the way for exporting in sequence output interface group and the second control sequential output interface group
Timing control signal containing clock signal, data enable signal, line synchronising signal and field sync signal；First control sequential
Output interface group is used for output multi-channel multisignal source premonitoring timing control signal, and the second control sequential output interface group is used
In the currently playing signal source timing control signal of output multi-channel.
In one embodiment of the invention, the back board device is additionally provided with genlock device and the genlock
Device connects the expanding unit interface.
Above-mentioned technical proposal can have following one or more advantages: by the way that pluggable expansion is arranged in video processor
Extending apparatus, makes can to cascade between multiple video processors and is constituted processing system for video with shared information, is directed to improve
Multi input/signal source output operating condition processing capacity；Furthermore device is forwarded as data, order using programmable logic device,
And by increasing the data physical channels such as networked physics layer transceiver group, it can achieve the purpose of simplified control logic and energy be real
Existing point-to-point communication, increases Data Transfer Parallelism, so as to promote properties of product.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill of field, without creative efforts, it can also be obtained according to these attached drawings others
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of processing system for video of the embodiment of the present invention；
Fig. 2 is a kind of structural schematic diagram of pluggable expanding unit of the embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of video processor of the embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of back board device of the embodiment of the present invention；
Fig. 5 is the communication mode schematic diagram of programmable logic device shown in Fig. 4；
Fig. 6 is a kind of structural schematic diagram of back board device of another embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1, processing system for video provided by one embodiment of the present invention includes two video processors, wherein one
A video processor 10 includes back board device 11, video input processing unit 13, video output processing apparatus 15 and pluggable
Expanding unit 16, another video processor 20 include back board device 21, video input processing unit 23, video output processing
Device 25 and pluggable expanding unit 26.Wherein, back board device 11 is for connecting video input processing unit 13, at video output
Manage device 15 and pluggable expanding unit 16；Back board device 21 is for connecting video input processing unit 23, video output processing
Device 25 and pluggable expanding unit 26.Video processor 10 passes through the pluggable expanding unit 16 and video processor of its own
20 pluggable expanding unit 26 is interconnected via cable (such as CXP cable etc.), to realize signal interaction, to improve needle
To multi input/signal source output operating condition access and processing capacity.
It should be noted that the tandem type video process apparatus in the present embodiment only gives two video processor cascades
The case where, it is possible to understand that there is the video processor of more than two similar structures to cascade constituted video process apparatus on ground
It should be within protection scope of the present invention.
Since video processor 10 is similar with the structure of video processor 20, for ease of description, hereinafter only
The structure of video processor 10 is described in detail.
Specifically, as shown in Fig. 2, pluggable expanding unit 16 includes connector 161 and subtending port 162.Subtending port
162 for the interconnection between multiple video processors, is, for example, CXP high-speed interface, and CXP is the abbreviation of CoaXPress,
It is a kind of point-to-point serial communication Digital Interface Standard of asymmetrical high speed.Connector 161 connect the back board device 11 with
Data path and control access are formed, is, for example, FCI high speed connector, and the data path is for example, by using serializer/unstring
Device bus realizes data transmission, while in order to guarantee completion of the data in high-speed transfer, preferably in data path in setting
Enhancing is forwarded to signal after forwarding chip 163.As for control access, then it is, for example, and is made of a plurality of signal wire.
Referring to Fig. 3, video processor 10 includes back board device 11, video input processing unit 13, video output processing dress
Set 15, pluggable expanding unit 16 and master control set 17.
Wherein, the specific structure of back board device 11 is as shown in figure 4, it is specifically included: video input processing unit interface group
111, video output processing apparatus interface group 113, master control set interface 115, expanding unit interface 116, matrix switch module
117, networked physics layer transceiver group 118a, networked physics layer transceiver group 118b, networked physics layer transceiver group 118c, can compile
Journey logical device 119 and genlock device 110.
Wherein, video input processing unit interface group 111 for example including multiple video input processing unit interfaces 1111 and
Card slot form can be used.
Video output processing apparatus interface group 113 is for example including multiple video output processing apparatus interfaces 1131 and can adopt
With card slot form.
Master control set interface 115 and expanding unit interface 116 can use card slot form.
116 connection matrix Switching Module 117 of expanding unit interface and programmable logic device 119.Specifically, extension dress
Interface 116 is set for example via multichannel SERDES bus connection matrix Switching Module 117 and for example by networked physics layer transceiver
Group 118c connection programmable logic device 119.Furthermore expanding unit interface 116 for connect pluggable expanding unit 16 with
Other video processors such as 20 form cascade, so that two video processors being connected can share signal source.
Matrix switch module 117 connects video input processing unit interface group 111, video output processing apparatus interface group
113 and master control set interface 115, for example including high speed matrix switch chip as CrossPoint Switch chip etc..
It is interconnected between genlock device such as 110,210 in multiple video processors, passes through genlock device 110,210
The synchronization signal of offer allows the output signal of multiple video processors to work in synchronous mode, avoids two and its output
The situation of the tearing of picture caused by signal is asynchronous.
Programmable logic device 119 connects master control set interface 115, by networked physics layer transceiver (or network
PHY it) organizes 118a connection video input processing unit interface group 111 and passes through networked physics layer transceiver group 118b connection video
Output processing apparatus interface group 113.In addition, programmable logic device 118 further includes control sequential output interface group 1191 and control
Sequential export interface group 1193 processed, control sequential output interface group 1191 connect video input processing unit interface group 111, control
Sequential export interface group 1193 connects video output processing apparatus interface group 113.
More specifically, including eight video input processing unit interfaces 1111 with video input processing unit interface group 111
And for video output processing apparatus interface group 113 includes eight video output processing apparatus interfaces 1131, then networked physics layer
Transceiver group 118a may include eight road network physical layer transceivers to be separately connected eight video input processing unit interfaces 1111,
Networked physics layer transceiver group 118b may include eight road network physical layer transceivers to be separately connected eight video output processing dresses
Set interface 1131；Similarly, control sequential output interface group 1191 may include eight tunnel control sequential output interfaces to be separately connected
Eight video input processing unit interfaces 1111, control sequential output interface group 1193 may include eight tunnel control sequential output interfaces
To be separately connected eight video output processing apparatus interfaces 1131.Certainly, it is worth mentioning at this point that, herein citing in interface quantity
It is not intended to limit the invention, it can elasticity design according to actual needs.Furthermore the programmable logic device of the present embodiment
119 be, for example, FPGA (Field Programmable Gate Array, field programmable gate array) device, certainly the present invention
It is not limited thereto.In addition, it is worth noting that, the programmable logic device 119 of the present embodiment is mainly used for realizing data, life
The forwarding of order, and by increasing the data physical channels such as networked physics layer transceiver group 118a, 118b, it can achieve simplified control
The purpose of logic processed is simultaneously able to achieve point-to-point communication, increases Data Transfer Parallelism.
Hold above-mentioned, video input processing unit 13 is connected to the video input in video input processing unit interface group 111
Processing unit interface 1111 (referring to fig. 4), video input processing unit 13 can also be referred to as defeated for example, by using board form
Enter card, correspondingly video input processing unit interface 1111 can be notch；As for being connected to video input processing unit
The quantity of the video input processing unit 13 of interface group 111 can be one, or multiple, particular number regards actual demand
Depending on.Furthermore video input, video pre-filtering or even video scaling, video preprocessor may be implemented in video input processing unit 13
The functions such as prison, OSD (on-screen display), UMD (Under Monitor Display).Video pre-filtering therein is
The operations such as gamma (Gamma) transformation, color gamut conversion (such as yuv format is converted into rgb format), filtering (such as median filtering).
In addition, each video input processing unit interface 1111 for example passes through multichannel SERDES bus connection matrix Switching Module 117.
Video output processing apparatus 15 is connected to the video output processing apparatus in video output processing apparatus interface group 113
Interface 1131 (referring to fig. 4), video output processing apparatus 15 can also be referred to as output card for example, by using board form, accordingly
Ground video output processing apparatus interface 1131 can be notch；As for being connected to video output processing apparatus interface group 113
Video output processing apparatus 15 quantity can be one, or multiple, particular number is depending on actual demand.Again
The functions such as image scaling, image superposition, video output may be implemented in person, video output processing apparatus 15.In addition, each video
Output processing apparatus interface 1131 for example passes through multichannel SERDES bus connection matrix Switching Module 117.
Master control set 17 is connected to the master control set interface 115 (referring to fig. 4) of back board device 11, can be used as host computer
Communication bridge between video processor 10, mainly realizes control function.Specifically, master control set 17 can pass through FMC
(Flexible Memory Controller can be changed storage control)/FSMC (Flexible Static Memory
Controller, variable static storage controller) etc. storage controls bus communicated with programmable logic device 119, and pass through
Programmable logic device 119 carries out data transmission with video input processing unit 13, video output processing apparatus 15.
Furthermore in the embodiment shown in fig. 3, video input processing unit 13, video output processing apparatus 15 and matrix are handed over
It changes the mold and is connected between block 117 using serializer/deserializers (SERDES) bus, to achieve the purpose that high speed data transfer.Matrix
Switching Module 117 uses high speed matrix switch chip, can be according to the switching command that master control set 17 issues by corresponding view
The data of frequency input processing device 13 are switched on corresponding video output processing apparatus 15.
Referring to Fig. 5, programmable logic device 119 stores mould for example including command analysis module, ID configuration module, data
The functional modules such as block, MVR/PGM sequence generation module.
After 10 system electrification of video processor, master control set 17 sends ID configuration order to programmable logic device first
119, ID configuration order is parsed by the command analysis module of programmable logic device 119, control ID configuration module generates n
A ID such as ID1 ... IDn, the value of n is usually by video input processing unit interface 1111 and video output processing apparatus herein
The total quantity of interface 1131 determines.N ID caused by ID configuration module is passed via network physical layer transceiver group 118a, 118b
It send to each video input processing unit 13 and video output processing apparatus 15, is exported by video input processing unit 13 and video
Processing unit 15 reads the ID received and saves into RAM.Then, at each video input processing unit 13 and video output
Reason device 15 generates responsion signal Ack 1 respectively ..., ACKn is to indicate to have been received ID and by networked physics layer transceiver
The data memory module that group 118a, 118b send programmable logic device 119 to save and is handled as each video input
The ID status information of device 13 and video output processing apparatus 15, and programmable logic device 119 can generate interrupt signal to master
Device 17 is controlled, the ID status information saved in data memory module is read by master control set 17.
As for MVR/PGM sequence generation module, MVR (Multi-Viewer) timing and PGM can produce
(Programming) timing.Wherein, MVR timing is for example including multichannel multisignal source premonitoring timing control signal, and per all the way
Multisignal source premonitoring is with timing control signal for example comprising clock signal (MCLK), data enable signal (DE), line synchronising signal
(HS) and field sync signal (VS) and via in control sequential output interface group 1191 the output interface of control sequential all the way and
The transceiver of networked physics layer all the way in networked physics layer transceiver group 118a is sent to corresponding video input processing unit
13, using as multisignal source premonitoring picture processing control sequential.Similarly, PGM timing is for example including the currently playing letter of multichannel
Number source (or PGM signal source, it typically is the currently playing signal sources shown for upper screen) output timing control signal, and
Per signal source output currently playing all the way with timing control signal for example comprising clock signal (PCLK), data enable signal
(DE), line synchronising signal (HS) and field sync signal (VS) and when via control all the way in control sequential output interface group 1193
The transceiver of networked physics layer all the way in sequence output interface and networked physics layer transceiver group 118b is sent to corresponding view
Frequency output processing apparatus 15, using as currently playing signal source output control sequential.
Referring to Fig. 6, in another embodiment of the present invention, back board device 31 includes: video input processing unit interface
Group 311, video output processing apparatus interface group 313, microcontroller circuit 314, master control set interface 315, expanding unit interface
316, matrix switch module 317, networked physics layer transceiver group 318a, networked physics layer transceiver group 318b, networked physics layer
Transceiver group 318c and programmable logic device 319 and genlock device 310.
Wherein, video input processing unit interface group 311 for example including multiple video input processing unit interfaces 1111 and
Card slot form can be used, is used to connect one or more video input processing units.
316 connection matrix Switching Module 317 of expanding unit interface and programmable logic device 319.Specifically, extension dress
Interface 316 is set for example via multichannel SERDES bus connection matrix Switching Module 317 and for example by networked physics layer transceiver
Group 318c connection programmable logic device 319.Furthermore expanding unit interface 316 is for connecting described in such as previous embodiment
Pluggable expanding unit is cascaded with being formed with other video processors, so that two video processors being connected can share letter
Number source.
Video output processing apparatus interface group 313 is for example including multiple video output processing apparatus interfaces 3131 and can adopt
With card slot form, it is used to connect one or more video output processing apparatus.
Microcontroller circuit 314 connects master control set interface 315, such as connects master control set interface by serial ports (UART)
315.Specifically, microcontroller circuit 314 may include memory of the microcontroller as MCU and connection microcontroller, and this
The memory at place for example connects microcontroller via universal serial bus.Furthermore microcontroller circuit 314 is connected by its microcontroller
Video input processing unit interface group 311 and video output processing apparatus interface group 313 are connect with acquiring video input processing unit
At the video output that the video input processing unit and video output processing apparatus interface group 313 that mouth group 311 is connected are connected
Manage the physical parameters such as the voltage signal of device；Memory such as flash memory by universal serial bus as spi bus and micro-controller communications,
Save the data record on microcontroller.
Master control set interface 315 can use card slot form, be used to connect master control set.And the master control set connected
It can be used as the communication bridge between host computer and video processor, mainly realize control function.
Matrix switch module 317 connects video input processing unit interface group 311, video output processing apparatus interface group
313 and master control set interface 315, for example including high speed matrix switch chip as CrossPoint Switch chip etc..This
Place, each of video input processing unit interface group 311 video input processing unit interface 3111 for example pass through multichannel
SERDES bus connection matrix Switching Module 317；Similarly, each of video output processing apparatus interface group 313 video
Output processing apparatus interface 3131 for example passes through multichannel SERDES bus connection matrix Switching Module 317.
Programmable logic device 319 for example by universal serial bus as spi bus connect master control set interface 315, pass through net
Network physical layer transceiver group 318a connection video input processing unit interface group 311 and pass through networked physics layer transceiver group
318b connection video output processing apparatus interface group 313.In addition, programmable logic device 318 further includes that control sequential output connects
Mouth group 3191 and control sequential output interface group 3193, control sequential output interface group 3191 connect video input processing unit and connect
Mouth group 311, control sequential output interface group 3193 connects video output processing apparatus interface group 313.
More specifically, including eight video input processing unit interfaces 3111 with video input processing unit interface group 311
And for video output processing apparatus interface group 313 includes eight video output processing apparatus interfaces 3131, then networked physics layer
Transceiver group 318a may include eight road network physical layer transceivers to be separately connected eight video input processing unit interfaces 3111,
Networked physics layer transceiver group 318b may include eight road network physical layer transceivers to be separately connected eight video output processing dresses
Set interface 3131；Similarly, control sequential output interface group 3191 may include eight tunnel control sequential output interfaces to be separately connected
Eight video input processing unit interfaces 3111, control sequential output interface group 3193 may include eight tunnel control sequential output interfaces
To be separately connected eight video output processing apparatus interfaces 3131.Certainly, it is worth mentioning at this point that, herein citing in interface quantity
It is not intended to limit the invention, it can elasticity design according to actual needs.Furthermore the programmable logic device of the present embodiment
319 be, for example, FPGA device, and the present invention is not limited thereto certainly.In addition, it is worth noting that, the programmable of the present embodiment is patrolled
Volume device 319 is mainly used for realizing the forwarding of data, order, and by increase by networked physics layer transceiver group 318a,
The data physical channels such as 318b can achieve the purpose of simplified control logic and realize point-to-point communication, increase data biography
Defeated concurrency.
Finally, it is noted that in other embodiments of the present invention, aforementioned programmable logic device can not also configure
Control sequential output interface group can equally reach the purpose of for example shared input source of more video processor shared informations.
In several embodiments provided herein, it should be understood that disclosed system, device and/or method, it can
To realize by another way.For example, the apparatus embodiments described above are merely exemplary, for example, unit is drawn
Point, only a kind of logical function partition, there may be another division manner in actual implementation, such as multichannel unit or component can
To combine or be desirably integrated into another system, or some features can be ignored or not executed.Another point, it is shown or beg for
The mutual coupling, direct-coupling or communication connection of opinion can be through some interfaces, the INDIRECT COUPLING of device or unit
Or communication connection, it can be electrical property, mechanical or other forms.
Unit may or may not be physically separated as illustrated by the separation member, shown as a unit
Component may or may not be physical unit, it can and it is in one place, or may be distributed over multi-channel network
On unit.It can some or all of the units may be selected to achieve the purpose of the solution of this embodiment according to the actual needs.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Previous embodiment describes the invention in detail, those skilled in the art should understand that: it still can be to aforementioned
Technical solution documented by each embodiment is modified or equivalent replacement of some of the technical features；And these are repaired
Change or replaces, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (11)
1. a kind of processing system for video characterized by comprising
First video processor, comprising:
First pluggable expanding unit, is provided with the first connector and the first subtending port；
First back board device, be provided with the first video input processing unit interface group, the first video output processing apparatus interface group,
First expanding unit interface, the first master control set interface and the first matrix switch module, wherein the first matrix switch module
Connect the first video input processing unit interface group, the first video output processing apparatus interface group, first expansion
Extending apparatus interface and the first master control set interface, the first video input processing unit interface group are defeated for connecting video
Enter processing unit, for the first video output processing apparatus interface group for connecting video output processing apparatus, described first is main
Control device interface connects first connector for connecting master control set, the first expanding unit interface；
Second video processor, comprising:
Second pluggable expanding unit, is provided with the second connector and the second subtending port；
Second back board device, be provided with the second video input processing unit interface group, the second video output processing apparatus interface group,
Second expanding unit interface, the second master control set interface and the second matrix switch module, wherein the second matrix switch module
Connect the second video input processing unit interface group, the second video output processing apparatus interface group, second expansion
Extending apparatus interface and the second master control set interface, the second video input processing unit interface group are defeated for connecting video
Enter processing unit, for the second video output processing apparatus interface group for connecting video output processing apparatus, described second is main
Control device interface connects second connector for connecting master control set, the second expanding unit interface；
Wherein, second subtending port connects first subtending port by cable,
Wherein, first back board device further include:
First network physical layer transceiver group；
Second networked physics layer transceiver group；
Third networked physics layer transceiver group；
First programmable logic device connects the first master control set interface, passes through the first network physical layer transceiver
Group connects the first video input processing unit interface group, by the second networked physics layer transceiver group connection described the
One video output processing apparatus interface group and pass through the third networked physics layer transceiver group connect it is described first extension dress
Set interface.
2. processing system for video as described in claim 1, which is characterized in that first connector and first order connection
It is formed with data path and control access between mouthful, relay repeater, and the relay forwarding are provided in the data path
Device connects first connector and first subtending port.
3. processing system for video as claimed in claim 2, which is characterized in that the relay repeater passes through serializer/unstring
Device bus connects first connector and first subtending port.
4. processing system for video as described in claim 1, which is characterized in that first programmable logic device further includes
One control sequential output interface group and the second control sequential output interface group, the first control sequential output interface group connect institute
The first video input processing unit interface group is stated, the second control sequential output interface group connects at the first video output
Manage device interface group.
5. processing system for video as described in claim 1, which is characterized in that the first matrix switch module passes through multichannel string
Change device/deserializer bus and connects the first expanding unit interface.
6. processing system for video as described in claim 1, which is characterized in that first back board device further include:
Microcontroller circuit, the memory including microcontroller and the connection microcontroller；
Wherein, the microcontroller connects the first master control set interface, the first video input processing unit interface group
With the first video output processing apparatus interface group.
7. processing system for video as claimed in claim 4, which is characterized in that first programmable logic device passes through storage
Controller bus connects the master control set interface, and the first control sequential output interface group and second control sequential are defeated
Include clock signal, data enable signal, the synchronous letter of row for output per control sequential output interface all the way in outgoing interface group
Number and field sync signal timing control signal；The first control sequential output interface group is pre- for output multi-channel multisignal source
Prison timing control signal, the second control sequential output interface group are used for the timing control of output multi-channel currently playing signal source
Signal processed.
8. processing system for video as described in claim 1, which is characterized in that it is same that first back board device is additionally provided with first
It walks phase locking unit and the first genlock device connects the first expanding unit interface；Second backboard is additionally provided with second
Genlock device and the second genlock device connection the second expanding unit interface.
9. a kind of video processor characterized by comprising
Pluggable expanding unit, is provided with connector and subtending port；
Back board device is provided with video input processing unit interface group, video output processing apparatus interface group, expanding unit and connects
Mouth, master control set interface and matrix switch module connect wherein the matrix switch module connects the video input processing unit
Mouth group, the video output processing apparatus interface group, the expanding unit interface and the master control set interface, the video are defeated
Enter processing unit interface group for connecting video input processing unit, the video output processing apparatus interface group is for connecting view
Frequency output processing apparatus, the master control set interface patch described in the expanding unit interface connection for connecting master control set
Part；
Wherein, data path and control access are formed between the connector and the subtending port, in the data path
It is provided with relay repeater, and the relay repeater connects the connector and the subtending port,
Wherein,
The back board device further include:
First network physical layer transceiver group；
Second networked physics layer transceiver group；
Third networked physics layer transceiver group；
Programmable logic device connects the master control set interface, connects institute by the first network physical layer transceiver group
It states video input processing unit interface group, the video output processing dress is connected by the second networked physics layer transceiver group
It sets interface group and the expanding unit interface is connected by the third networked physics layer transceiver group.
10. video processor as claimed in claim 9, which is characterized in that the programmable logic device further includes the first control
Sequential export interface group processed and the second control sequential output interface group, the first control sequential output interface group connect the view
Frequency input processing device interface group, the second control sequential output interface group connect the video output processing apparatus interface
Group；It is defeated per control sequential all the way in the first control sequential output interface group and the second control sequential output interface group
Outgoing interface is used to export the timing control signal comprising clock signal, data enable signal, line synchronising signal and field sync signal；
The first control sequential output interface group is used for output multi-channel multisignal source premonitoring timing control signal, second control
Sequential export interface group is used for the currently playing signal source timing control signal of output multi-channel.
11. the video processor as described in claim 9-10 any one, which is characterized in that the back board device is additionally provided with
Genlock device and the genlock device connection expanding unit interface.
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| CN112448974B (en) * | 2019-08-30 | 2023-10-17 | 北京嗨动视觉科技有限公司 | Network interaction method, device and system and image processing system |
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