CN107579108B - Method for forming semiconductor structure - Google Patents
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- CN107579108B CN107579108B CN201610516729.3A CN201610516729A CN107579108B CN 107579108 B CN107579108 B CN 107579108B CN 201610516729 A CN201610516729 A CN 201610516729A CN 107579108 B CN107579108 B CN 107579108B
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Abstract
The invention provides a method for forming a semiconductor structure, which comprises the following steps: forming a substrate comprising: a first region and a second region; forming an isolation structure in the substrate; forming a protective layer on the second region isolation structure; forming a doping layer on the surface of the first region substrate, wherein the doping layer is provided with doping ions; annealing the doped layer to enable doped ions in the doped layer to diffuse into the first region substrate; and removing the doped layer after the protective layer is formed and the annealing treatment is carried out. The protective layer can protect the second region isolation structure from being thinned in the process of removing the doped layer, so that the second region isolation structure can be ensured to have enough thickness, the leakage current of the semiconductor structure is reduced, and the structural performance of the semiconductor body is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
With the continuous progress of semiconductor technology, semiconductor devices are developed toward high integration and high quality, and the feature size of the semiconductor devices is correspondingly reduced.
The reduction in feature size of semiconductor devices, particularly the reduction in width of the gate structure, has led to a continuous reduction in the length of the channel beneath the gate structure. The reduction in channel length in a transistor increases the likelihood of charge punch-through between source and drain doped regions and tends to cause channel leakage currents. In order to reduce the channel leakage current, in the formation process of the semiconductor structure, the substrates on two sides of the gate structure are often doped, so that the substrate surface becomes amorphous, and a lightly doped region is formed, thereby reducing the channel leakage current.
In a semiconductor process, the lightly doped region generally needs to be formed in the fin portion through light doping implantation, however, the ion implantation is easy to make the top portion of the fin portion amorphous, which affects the performance of the semiconductor device. In order to reduce the influence of ion implantation on the fin part when the lightly doped region is formed, a solid source doping process is introduced into the forming method of the semiconductor structure. The solid source doping process is to form a doping layer on a semiconductor substrate, wherein the doping layer is provided with doping ions; diffusing the doping ions in the doping layer into the substrate to form a lightly doped region through an annealing process; and after the lightly doped region is formed, removing the doped layer.
However, the method for forming the semiconductor structure is easy to reduce the thickness of the isolation layer in the semiconductor structure, and affects the performance of the semiconductor structure.
Disclosure of Invention
The invention solves the problem of providing a method for forming a semiconductor structure, which can improve the performance of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: forming a substrate comprising: a first region and a second region; forming an isolation structure in the first region and the second region; forming a protective layer on the second region isolation structure; forming a doping layer on the surface of the first region substrate, wherein the doping layer is provided with doping ions; annealing the doped layer to enable doped ions in the doped layer to diffuse into the first region substrate; and removing the doped layer after the protective layer is formed and the annealing treatment is carried out.
Optionally, after forming the protection layer on the second region isolation structure, a doping layer is formed on the substrate surface of the first region.
Optionally, before forming the protective layer on the second region isolation structure, a doped layer is formed on the substrate surface of the first region.
Optionally, the substrate comprises: the semiconductor device includes a substrate and a fin located on the substrate.
Optionally, the step of forming the substrate comprises: providing an initial substrate; patterning the initial substrate to form a substrate and a fin part positioned on the substrate; the isolation structure is located on the substrate between the fin portions and covers partial side wall surfaces of the fin portions.
Optionally, the step of forming a protective layer on the second region isolation structure includes: forming an initial protective layer on the substrate and the isolation structure; and removing the initial protective layer on the first area substrate.
Optionally, before forming the protective layer, the method further includes: forming a grid structure on the first region substrate or the second region substrate; and in the step of removing the initial protective layer on the first region substrate, reserving the initial protective layer on the side wall of the first region grid structure to form a first side wall.
Optionally, the protective layer is made of silicon nitride or silicon oxynitride.
Optionally, the thickness of the protective layer is 10 angstroms to 40 angstroms.
Optionally, the process for forming the initial protection layer includes: a chemical vapor deposition process or an atomic layer vapor deposition process.
Optionally, the process of removing the initial protection layer on the substrate in the first region includes: and (5) anisotropic dry etching.
Optionally, after removing the doped layer, removing the protective layer is further included.
Optionally, the protective layer is made of photoresist, and the process for removing the protective layer includes an ashing process.
Optionally, the material of the protective layer is an organic anti-reflective coating, and the method for removing the protective layer includes: and removing the protective layer by flushing water in the photoetching process.
Optionally, the material of the doped layer is silicon oxide or silicon oxynitride; and the doping layer is doped with phosphorus ions or arsenic ions.
Optionally, the step of forming a doped layer on the substrate surface in the first region includes: forming an initial doping layer on the surface of the first region substrate and the second region substrate; and removing the initial doped layer on the second region substrate.
Optionally, the process of removing the initial doping layer on the second region substrate includes: dry etching or wet etching.
Optionally, the first region is used for forming an NMOS; the second region is used for forming PMOS; the doped ions are phosphorus or arsenic.
Optionally, after removing the doped layer, the method further includes: and carrying out light doping implantation on the second area substrate, wherein the implanted ions comprise boron ions or BF2 ions.
Optionally, after performing the light doping implantation on the second region substrate, the method further includes: and removing the protective layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming a semiconductor structure of the present invention, a protective layer is formed on the second region isolation structure before the doped layer is removed. The protective layer can protect the second region isolation structure from being thinned in the process of removing the doped layer, so that the second region isolation structure can be ensured to have enough thickness, the leakage current of the semiconductor structure is reduced, and the structural performance of the semiconductor body is improved.
Drawings
FIGS. 1-2 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 3 to 16 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The formation method of the semiconductor structure has many problems, such as: the forming method of the semiconductor structure is easy to reduce the thickness of the isolation structure in the semiconductor structure, and influences the performance of the semiconductor structure.
Now, in combination with a method for forming a semiconductor structure, the reason why the method for forming a semiconductor structure is apt to reduce the thickness of an isolation layer in the semiconductor structure is analyzed:
fig. 1 and 2 are schematic structural views of steps of a method of forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, the substrate includes a first region a and a second region B, and the substrate includes: a substrate 100; a fin 111 on the substrate 100.
With continued reference to fig. 1, isolation structures 101 are formed on the substrate between the fins 111.
With reference to fig. 1, a doped layer 112 is formed on the surface of the first I-fin portion 111, and the doped layer 112 has doped ions therein.
Continuing with fig. 1, annealing the doping layer 112 to diffuse the doping ions into the first I-fin portion 111 to form a lightly doped region.
Referring to fig. 2, after the annealing process, the doped layer 112 (shown in fig. 1) is removed.
In the process of removing the doped layer 112 by etching, the second region B isolation structure 101 is also easily etched, so that the second region B isolation structure 101 is thinned, and the isolation performance of the second region B isolation structure 101 is easily affected. Therefore, the method of forming the semiconductor structure easily affects the performance of the semiconductor structure.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming a substrate comprising: a first region and a second region; forming an isolation structure in the substrate; forming a protective layer on the second region isolation structure; forming a doping layer on the surface of the first region substrate, wherein the doping layer is provided with doping ions; annealing the doped layer to enable doped ions in the doped layer to diffuse into the first region substrate; and removing the doped layer after the protective layer is formed and the annealing treatment is carried out.
And forming a protective layer on the second region isolation structure before removing the doped layer. The protective layer can protect the second region isolation structure from being thinned in the process of removing the doped layer, so that the second region isolation structure can be ensured to have enough thickness, the leakage current of the semiconductor structure is reduced, and the structural performance of the semiconductor body is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 16 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
In the CMOS formation process, when the NMOS transistor is lightly doped, the dopant ions are arsenic. Arsenic has a large atomic weight and is likely to damage a substrate. Thus, for NMOS transistors, the substrate of the NMOS transistor is typically doped by a solid source doping process. In the process of removing the doping layer formed in the solid source doping process, the isolation structure is easy to etch, so that the thickness is reduced, and the electrical property of the semiconductor structure is easy to influence. Therefore, in this embodiment, the substrate of the NMOS transistor may be doped by a solid source doping process, for example, and the method for forming the semiconductor structure of the present invention is described in detail. In other embodiments, the substrate of the PMOS transistor may also be doped by a solid source doping process.
Referring to fig. 3, a substrate is formed, the substrate including: a first region I and a second region II.
In this embodiment, the substrate is used to form a finfet. In other embodiments, the substrate may also be used to form planar transistors.
In this embodiment, the first region I is used to form an NMOS transistor; the second region II is used to form a PMOS transistor.
In this embodiment, the step of forming the substrate includes: providing an initial substrate; the initial substrate is patterned to form a substrate 200 and a fin 211 on the substrate 200.
In this embodiment, the initial substrate is made of silicon. In other embodiments, the initial substrate may also be a semiconductor substrate such as a germanium substrate, a silicon-on-insulator or a germanium-on-insulator.
In this embodiment, the fin 211 is located on the surface of the substrate 200. In other embodiments, an oxide layer may be further disposed between the fin and the substrate.
Referring to fig. 4, an isolation structure 201 is formed in the substrate.
The isolation structure 201 is used to electrically isolate different semiconductor devices.
In this embodiment, the substrate includes: a substrate 200; a fin 211 on the substrate 200. The isolation structures 201 are located on the substrate 200 between the fins 211.
In this embodiment, the isolation structure 201 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon oxynitride.
As shown in fig. 5 and fig. 6, in the present embodiment, after the isolation structure 201 is formed, the forming method further includes: forming an isolation layer (not shown) on the surface of the fin 211; as shown in fig. 5, after forming the isolation layer, a first ion implantation is performed on the first I-fin portion 211 in the first region; as shown in fig. 6, a second ion implantation is performed on the second region II fin 211.
The isolation layer is used for protecting the first region I fin portion 211 from being damaged in the first ion implantation process, and protecting the second region II fin portion 211 from being damaged in the second ion implantation process.
The first ion implantation is used for adjusting the threshold voltage of the NMOS transistor; the second ion implantation is used for adjusting the threshold voltage of the PMOS transistor.
In this embodiment, the isolation layer is made of silicon oxide. In other embodiments, the material of the isolation layer may also be silicon nitride or silicon oxynitride.
In this embodiment, the implanted ions of the first ion implantation are boron ions; the implanted ions of the second ion implantation are phosphorus ions.
It should be noted that, as shown in fig. 7 and 8, fig. 8 is a side sectional view taken along line 1-1' of fig. 7. The forming method further includes: a gate structure 230 is formed across the fin 211, wherein the gate structure 230 covers a portion of the sidewalls and the top surface of the fin 211.
In this embodiment, the gate structure 230 includes: a gate dielectric layer (not shown) crossing the fin 211, the gate dielectric layer covering a portion of the sidewall and the top surface of the fin 211; the grid electrode is positioned on the surface of the grid dielectric layer; and the mask layer is positioned on the surface of the grid electrode.
In this embodiment, the gate dielectric layer is made of silicon oxide. In other embodiments, the material of the gate dielectric layer may also be silicon nitride or silicon oxynitride.
In this embodiment, the gate is made of polysilicon, and in other embodiments, the gate may also be a metal gate.
Referring to fig. 9, 10 and 11, fig. 11 is a side sectional view taken along line 2-2' of fig. 10, and a protection layer 222 is formed on the second region II isolation structure 201.
In this embodiment, the step of forming the protection layer 222 includes: forming an initial protection layer 202 on the substrate and the isolation structure 201; the initial protective layer 202 on the first area I substrate is removed to form the protective layer 222.
The step of forming the protection layer 222 is described in detail below with reference to the accompanying drawings.
Referring to fig. 9, an initial protection layer 202 is formed on the substrate and the isolation structure 201.
In this embodiment, the substrate 200 has a gate structure 230 on its surface. The initial protection layer 202 also covers the top and sidewall surfaces of the gate structure 230.
In this embodiment, the material of the initial protection layer 202 is different from the material of the isolation structure. The initial protection layer 202 and the isolation structure 201 are made of different materials, and the etching rates of the initial protection layer 202 and the isolation structure 201 are different, so that the loss of the isolation structure 201 is small in the process of removing the initial protection layer 202 in the first region I. In other embodiments, the material of the initial protection layer and the material of the isolation structure may also be the same.
In this embodiment, the initial protection layer 202 is made of silicon nitride. In other embodiments, the material of the protective layer may also be silicon oxynitride, germanium oxide, germanium oxynitride, or germanium nitride. In addition, the material of the initial protection layer can also be an anti-reflection coating or photoresist.
It should be noted that, if the thickness of the initial protection layer 202 is too small, it is difficult to protect the second region II isolation structure 201 in the subsequent process of removing the doped layer; if the thickness of the initial protection layer 202 is too large, the difficulty of subsequently etching the initial protection layer 202 is easily increased. Specifically, in this embodiment, the thickness of the initial protection layer 202 is 10 to 40 angstroms, for example, 20 angstroms.
In this embodiment, the initial protection layer 202 is formed by a chemical vapor deposition, atomic layer deposition, or physical vapor deposition process.
Referring to fig. 10 and 11, the initial passivation layer 202 on the first I region substrate is removed (as shown in fig. 9), so as to form the passivation layer 222.
The protection layer 222 is used for protecting the second region II isolation structure 201 from being etched in the subsequent process of removing the doped layer, so that the isolation performance of the second region II isolation structure 201 is improved, and the performance of the semiconductor structure is further improved.
In this embodiment, the material of the protection layer 222 is different from that of the isolation structure 201, so that the etching rate of the protection layer 222 is different from that of the isolation structure 201 in the process of etching the initial protection layer 202 on the first region I substrate. Therefore, the damage to the isolation structure 201 during etching is small. In other embodiments, the materials of the protective layer and the isolation structure may also be the same.
In this embodiment, the initial protection layer 202 on the first area I substrate is removed by anisotropic dry etching. The anisotropic dry etching has a smaller etching rate in the transverse direction than in the longitudinal direction, and has good profile control. In the etching process, the initial protection layer 202 on the sidewall surface of the first region I-gate structure 230 can be retained to form the sidewall spacers 212.
It should be noted that, in this embodiment, in order to simplify the process flow, the initial protection layer 202 is etched by anisotropic dry etching to form the sidewall spacers 212. In other embodiments, the sidewall spacers may also be formed before the initial protective layer is formed. The process of removing the initial protective layer on the first area substrate may further include: wet etching or isotropic dry etching.
In this embodiment, the initial protection layer 202 is made of silicon nitride. Correspondingly, the material of the protective layer is silicon nitride. In other embodiments, the material of the protection layer may also be silicon oxide, silicon oxynitride, germanium oxide, germanium oxynitride, or germanium nitride.
In this embodiment, the thickness of the protection layer 222 is the same as the thickness of the initial protection layer 202. Specifically, in this embodiment, the thickness of the protection layer 222 is 10 to 40 angstroms, for example, 20 angstroms.
Referring to fig. 12 and 13, a doped layer 213 is formed on the surface of the first region I substrate, and the doped layer 213 has doped ions therein.
In this embodiment, the step of forming the doped layer 213 includes: forming an initial doping layer 203 on the surface of the first region I substrate and the surface of the protection layer 222; the initially doped layer 203 on the surface of the protection layer 222 is removed.
In this embodiment, after the protective layer 222 is formed, the doping layer 213 is formed. The protection layer 222 may protect the second region II isolation structure 201 during the removal of the initial doping layer 203. In other embodiments, the doped layer may also be formed before the protective layer is formed.
The step of forming the doped layer 213 will be described in detail below with reference to the accompanying drawings.
Referring to fig. 12, an initial doping layer 203 is formed on the surface of the first region I substrate and the surface of the protection layer 222.
In this embodiment, the base includes a fin 211 on the substrate 200. The step of forming the initial doping layer 203 includes: an initial doping layer 203 is formed on the surface of the first region I fin 211.
In this embodiment, the initial doping layer 203 further covers the first I-isolation structure 201.
In this embodiment, the material of the initial doping layer 203 is silicon oxide. In other embodiments, the material of the initial doping layer may further include silicon nitride or silicon oxynitride.
It should be noted that, if the thickness of the initial doping layer 203 is too small, it is difficult to amorphize the fin portions 211 on both sides of the gate structure 211; if the thickness of the initial doped layer 203 is too large, difficulties may be easily caused in the subsequent etching process. Specifically, in this embodiment, the thickness of the initial doped layer 203 is 10 to 30 angstroms, for example, 20 angstroms.
In this embodiment, the first region I is used to form an NMOS transistor, and thus, the dopant ions are phosphorus or arsenic. In other embodiments, the first region may also be used to form a PMOS transistor, and the dopant ions may also be B or BH2。
In this embodiment, the initial doping layer 203 is formed by an atomic layer deposition process, and doping is performed during the deposition process. In other embodiments, the initially doped layer may also be formed by a chemical vapor deposition process or a physical vapor deposition process.
In this embodiment, the process parameters for forming the initial doping layer 203 by the atomic layer deposition process include: the reactants include: an organic precursor containing Si and PH3 gas; the gas flow is 10sccm and 5000 sccm;
in this embodiment, the concentration of the doping ions in the initial doping layer 203 is 1.0E20atoms/cm3～1.0E22atoms/cm3。
Referring to fig. 13, the initially doped layer 203 on the surface of the protection layer 222 is removed (as shown in fig. 12), and a doped layer 213 is formed.
In the process of removing the initial doping layer 203 on the surface of the protection layer 222, the protection layer 222 can protect the second region II isolation structure 201 from being etched, so that the influence of the etching process on the isolation performance of the second region II isolation structure 201 can be reduced.
In this embodiment, the initial doping layer 203 on the surface of the protection layer 222 is removed by dry etching, wet etching or a combination of dry etching and wet etching.
In this embodiment, the doping layer 213 is formed of the initially doped layer 203, and thus, the doping layer 213 and the initially doped layer 203 have the same material and thickness. Specifically, the material of the doping layer 213 is silicon oxide, and the doping ions are phosphorus or arsenic. The doped layer 213 has a thickness of 10 to 30 angstroms, for example, 20 angstroms.
Continuing with fig. 13, annealing the doped layer 213 to diffuse the doped ions in the doped layer 213 into the first I-substrate region, thereby forming a lightly doped region.
The lightly doped region is used for reducing the channel leakage current of the transistor and reducing the short channel effect.
In the process of annealing the doped layer 213, if the annealing temperature is too low, it is difficult to diffuse the doped ions in the doped layer 213 into the first I-substrate region, so that it is difficult to form a lightly doped region; if the annealing temperature is too high, the diffusion rate of the doping ions is easy to be too fast, and the thickness of the formed lightly doped region is difficult to control. Specifically, in this embodiment, the annealing temperature is 950 ℃ to 1050 ℃.
If the annealing time is too short, it is difficult to diffuse the dopant ions in the doped layer 213 into the first region I substrate, thereby making it difficult to reduce the short channel effect; if the annealing time is too long, the thickness of the formed lightly doped region is easily too large, which affects the electrical performance of the transistor.
Referring to fig. 14, after the protective layer 222 is formed and an annealing process is performed, the doped layer 213 is removed (as shown in fig. 13).
In the process of removing the doped layer 213, the protection layer 222 can protect the second region II isolation structure 201 from being etched, so that the influence of the etching process on the isolation performance of the second region II isolation structure 201 can be reduced.
In this embodiment, the process of removing the doped layer 213 may include: wet etching, dry etching or a combination of dry and wet etching.
In other embodiments, if the material of the protective layer is photoresist. The process for removing the protective layer comprises an ashing process; if the material of the protective layer is an organic anti-reflective coating, the protective layer can be removed by ashing or flushing in a photolithography process.
Referring to fig. 15, in the present embodiment, after removing the doping layer 213 (as shown in fig. 13), the forming method further includes: and carrying out light doping injection on the second area II substrate, and forming a second light doping area in the second area II substrate.
Specifically, in this embodiment, light doping implantation is performed on the second region II fin portion 211, and a second light doping region is formed in the second region II fin portion 211. The second region II is used to form a PMOS transistor, and in the process of performing light doping implantation on the second region II fin portion 211, the implanted ions are boron, the mass fraction of boron is small, and in the process of light doping implantation, the damage to the second region II fin portion 211 is small. In other embodiments, the second lightly doped region may also be formed by solid source doping.
The step of ion implantation of the second region II fin 211 includes: forming a photoresist 230 covering the surface of the first region I fin portion 211; performing ion implantation to form a second lightly doped region; the photoresist 230 is removed.
Referring to fig. 16, in the present embodiment, after performing the light doping implantation on the second region II fin 211, the forming method further includes: the protective layer 222 is removed (as shown in fig. 15).
In this embodiment, the protection layer 222 may be removed by dry etching, wet etching, or a combination of dry etching and wet etching.
In this embodiment, after the light doping implantation is performed on the second region II fin portion 211, the protection layer 222 is removed, and the protection layer 222 can protect the second region II fin portion 211 in the light doping implantation process, so as to reduce damage to the second region II fin portion 211. In other embodiments, the protective layer may be removed before performing the light doping implantation on the second region fin.
It is noted that the method for forming a semiconductor structure of the present invention provides another embodiment.
The same points as those in the previous embodiment are not described in detail herein, but the differences include forming a doped layer on the substrate surface in the first region before forming the protection layer on the second region isolation structure. The steps of forming the protection layer and the doping layer are the same as those in the previous embodiment, and are not described herein again. In summary, in the method for forming a semiconductor structure of the present invention, before removing the doping layer, a protection layer is formed on the second region isolation structure. The protective layer can protect the second region isolation structure from being thinned in the process of removing the doped layer, so that the second region isolation structure can be ensured to have enough thickness, the leakage current of the semiconductor structure is reduced, and the structural performance of the semiconductor body is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
forming a substrate comprising: a first region and a second region;
forming an isolation structure in the first region and the second region;
forming a protective layer on the second region isolation structure;
forming a doping layer on the surface of the first region substrate, wherein the doping layer is provided with doping ions;
annealing the doped layer to enable doped ions in the doped layer to diffuse into the first region substrate;
after the protective layer is formed and annealing treatment is carried out, the doped layer is removed;
and removing the protective layer after removing the doped layer.
2. The method of claim 1, wherein a doped layer is formed on the substrate surface of the first region after the protective layer is formed on the second region isolation structure.
3. The method of claim 1, wherein a doped layer is formed on the substrate surface of the first region before the protective layer is formed on the second region isolation structure.
4. The method of forming a semiconductor structure according to any of claims 1 to 3, wherein the substrate comprises: the semiconductor device includes a substrate and a fin located on the substrate.
5. The method of forming a semiconductor structure of claim 4, wherein the step of forming a substrate comprises: providing an initial substrate; patterning the initial substrate to form a substrate and a fin part positioned on the substrate;
the isolation structure is located on the substrate between the fin portions and covers partial side wall surfaces of the fin portions.
6. The method of forming a semiconductor structure according to any one of claims 1 to 3, wherein the step of forming a protective layer on the second area isolation structure comprises: forming an initial protective layer on the substrate and the isolation structure; and removing the initial protective layer on the first area substrate.
7. The method of forming a semiconductor structure of claim 6, further comprising, prior to forming the protective layer: forming a grid structure on the first region substrate and the second region substrate; and in the step of removing the initial protective layer on the first region substrate, reserving the initial protective layer on the side wall of the first region grid structure to form a first side wall.
8. The method of claim 7, wherein the protective layer is made of silicon nitride or silicon oxynitride.
9. The method of forming a semiconductor structure of claim 7, wherein the protective layer has a thickness of 10 to 40 angstroms.
10. The method of forming a semiconductor structure of claim 7, wherein the process of forming the initial protection layer comprises: a chemical vapor deposition process or an atomic layer vapor deposition process.
11. The method of claim 7, wherein the removing the initial protective layer on the first area substrate comprises: and (5) anisotropic dry etching.
12. The method of claim 1, wherein the protective layer is formed of a photoresist, and wherein the removing the protective layer comprises an ashing process.
13. The method of claim 1, wherein the protective layer is made of an organic anti-reflective coating, and the removing the protective layer comprises: and removing the protective layer by flushing water in the photoetching process.
14. The method of claim 1, wherein the material of the doped layer is silicon oxide or silicon oxynitride;
and the doping layer is doped with phosphorus ions or arsenic ions.
15. The method as claimed in any one of claims 1 to 3, wherein the step of forming the doped layer on the substrate surface in the first region comprises: forming an initial doping layer on the surface of the first region substrate and the second region substrate; and removing the initial doped layer on the second region substrate.
16. The method of claim 15, wherein the removing the initial doped layer on the second region substrate comprises: dry etching or wet etching.
17. The method of forming a semiconductor structure of claim 1, wherein the first region is used to form an NMOS; the second region is used for forming PMOS;
the doped ions are phosphorus or arsenic.
18. The method of forming a semiconductor structure of claim 17, further comprising, after removing the doped layer: performing light doping implantation on the second region substrate, wherein the implanted ions comprise boron ions or BF2Ions.
19. The method of claim 18, wherein the protective layer is removed after the second region substrate is lightly doped.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105280498A (en) * | 2014-07-22 | 2016-01-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN105336613A (en) * | 2014-06-30 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor structure |
| CN105489555A (en) * | 2014-09-19 | 2016-04-13 | 中国科学院微电子研究所 | Manufacturing method of semiconductor device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090057846A1 (en) * | 2007-08-30 | 2009-03-05 | Doyle Brian S | Method to fabricate adjacent silicon fins of differing heights |
| US8980719B2 (en) * | 2010-04-28 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for doping fin field-effect transistors |
| CN103855093B (en) * | 2012-11-30 | 2016-07-06 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
| US8895446B2 (en) * | 2013-02-18 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin deformation modulation |
| US8993417B2 (en) * | 2013-06-28 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET fin bending reduction |
| CN104465389B (en) * | 2013-09-25 | 2017-07-11 | 中国科学院微电子研究所 | The forming method of FinFet device source-drain areas |
| US9691900B2 (en) * | 2014-11-24 | 2017-06-27 | International Business Machines Corporation | Dual epitaxy CMOS processing using selective nitride formation for reduced gate pitch |
-
2016
- 2016-07-04 CN CN201610516729.3A patent/CN107579108B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336613A (en) * | 2014-06-30 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor structure |
| CN105280498A (en) * | 2014-07-22 | 2016-01-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN105489555A (en) * | 2014-09-19 | 2016-04-13 | 中国科学院微电子研究所 | Manufacturing method of semiconductor device |
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