CN107577418A - A kind of distributed memory system based on ARM frameworks - Google Patents
A kind of distributed memory system based on ARM frameworks Download PDFInfo
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Abstract
The present invention relates to a kind of distributed memory system based on ARM frameworks, includes ARM baseboard controllers, Ethernet switch, the CPU microservers based on ARM, multiple memory modules, system power supply module, system fan；In the distributed memory system, it greatly strengthen Fault Tolerance, power-on and power-off are carried out to hard disk by microprocessor, greatly reduce system operation and safeguard power consumption, therefore, the possibility using higher density of equipment is also increased, non-blocking network has been laid out by ethernet switch hub, the enterprise of different scales and business scenario are adapted to by flexible configuration mode.
Description
Technical field
The present invention relates to field of distributed storage, is a kind of distributed memory system based on ARM frameworks.
Background technology
With the high-tech network such as high speed, swift and violent development, Google, Amazon of cloud computing technology in the world
Enterprise also rapidly emerges, particularly the deep business cloud demand merged under background of internet and other industry, traditional
Enterprise is passively hovered in Constructing data center between two kinds of system storage architectures of conventional memory array and distributed storage.
The data storage scheme of industry is essentially all the centralised storage framework based on Intel x86 at present, and there is cpu fault shadow
Sound whole system, high power consumption, density of equipment are relatively low, the restricted shortcoming of network bandwidth.And the flouring of big data allows distribution to deposit
The storage method of storage framework obtained unprecedented concern in recent years.Therefore, can be on the basis of distributed storage architecture
On, storage system is improved, to adapt to demand for development now.
The content of the invention
In view of this, the present invention provides a kind of distribution based on ARM frameworks for solving or partly solving the above problems and deposited
Storage system.
To reach the effect of above-mentioned technical proposal, the technical scheme is that：A kind of distribution based on ARM frameworks is deposited
Storage system, include herein below：
Distributed memory system includes ARM baseboard controllers, Ethernet switch, the CPU microservers based on ARM, more
Individual memory module, system power supply module, system fan；
Multiple memory modules be expressed as memory module 1, memory module 2 ..., memory module n, wherein, n is more than 1 just
Integer；
Memory module includes storage medium, cache module, storage control, command register, Clock management module, its
In, storage medium is the mechanical hard disks of 3.5 cun of SATA or solid state hard disc, to realize the physical store of data, memory module
The course of work includes the read operation of memory module, the write operation of memory module, the data record process of memory module；
In a storage module, the multistage-mapping of memory space is established, multistage-mapping is divided into three-level, and the first order controls for storage
Mapping relations between device and command register, storage control are responsible for the specific control to memory module, concurrently provide gymnastics
Instruct and include write operation instruction, read operation instruction, data record instruction to command register, concrete operations instruction, instructing
In register, three instruction memory sizes are opened, represent the storage of the Three Estate of concrete operations instruction, concrete operations refer to
Order is divided into grade one, grade two, grade three, and instruction memory size takes first in first out, the specific behaviour being issued at first
Instruct and enter instruction memory size at first and rank, when current time has only ejected one from three instruction memory sizes
Individual concrete operations instruction, then concrete operations instruction is first carried out, if current time ejects from three instruction memory sizes
More than one concrete operations instruction, the grade that storage control instructs to more than one concrete operations judges, first carry out
The high concrete operations instruction of grade, Clock management module are responsible for sending the clock signal of fixed frequency, are responsible for distributed storage system
The clock of system is synchronous, and when performing the high concrete operations instruction of grade, the concrete operations instruction of other ejections is delayed, Clock management
Clock signal delay, the i.e. time of distributed memory system are suspended by module, when the high concrete operations instruction of grade is commanded
Finish, other ejection concrete operations instruction by grade sequence perform, be carried out finishing, Clock management module followed by
Supervention goes out the clock signal of fixed frequency, i.e. the time of distributed memory system continues to calculate；
Mapping relations of the second level between command register and cache module, being ejected in command register needs to perform
Concrete operations instruction, in cache module store three instruction memory sizes in concrete operations instruction in by operation data
Physical address, physical address be in storage medium by the actual storage address of operation data, and in cache module, specific behaviour
That is, in cache module, cached in the presence of address relationship in logic by the storage of the physical address of operation data in instructing
Be stored as in module in logical address, concrete operations instruction, concrete operations instruction by the physical address of operation data, storage it is suitable
Sequence is the order of the time for the clock signal that Clock management module is sent, while the concrete operations instruction ejected is by the height of grade
Arrangement；When distributed memory system is powered on, start distributed memory system operation, even if unexpected power down, due to caching
Space is stored, and is actually backed up, and when distributed memory system is upper electric again, is called from spatial cache；
Mapping relations of the third level between cache module and storage medium, reflecting between physical address and logical address
Relation is penetrated, to realize the execution for performing concrete operations instruction, physical address is stored as a physical address table, and logical address represents
For a logical address table, the mapping between physical address table and logical address table is represented with triple, first of triple
Element is expression symbol of the physical address on physical address table, and the 3rd element of triple is logical address in logical address
Expression symbol on table, second element of triple are the operation of concrete operations instruction, are divided into three kinds, read operation, write operation,
Data record, expression symbol, logical address expression symbol on logical address table of the physical address on physical address table is all
It is expressed as BNF form；
Logical address table is expressed as a binary array with physical address table, and logical address table is expressed asPhysical address table is expressed asThe number of content in both is identical, to three
Carry out being converted to n by the number x of the physical address of operation data in concrete operations instruction in individual instruction memory size2, n is to patrol
Collect the stratum of address table and physical address table, x≤n2, n2For square of the minimum integer more than x, read operation, write operation, number
Read, write, recovery are expressed as according to recovery；
Expression symbol of the logical address on logical address tableK, m is positive integer；
Expression symbol of the physical address on physical address table is expressed asI, j is for just
Integer；
The process of the read operation of memory module is：
Storage control simultaneously sends concrete operations and instructed to command register, the concrete operations instruction of command register ejection
Instructed for read operation, the operation that the CPU microservers based on ARM are carried out is as follows：Concrete operations instruction is read, is adjusted from cache module
Address relationship logically is taken, as by the physics of operation data in logical address, concrete operations instruction, concrete operations instruction
Address, logical address are the storage address on cache module, according to the mapping relations between physical address and logical address, are obtained
It by the physical address of operation data in being instructed to concrete operations, will be recalled from storage medium by operation data, and calculate specific behaviour
By the length of operation data in instructing, cutting is carried out by the length of operation data in being instructed to concrete operations, cutting is 8 words
One group is saved, and number of the read signal for group is set, it is 8 bytes to read length every time, has read and has subtracted one by read signal, and has started
CPU microservers based on ARM carry out data transmission, and ARM baseboard controllers will control Ethernet switch to go out data transfer
Go, when read signal is 0, end of transmission；
The process of the write operation of memory module is：
Storage control simultaneously sends concrete operations and instructed to command register, the concrete operations instruction of command register ejection
Instructed for write operation, the operation that the CPU microservers based on ARM are carried out is as follows：
Concrete operations instruction is read, address relationship logically, as logical address, specific behaviour are transferred from cache module
Instruct, in concrete operations instruction by the physical address of operation data, now, by the physics of operation data in concrete operations instruction
Address is sky, comprising the data for needing to write in write operation instruction, carries out cutting to the data that needs write, cutting is 8 words
Save as one group, and number of the write signal for group is set, it is 8 bytes to write take length every time, writes and subtracts one by write signal, and starts
CPU microservers based on ARM carry out data transmission, and ARM baseboard controllers will control Ethernet switch to be read from outside and need
The data to be write, when read signal is 0, end of transmission；
Idle physical block in storage control distribution storage medium, looks for the minimum idle physics of physical address
Block, the mapping relations between physical address and logical address are changed, change the mapping relations between physical address and logical address,
Logical address is set to be mapped as the physical address of the minimum idle physical block of physical address of distribution, 8 bytes are one group toward thing
The minimum idle physical block write-in data in reason address, the idle of current physical address minimum is redistributed when writing during failure
Physical block, again repeatedly said process；
The data record process of memory module is：Scanning is timed to the bad block in storage medium, by bad block from storage
Removed in idle physical block in medium,
Reclaim logic and the physical block containing non-useful information is reclaimed or shifted static information.The logic mainly realizes three work(
Can, one is to wipe the block containing non-useful information and recorded after being erased in free block message queue, second, transfer is static
Information, third, if encountering erasing failure, then will start bad block in erase process and exclude logic, bad block is not recorded in into free block
Message queue in, avoid writing information into bad block in write-in, and cause information to be lost.When storage system is not received by reading
During write order, block recovery logic working, after block recovery logic starts, the physical address according to pointed by block reclaims pointer starts
The containing dirty pages information of the block is scanned, is reclaimed if meeting that recovery requires, pointer is otherwise reclaimed and presses memory space physically
Location loopy moving, until completing block reclaimer operation this time.
ARM baseboard controllers are the key control units of whole system, and whole distributed storage is controlled by system bus
System, realize to the CPU microservers based on ARM and the upper and lower electricity of storage medium, reset management, detection, IP match somebody with somebody in place
Put, and control the power-on and power-off, startup self-detection, Ethernet switch of whole distributed memory system to control, system power supply module
Management, the control of fan；
CPU microservers based on ARM, it is connected by connector with multiple storage mediums, becomes distribution and deposit
Intelligent storage node in storage system, and receive the instruction from ARM baseboard controllers, realize to storage medium it is upper electricity, under
Electricity, data transfer and other management；
Ethernet switch is responsible for being connected with external switch, realizes the data exchanging function on network；
System power supply module is responsible for whole distributed memory system and provides the energy；
System fan provides cooling source for whole distributed memory system.
The present invention useful achievement be：The invention provides a kind of distributed memory system based on ARM frameworks, in this point
In cloth storage system, Fault Tolerance is greatly strengthen, power-on and power-off are carried out to hard disk by microprocessor, greatly reduced
System operation safeguards power consumption, therefore, also increases the possibility using higher density of equipment, is laid out by ethernet switch hub
Non-blocking network, is adapted to the enterprise of different scales and business scenario, especially, to it by flexible configuration mode
In the memory module that is related to further refine, the function that the process being related to and process be related to will be stored and be distributed to each submodule
Block, with the process of standard operation, the composition of the storage medium in memory module can modify according to different application scenarios,
To tackle different memory requirements.
Brief description of the drawings
Fig. 1 is the structural representation of the distributed memory system provided by the invention based on ARM frameworks.
Embodiment
In order that technical problems, technical solutions and advantages to be solved are more clearly understood, tie below
Embodiment and accompanying drawing are closed, the present invention will be described in detail.It should be noted that specific embodiment described herein is only used
To explain the present invention, it is not intended to limit the present invention, can realizes that the product of said function belongs to equivalent substitution and improvement, include
Within protection scope of the present invention.Specific method is as follows：
Embodiment 1：By establishing recovery standard during the data record of memory module, can be deposited in storage medium by page
Store up, wiped by block, containing dirty pages are handled, containing dirty pages are the page containing invalid information in block, and the information of some pages is in some pieces
Effectively, and in long-time do not changed, will so cause the erasable number of these blocks to be far below other pieces, and cause to be lost
It is unbalanced, while be also possible to because page a small number of in some pieces causes monoblock memory space to be released for effective information page
Put, so as to cause available block to reduce, available memory space is reduced.Free memory is reclaimed and tried one's best in time to realize
Reduce the erasable number of memory space, it is necessary to which needs how many page in i.e. one piece that lays down a criterion is that invalid information then needs
Containing dirty pages collection is carried out, i.e., is shifted effective information page, then wipe the block.
Temporally mark transfer static information, static information be exactly those be not updated in a very long time it is effective
Information, and some physical blocks are taken for a long time, and cause the erasing times of these physical blocks significantly lower than other physical blocks
Erasing times, so that the loss of whole memory is uneven.When the number used of memory space uses in the present invention
Between labelling method, when the physical address for being written into block is the maximum physical address of free space, current time adds one, and will be current
Time is recorded in the memory space that a fixed logical address is pointed to.Current time is write on to the reservation of every page during write operation
Area, the time for the page write in same a period of time is all identical, and the time of the page containing static information is far below currently
Time.Show that time and the current time record when some pieces are in a ratio of the letter of ten times or more than the ten times then blocks by practice
Cease for static information, it is necessary to shift.
To shorten retrieval time, the following storage organization of bad block is devised：By high 10 benefits of bad block reason address (13)
07, the index address as bad block；Under low 3 index bits as 8 in the address bad block message data, the i.e. index
The index data position of bad block be " 1 ".For example, in block physical address " 10D0h "-" 10D7h " (13bits), address is
The block of " 10D5h " is bad block, and binary system is " 1000011010101b ".Preceding 10 zero paddings 7 are
The index address writing address of " 00000001000011010b " as bad block." 5 " in 3 " 101b " mark " 0-7 " positions afterwards
This position is " 1 ", i.e., 8 bad block messages that the address is write in the index address of bad block are " 00100000b ".
The present invention devises two kinds of important application scenarios, respectively towards enterprise data center example approach with towards
The example approach of in general enterprise level, to tackle the different needs of enterprise.
In the example approach towards enterprise data center, the storage medium in memory module is by 96 3.5 cun of HDD machineries
Hard disk or SSD solid state hard discs, either using 80 3.5 cun of HDD mechanical hard disks or SSD solid state hard discs or using 64 3.5 cun
HDD mechanical hard disks or SSD solid state hard discs, the number of different storage mediums is taken to depend on the data that data storage needs to store
Size, the present embodiment has the characteristics of high density, low-power consumption, to be adapted to Enterprise Data center mass data storage
It is required that.
In the example approach towards in general enterprise level, the storage medium in memory module is by 12 3.5 cun of HDD machines
Tool hard disk or SSD solid state hard discs composition storage medium, the cost performance of the present embodiment is high, to adapt in general enterprise level
The demand of data storage.
In above two example approach, Intel X86 modules can be increased as needed to realize computing function,
Intel X86 modules are frequently utilized for centralised storage framework, and centralised storage is usually mixed with distributed storage in practical application
Close and use, with reference to the advantages of both.In addition, the memory module of the present invention includes storage medium, cache module, storage control
Device, command register, Clock management module, while being changed again to the number of storage medium in this example approach, also may be used
With supporting increase cache module, storage control, command register, Clock management module, carried out with the operation to storage medium
Specification, improve the efficiency of storage.Therefore, the present invention has very strong autgmentability, can be neatly real using the solution of the present invention
The storage of existing different scenes, increased functional module is belonged within protection scope of the present invention on the basis of the present invention.
Embodiment 2：A kind of distributed memory system based on ARM frameworks provided by the invention, is comprised the steps of：
Distributed memory system includes ARM baseboard controllers, Ethernet switch, the CPU microservers based on ARM, more
Individual memory module, system power supply module, system fan；Multiple memory modules be identified as memory module 1, memory module 2 ...,
Memory module n, wherein, n is the positive integer more than 1；Memory module includes storage medium, cache module, storage control, instruction
Register, Clock management module, wherein, storage medium is the mechanical hard disks of 3.5 cun of SATA or solid state hard disc, to realize data
Physical store, the course of work of memory module includes the read operation of memory module, the write operation of memory module, memory module
Data record process；
In a storage module, the multistage-mapping of memory space is established, multistage-mapping is divided into three-level, and the first order controls for storage
Mapping relations between device and command register, mapping relations of the second level between command register and cache module, when point
When cloth storage system is powered on, start distributed memory system operation, even if unexpected power down, due to being carried out in spatial cache
Storage, is actually backed up, and when distributed memory system is upper electric again, is called from spatial cache；The third level is slow
Mapping relations between storing module and storage medium, the mapping relations between physical address and logical address, performed with realizing
The execution of concrete operations instruction, physical address are stored as a physical address table, and logical address is expressed as a logical address table；
Logical address table is expressed as a binary array with physical address table, and logical address table is expressed asPhysical address table is expressed asThe number of content in both is identical, right
Carry out being converted to n by the number x of the physical address of operation data in concrete operations instruction in three instruction memory sizes2, n is
The stratum of logical address table and physical address table, x≤n2, n2For square of the minimum integer more than x, read operation, write operation,
Data record is expressed as read, write, recovery；
Expression symbol BNF form of the logical address on logical address table beK, m is
Positive integer；Expression symbol of the physical address on physical address table is expressed asI, j is to be just whole
Number；
The data record process of memory module is：Scanning is timed to the bad block in storage medium, by bad block from storage
Removed in idle physical block in medium, the physical block containing non-useful information is reclaimed or shifted static information by recovery logic.
The logic mainly realizes three functions, and one is by the block erasing containing non-useful information and after being erased in free block message queue
Middle record, second, transfer static information, third, if encountering erasing failure, then will start bad block in erase process and exclude logic,
Bad block is not recorded in the message queue of free block, avoids writing information into bad block in write-in, and cause information to be lost.When
When storage system is not received by read write command, block recovery logic working, after block recovery logic starts, pointer is reclaimed according to block
Pointed physical address starts to scan the containing dirty pages information of the block, is reclaimed if meeting that recovery requires, otherwise recovery refers to
Pin presses the physical address loopy moving of memory space, until completing block reclaimer operation this time.
ARM baseboard controllers are the key control units of whole system, and whole distributed storage is controlled by system bus
System, realize to the CPU microservers based on ARM and the upper and lower electricity of storage medium, reset management, detection, IP match somebody with somebody in place
Put, and control the power-on and power-off, startup self-detection, Ethernet switch of whole distributed memory system to control, system power supply module
Management, the control of fan；
CPU microservers based on ARM, it is connected by connector with multiple storage mediums, becomes distribution and deposit
Intelligent storage node in storage system, and receive the instruction from ARM baseboard controllers, realize to storage medium it is upper electricity, under
Electricity, data transfer and other management；
Ethernet switch is responsible for being connected with external switch, realizes the data exchanging function on network；System electricity
Source module is responsible for whole distributed memory system and provides the energy；System fan provides cold for the whole distributed memory system
But source；
In general, conventional fan tests the speed transposition without code-disc, simply simple if not detecting the rotating speed of fan electromotor
Change pulse width modulated duty cycle, carry out opened loop control.The rotating speed control of so fan system is easily done by the external world
Disturb, such as the fluctuation of supply voltage, the change of motor load etc., cause rotating speed control inaccurate.Fan electromotor is turned in order to realize
The accurate control of speed forms speed closed loop negative-feedback, motor is realized by pid control algorithm, it is necessary to detects motor speed in real time
The high precision closed loop control of rotating speed.Therefore, from the 12V DC motor (ASLONG RF371) for coming with the code-disc that tests the speed, in electricity
Machine installs flabellum to form the DC fan of system.The motor often rotates a circle exportable 334 rectangular pulses, by pulse
Count the real-time detection that can be achieved to motor speed.
The present invention useful achievement be：The invention provides a kind of distributed memory system based on ARM frameworks, in this point
In cloth storage system, Fault Tolerance is greatly strengthen, power-on and power-off are carried out to hard disk by microprocessor, greatly reduced
System operation safeguards power consumption, therefore, also increases the possibility using higher density of equipment, is laid out by ethernet switch hub
Non-blocking network, is adapted to the enterprise of different scales and business scenario, especially, to it by flexible configuration mode
In the memory module that is related to further refine, the function that the process being related to and process be related to will be stored and be distributed to each submodule
Block, with the process of standard operation, the composition of the storage medium in memory module can modify according to different application scenarios,
To tackle different memory requirements.
The preferred embodiments of the invention is the foregoing is only, is not limited to the claims of the present invention.
It is simultaneously described above, for those skilled in the technology concerned it would be appreciated that and implement, therefore other are based on institute of the present invention
The equivalent change that disclosure is completed, should be included in the covering scope of the claims.
Claims (1)
1. a kind of distributed memory system based on ARM frameworks, it is characterised in that include herein below：
The distributed memory system includes ARM baseboard controllers, Ethernet switch, the CPU microservers based on ARM, more
Individual memory module, system power supply module, system fan；
The multiple memory module be expressed as memory module 1, memory module 2 ..., memory module n, wherein, n is more than 1 just
Integer；
The memory module includes storage medium, cache module, storage control, command register, Clock management module, its
In, the storage medium is the mechanical hard disks of 3.5 cun of SATA or solid state hard disc, described to deposit to realize the physical store of data
The course of work for storing up module includes the read operation of the memory module, the write operation of the memory module, the memory module
Data record process；
In the memory module, the multistage-mapping of memory space is established, the multistage-mapping is divided into three-level, the respectively first order
Mapping, second level mapping, third level mapping；The first order is mapped as reflecting between the storage control and the command register
Relation is penetrated, the storage control is responsible for the specific control to the memory module, and sends concrete operations and instruct to the finger
Register is made, the concrete operations instruction includes write operation instruction, read operation instruction, data record instruction, posted in the instruction
In storage, three instruction memory sizes are opened, represent the storage of the Three Estate of the concrete operations instruction, it is described specific
Operational order is divided into grade one, grade two, grade three, and the instruction memory size takes first in first out, is sent out at first
The concrete operations instruction gone out enters the instruction memory size and ranked at first, and empty from the instruction storage at first
Between in be ejected, when current time has only ejected concrete operations instruction from three instruction memory sizes, then first
One concrete operations instruction is performed, if current time has ejected more than one tool from three instruction memory sizes
Body operational order, the storage control is judged the grade of the more than one concrete operations instruction, first carries out grade
High concrete operations instruction, the Clock management module are responsible for sending the clock signal of fixed frequency, are responsible for the distribution and deposit
The clock of storage system is synchronous, and when performing the high concrete operations instruction of the grade, the concrete operations instruction of other ejections is delayed,
The Clock management module is by the clock signal delay, i.e., the time of described distributed memory system is suspended, when described etc.
The high concrete operations instruction of level, which is commanded, to be finished, and the concrete operations instruction of other ejections is performed by the sequence of grade, is all held
Row finishes, and the Clock management module is further continued for sending the clock signal of fixed frequency, i.e., described distributed memory system
Time is further continued for being calculated；
The second level is mapped as the mapping relations between the command register and the cache module, quilt in the command register
Ejection needs the concrete operations instruction performed, and the tool in three instruction memory sizes is stored in the cache module
By the physical address of operation data in body operational order, the physical address is by the reality of operation data in the storage medium
Border storage address, and in the cache module, deposited in the concrete operations instruction by the storage of the physical address of operation data
Address relationship logically, i.e., in the cache module, the address relationship is stored as logical address, the specific behaviour
Instruct, sent out in concrete operations instruction by the physical address of operation data, the order of storage for the Clock management module
The sequencing of the time of the clock signal gone out, while the concrete operations instruction ejected is arranged by the height of its grade, and
Stored；
The third level is mapped as the mapping relations between the cache module and the storage medium, be the physical address with it is described
Mapping relations between logical address, to realize the execution of the concrete operations instruction, the physical address, which collects, is expressed as one
Individual physical address table, the logical address, which collects, is expressed as a logical address table, the physical address table with it is described logically
Mapping between the table of location represents with triple, and first element of the triple is the physical address in the physical address
Expression symbol on table, the 3rd element of the triple is expression symbol of the logical address on the logical address table
Number, second element of the triple is the operation of concrete operations instruction, is divided into three kinds, be read operation, write operation,
Data record, expression symbol of the physical address on the physical address table, the logical address are in the logical address
Expression symbol on table is expressed as BNF form；
The process of the read operation of the memory module is：
The storage control simultaneously sends concrete operations and instructed to the command register, the command register ejection it is described
Concrete operations instruction instructs for read operation, and the operation that the CPU microservers based on ARM are carried out is as follows：Read described specific
Operational order, the address relationship logically, as described logical address, the specific behaviour are transferred from the cache module
Instruct, in concrete operations instruction by the physical address of operation data, the logical address is on the cache module
Storage address, according to the mapping relations between the physical address and the logical address, obtain the concrete operations instruction
It the middle physical address by operation data, will be recalled from the storage medium by operation data, calculate the concrete operations instruction
The middle length by operation data, cutting is carried out by the length of operation data in being instructed to the concrete operations, cutting is 8 bytes
One group, and set read signal to read length every time for the number for the group being split in concrete operations instruction by operation data
For 8 bytes, read and read signal is subtracted one, and started the CPU microservers based on ARM and carry out data transmission, it is described
ARM baseboard controllers will control the Ethernet switch that data transfer is gone out, when the read signal is 0, end of transmission；
The process of the write operation of the memory module is：
The storage control simultaneously sends concrete operations and instructed to the command register, the command register ejection it is described
Concrete operations instruction instructs for write operation, and the operation that the CPU microservers based on ARM are carried out is as follows：
Concrete operations instruction is read, the address relationship logically is transferred from the cache module, is described patrol
Collect by the physical address of operation data in address, concrete operations instruction, concrete operations instruction, it is now, described specific
By the physical address of operation data to be empty in operational order, comprising the data for needing to write in the write operation instruction, to described
The data for needing to write carry out cutting, and cutting is that 8 bytes are one group, and set write signal as the data quilt for needing to write
The number of the group of cutting, it is 8 bytes to write take length every time, writes and subtracts one by the write signal, and is started described based on ARM's
CPU microservers carry out data transmission, and the ARM baseboard controllers will be controlled described in the Ethernet switch from outside reading
The data write are needed, when the read signal is 0, end of transmission；
The idle physical block that the storage control is distributed in the storage medium, look for the minimum idle thing of physical address
Block is managed, changes the mapping relations between the physical address and the logical address, logical address is mapped as the physics of distribution
The physical address of the minimum idle physical block in address, 8 bytes are one group and write toward the minimum idle physical block of physical address
Enter data, current physical address minimum idle physical block is redistributed during failure when writing, again repeatedly said process；
The data record process of the memory module is：Scanning is timed to the bad block in the storage medium, by bad block from
Removed in idle physical block in the storage medium；
The ARM baseboard controllers are the key control units of whole system, and the whole distribution is controlled by system bus
Storage system, realize the upper and lower electricity to the CPU microservers based on ARM and the storage medium, reset management,
Position detection, IP configurations, and control the whole distributed memory system power-on and power-off, startup self-detection, Ethernet switch control,
The management of the system power supply module, the control of the fan；
The CPU microservers based on ARM, it is connected by connector with the multiple storage medium, is become described
Intelligent storage node in distributed memory system, and receive the instruction from the ARM baseboard controllers, realize and deposited to described
Upper electric, lower electricity, data transfer and the other management of storage media；
The Ethernet switch is responsible for being connected with external switch, realizes the data exchanging function on network；
The system power supply module is responsible for the whole distributed memory system and provides the energy；
The system fan provides cooling source for the whole distributed memory system.
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