CN107561432A

CN107561432A - A kind of clock signal fault detection method based on even-odd check

Info

Publication number: CN107561432A
Application number: CN201710621834.8A
Authority: CN
Inventors: 陈飞宇; 王耀明
Original assignee: 724th Research Institute of CSIC
Current assignee: 724th Research Institute of CSIC
Priority date: 2017-07-27
Filing date: 2017-07-27
Publication date: 2018-01-09

Abstract

The present invention is a kind of clock signal fault detection method based on even-odd check, the method can occur being delayed to clock signal in timing sequence signal generator, be along shake, pulse width variations and signal deletion progress fault detect and instruction, the thinking of the invention before and after pulse：The time sequence status of the cover signal exported by PLD is extrapolated for the parity of high level number according to multichannel clock signal synchronization；Multicircuit time clock signal and cover signal are sent into odd even detection circuit to be detected, when there is delay, shake, pulse width variations and missing in any road clock signal, level conversion will occur for the output end of detection circuit, finally detect clock signal failure and indicate.

Description

A kind of clock signal fault detection method based on even-odd check

Technical field

The invention belongs to fault detection technique field.

Background technology

In the electronic equipment of radar or other large-scale and complicated devices, internal each subdivision generally requires the work of harmonious orderly Make, it is general to use clock signal to be controlled and trigger to ensure the synchronism of each unit work.Thus require that timing sequence is believed The clock signal that number generator is sent protects the stringent synchronization in sequential, no time jitter, no signal missing, and pulse width is kept not Become, to fulfill this requirement, on the premise of Fine design manufactures, consider the factors such as interference, it is also necessary to which clock signal is carried out Fault detect.

The design of common radar timer is realized using PLD more at present, the scheme of its fault detect Much such as：1. timer clock is sent into PLD carries out frequency division counter, count results are entered with reference clock Whether normal row contrast, carry out judgment standard clock；2. the condition indicative signal using the loading of PLD program is indirect Judge whether timing signal has produced；3. will be right wherein all the way or a few road time series pulse signals change into Transistor-Transistor Logic level signal It is detected.First two scheme is without the clock signal for directly detecting timer output, and the third scheme is then simply to one Or several clock signals are detected, occurs the exception of edge shake before and after delay, pulse width variations and pulse signal to signal Phenomenon is difficult detection.

Whole clock signal failures that the present invention is exported using the thinking of odd even detection to timer detect.

The content of the invention

The invention provides a kind of clock signal fault detection method.

The present invention first extracts the cover signal of one group of clock signal to be detected, and the extraction principle of cover signal is：At that time Sequential signal is the number of high level when being even number, and cover signal is high level, otherwise is low level.Then by clock signal to be measured Odd even detection circuit is sent to together with cover signal, when certain clock signal appearance delay, pulsewidth change all the way of this group of clock signal Change, be vacant, be front and rear along during shake, feeding odd even detection circuit input end mouth becomes even number for the signal number of high level, causes Level conversion occurs for odd even detection circuit output port signal, sends fault indication signal.

Compared with prior art, it is mainly characterized in that the present invention：

(1) fault detect can be carried out to whole timing sequence signals；

(2) failures such as timing signal missing, delay, pulse width variations can be detected；

(3) it can detect that the pulse of clock signal is front and rear along transient faults such as shakes.

So the present invention is a kind of more accurate more direct timing failure detection method.

The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings

Brief description of the drawings

Fig. 1 odd evens detect circuit block diagram.

The design principle block diagram of Fig. 2 pulse signal generators therefore inspection circuit.

Embodiment

The specific implementation step of the present invention is as follows：

(1) multichannel clock signal is grouped first, can be only divided into one group, also can be according to the correlation degree of work point To be multigroup；

(2) " the cover signal " of every group of clock signal is determined, determining the principle of cover signal is：When this group of clock signal is When the number of high level is even number, cover signal is high level, otherwise is low level.So, clock signal has several groups, just has several Road " cover clock signal "；

(3) " cover signal " generator is realized：The time sequence status of cover signal is passed through with a kind of hardware description language The mode write-in program of programming, is loaded into the storage chip of timer circuit by composing software, is achieved in that all the way or more Road " cover clock signal "；

(4) every group of clock signal and corresponding " cover signal " are sent into every group of odd even detection circuit and tested, When certain road clock signal occurs abnormal, this group of odd even detection circuit will send out fault message.All fault messages can be sent Enter an AND logic circuit computing, as long as one is broken down, logic circuit will send fault alarm.

Claims

A kind of 1. clock signal fault detection method based on even-odd check, it is characterised in that：First produced and " mended using odd even detection Position signal ", cover signal is sent into parity checker together with clock signal to be checked and carries out even-odd check, when directly detecting Delay, pulse width variations, pulse missing, the pulse of sequential signal appearance are front and rear along jitterbug.
A kind of 2. clock signal fault detection method based on even-odd check according to claim 1, it is characterised in that：Institute The determination method for stating cover signal is：The moment is determined according to the parity of one group of clock signal any instant high level number The height of the level of " cover signal ", when one group of clock signal high level number is even number, the level of " cover signal " is height, Otherwise the level of " cover signal " is low；It is or completely opposite.