CN107546222A - Semiconductor device including ldmos transistor - Google Patents

Semiconductor device including ldmos transistor Download PDF

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Publication number
CN107546222A
CN107546222A CN201710485102.0A CN201710485102A CN107546222A CN 107546222 A CN107546222 A CN 107546222A CN 201710485102 A CN201710485102 A CN 201710485102A CN 107546222 A CN107546222 A CN 107546222A
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region
semiconductor device
grid
substrate
hole
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CN201710485102.0A
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CN107546222B (en
Inventor
A.比尔纳
M.布劳恩
H.布雷赫
C.埃克尔
M.齐格尔德伦
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Infineon Technologies AG
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Infineon Technologies AG
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
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  • Engineering & Computer Science (AREA)
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Abstract

The present invention relates to the semiconductor device including ldmos transistor.In embodiment, a kind of semiconductor device includes：Semiconductor substrate, there is the Ohm.cm of body resistivity ρ >=100, preceding surface and rear surface；At least one ldmos transistor, in Semiconductor substrate；With RESURF structures.RESURF structures include doping buried layer, and doping buried layer is arranged in the semiconductor substrate, and preceding surface and rear spaced apart from surfaces certain distance, and with least one region couples in the channel region and body contact region of ldmos transistor.

Description

Semiconductor device including ldmos transistor
Background technology
Continue to need being adapted to the solid-state circuit in higher and higher frequency (including microwave frequency) operation.As herein Used, term " microwave " be intended to indicate that about 300 MHz or higher than about 300 MHz (for example, in 300 MHz and 3 GHz Between) frequency.The various transistor arrangements of gain can be provided in this frequency range by having created.LDMOS (sideways diffusions Metal-oxide semiconductor (MOS)) transistor be this transistor arrangement example.
For the power amplifier circuit with very fast switching speed, it is desired to have high-breakdown-voltage and connects electricity with low The ldmos transistor of resistance.However, these parameters are influenceed in the opposite manner.For example, by increasing drift length, breakdown is improved Voltage, but increase and connect resistance.
Therefore, it is desirable to the further improvement of the performance improved is provided for transistor unit in higher frequency.
The content of the invention
In embodiment, a kind of semiconductor device includes：Semiconductor substrate, have the Ohm.cm of body resistivity ρ >=100, Preceding surface and rear surface；At least one ldmos transistor, in Semiconductor substrate；With RESURF structures.RESURF structure bags Including doping buried layer, doping buried layer is arranged in the semiconductor substrate, and preceding surface and rear spaced apart from surfaces certain distance, and And with least one region couples in the channel region and body contact region of ldmos transistor.
In embodiment, a kind of semiconductor device includes：Semiconductor substrate, have the Ohm.cm of body resistivity ρ >=100, Preceding surface and rear surface；At least one ldmos transistor, in Semiconductor substrate, ldmos transistor include source region, Drain region, channel region, drift region and body contact region, wherein source region are coupled on the rear surface of substrate Conductive layer；Buried layer is adulterated, is arranged in the substrate, and preceding surface and rear spaced apart from surfaces certain distance, and it is brilliant with LDMOS The body contact region coupling of body pipe；Grid cover, extend from grid towards the source region of ldmos transistor；And field plate, from Grid extends towards the drain region of ldmos transistor.
In embodiment, a kind of method includes：With body resistivity ρ >=100 Ohm.cm Semiconductor substrate in note Enter to have the concentration of dopant of the first conductivity type from depletion layer；And ldmos transistor is formed in the preceding surface of substrate, with So that source region, channel region, drift region and drain region by a part for substrate and with being separated from depletion layer, its Described in body contact region extend to from depletion layer and coupled with from depletion layer.
Those skilled in the art will recognize other when reading following detailed description and when watching accompanying drawing Feature and advantage.
Brief description of the drawings
The element of accompanying drawing may not be drawn to scale relative to each other.Identical label specifies corresponding similar portions.It is various to show The feature of the embodiment gone out can be combined, unless they repel each other.Depicted example embodiment and under in the accompanying drawings Detailed examples embodiment in the description in face.
Fig. 1 diagrams include the semiconductor device of the ldmos transistor with RESURF structures.
Fig. 2 diagrams include the semiconductor device of the ldmos transistor with RESURF structures.
Fig. 3 diagrams include the semiconductor device of the ldmos transistor with RESURF structures.
Fig. 4 diagrams include the semiconductor device of the ldmos transistor with RESURF structures.
Fig. 5 diagrams include the semiconductor device of the ldmos transistor with RESURF structures.
Fig. 6 diagrams include the semiconductor device of the ldmos transistor with RESURF structures.
Fig. 7 illustrates the flow chart of the method for processing the ldmos transistor with RESURF structures.
Embodiment
In the following detailed description, referring to the drawings, accompanying drawing forms a part and in the accompanying drawings for the detailed description The particular embodiment of the present invention can be implemented by being shown by way of illustration.In terms of this, with reference to (one or more) described The orientation use direction term of accompanying drawing, " top ", " bottom ", "front", "rear", " head ", " tail " etc..Because the part energy of embodiment Enough it is located at many different azimuths, so direction term is used for the purpose of explanation, and is by no means limitative.It should be understood that not In the case of departing from the scope of the present invention, other embodiments can be used and structure or logical changes can be realized.It should not limit Understand following detailed description in property meaning, and be defined by the independent claims the scope of the present invention.
Many exemplary embodiments will be explained below.In this case, identical architectural feature is by the phase in accompanying drawing Same or similar label identification.In the context of this description, " lateral " or " lateral " should be understood that and mean substantially On parallel to the lateral extent of semi-conducting material or semiconductor carrier the direction extended or scope.Lateral therefore generally Extend parallel to these surfaces or side.In contrast to this, term " vertical " or " vertical direction " are understood to imply generally Extend perpendicular to these surfaces or side and therefore perpendicular to the direction that lateral extends.Vertical direction is therefore along half The thickness direction of conductor material or semiconductor carrier extends.
As employed in this specification, when element (such as, layer, region or substrate) is referred to as " on another element " or When " extending on another element ", it on another element or can be extended directly on another element, Or intermediary element also may be present.By contrast, when element is referred to as " on another element " or " extends directly into another On one element " when, in the absence of intermediary element.
As employed in this specification, when element is referred to as " connecting " or during " coupled " to another element, it can be direct Another element is connected or coupled to, or intermediary element may be present.By contrast, when element be referred to as " being directly connected to " or When " direct-coupling " arrives another element, in the absence of intermediary element.
As used herein, various type of device and/or doped semiconductor regions can be identified as with n-type or p-type, But this merely to the convenience of description and be not intended to it is restricted, and this identification can by with " the first conductivity type " or The more typically description of " the second opposite conductivity type " is replaced, and wherein the first kind can be n or p-type and Second Type is then p or n Type.
It will be understood to those of skill in the art that (one or more) active device (such as, ldmos transistor) can basis The property of (one or more) device and be formed on substrate or formed above substrate or be formed entirely in substrate or Person is partially formed in substrate and is partially formed on substrate or is formed above substrate.Therefore, such as herein for (one or more) active device is used, and term " in the substrate ", " in the semiconductor substrate " and equivalent are intended to include institute There is this change.
Fig. 1 illustrates the semiconductor device 10 according to embodiment.Semiconductor device 10 includes Semiconductor substrate 11, semiconductor lining Bottom 11 has preceding surface 12 and rear surface 13.There is Semiconductor substrate 11 body resistivity ρ, body resistivity ρ to be more than or equal to 100 Ohm.cm.Semiconductor device 10 includes at least one LDMOS (the sideways diffusion metal oxides half being located in Semiconductor substrate 11 Conductor) transistor 14.Semiconductor device 10 also includes RESURF structures 15, and RESURF structures 15 include being arranged in Semiconductor substrate Doping buried layer 16 in 11.Doping buried layer 16 and preceding surface 12 separate certain distance, and with Semiconductor substrate 11 Surface 13 separates certain distance afterwards.Adulterate channel region 17 and/or the body contact region of buried layer 16 and ldmos transistor 14 Domain 18 couples.
RESURF structures 15 (reducing surface field structure) in ldmos transistor are used to reduce before Semiconductor substrate 11 The electric field on surface 12 and realized between high-breakdown-voltage and low on-resistance improved compromise.
Semiconductor substrate 11 has the body resistivity ρ more than or equal to 100 Ohm.cm, and can be described as having height Resistance.In certain embodiments, Semiconductor substrate 11 includes silicon and may include silicon single crystal.
When the body resistivity of Semiconductor substrate is equal to or more than predeterminated level, substrate relevant inductor and capacitive parasitic effect It can reduce.Desired predeterminated level is valuably equal to or more than 100 Ohm.cm resistivity, is easily equal to or more than about 500 Ohm.cm resistivity, more easily it is equal to or more than about 1000 Ohm.cm resistivity.As used herein, term " body resistivity " be related to substrate 60 be located at device region outside (for example, doped region and any pass positioned at ldmos transistor Outside the RESURF structures of connection) those parts.
The doping buried layers 16 of RESURF structures 15 is provided with reduce the electric field on the preceding surface 12 of Semiconductor substrate 11 with And particularly, the drain side edge at the drain side edge 28 of grid 21 and in the direction along drain region 20 from grid 21 The electric field on the preceding surface 12 of Semiconductor substrate 11 in 28 regions started.Doping buried layer 16 is also configured to exhaust certainly And source ground.Doping buried layer 16 is used for by making the less mutation of drain junction limit drain-source leakage, and helps The depletion drift region domain during the biasing of drain junction.
As used herein, term " ldmos transistor " represents the single LDMOS crystal for including source electrode, grid and drain electrode Tubular construction.Single LDMOS transistor structure is also referred to as primitive or fragment.Ldmos transistor 14 includes：Source region 19, quilt Utilize the second conductivity type (for example, n+) high doped；With drain region 20, it is utilized the second conductivity type (for example, n+) and highly mixes It is miscellaneous.Source region 19 and drain region 20 are placed asymmetrically on around grid 21 on the preceding surface 12 of Semiconductor substrate 11, Grid 21 is disposed on preceding surface 12.
Direction of the drift region 22 along drain region 20 is extended in preceding surface 12 from grid 21, and can be doped with second Conductivity type (for example, n).Compared with drain region 20, drift region 22 is extended more deeply into Semiconductor substrate 11.Drift region Doped with the second conductivity type (for example, n), and there is the doping smaller than the concentration of dopant of drain region 20 and source region 19 Thing concentration.Compared with channel region 17, drift region 22 extends bigger distance in Semiconductor substrate 11, but passes through semiconductor A part for substrate 11 and with doping buried layer 16 separate.
Ldmos transistor 14 also includes：Channel region 17, extend below source region 19 from drift region 22；And master Body contact zone domain 18, doped with the first conductivity type, and extend more deeply into from preceding surface 12 compared with channel region 17 and partly lead In body substrate 11.By the high doped trap for extending to doping buried layer 16 and second conductivity type overlapping with doping buried layer 16 Provider's contact area 18.
In certain embodiments, Semiconductor substrate 11 may include the silicon being lightly doped using the first conductivity type (for example, p--). Bury doped layer 16 can doped with the first conductivity type (for example, p), channel layer 17 can doped with the first conductivity type (for example, p), and And body contact region 18 carries out high doped using the first conductivity type (for example, p+).
Ldmos transistor 14 is one of multiple transistor primitives or fragment, and thus the identical electrode of transistor primitive leads to The unshowned metallization structure being arranged on preceding surface 12 is crossed electronically to be coupled to form single switch device. In symmetrical structure, drain region 20 is provided at around center line 23, and is two neighbouring transistor primitives or fragment Common drain region 20 is provided.It is also possible, however, to use asymmetric arrangement.
Drain region 20 is with valuably at least 5.1019 cm-3Doping concentration, easily at least 1.1020 cm-3Mix Miscellaneous concentration, and more easily at least 3.1020 cm-3Doping concentration, but higher or lower doping concentration can also be used.Drift Move region 22 and be close to drain region 20 along lateral in symmetrical structure, and with valuably in 1.1016 cm-3Arrive 1.1018 cm-3Scope in, easily in 7.1016 cm-3To 3.1017 cm-3Scope in, and be more easily in 1.1017 cm-3To 2.1017 cm-3Scope in doping concentration, but higher or lower doping concentration can also be used.Relative to The laterally outside of the drift region 22 of center line 23 is channel region 17, and channel region 17 is located under at least a portion of grid 21 Face.Channel region 17, which has, is valuably in 1.1017 cm-3To 2.1018 cm-3Scope in, easily in 3.1017 cm-3 To 1.1018 cm-3Scope in, and more easily be in 5.1017 cm-3To 9.1017 cm-3Scope in doping concentration, But higher or lower doping concentration can also be used.The laterally outside of channel region 17 is source region 19.Source region 19 has Have valuably at least 5.1019 cm-3, easily at least 1.1020 cm-3, and more easily at least 3.1020 cm-3Doping it is dense Degree, but higher or lower doping concentration can also be used.The laterally outside of source region 19 is body contact region 18.Main body connects Touching region 18 has valuably in 1.1018 cm-3To 1.1020 cm-3Scope in, easily in 2.1018 cm-3Arrive 7.1019 cm-3Scope in, and more easily be in 5.1018 cm-3To 5.1019 cm-3Scope in doping concentration, but Higher or lower doping concentration can also be used.Substrate 11, which can have, is in 1.1017 cm-3To 2.1018 cm-3Scope in Doping concentration.Adulterating buried layer can have in 1.1013 cm-3To 2.1015 cm-3Scope in doping concentration.
When grid 21 is suitably biased, conducting channel 17 is formed between source region 19 and drain region 20.With The exemplar conductive type of upper proposition is suitable for forming N-channel structure, it will be apparent, however, to one skilled in the art, that passing through various doping The appropriate exchange of the conductivity type in region and the biasing on grid 21 it is suitably modified, can also form P-channel structure.
The source region 19 of ldmos transistor 14 can be coupled to the rear surface 13 of Semiconductor substrate 11.Source region 19 Conductive path between rear surface 13 can have multi-form.
In certain embodiments, there is provided conductive through hole, the conductive through hole prolong from preceding surface 12 through Semiconductor substrate 11 Reach rear surface 13.Conductive through hole can be positioned, so as to which body contact region 18 surrounds the top of conductive through hole.Conductive through hole can Small pieces of cloth used for patches has metal (such as, tungsten or copper).In certain embodiments, the underfill of conductive through hole has high purity copper, and described logical The top in hole includes surrounding the high purity copper cladding sidewall in space.The top of the through hole can be sealed on the top of substrate through vias Interior offer chamber or gap.
Contact structures including one or more metal levels can be substantially on the whole rear surface 13 of Semiconductor substrate 11 Fang Yanshen.The contact structures on surface 13 can be electrically coupled to the phase of Semiconductor substrate 11 for example, by conductive through hole afterwards To preceding surface 12 in source region 19.
Ion is carried out by using preceding surface 12 of the mask and dopant ions being suitably constructed through Semiconductor substrate 11 Inject and by being then diffused to the region of injection, doping buried layer 16, channel region 17, body contact region can be formed Domain 18, drift region 22, source region 19 and drain region 20.
In some embodiments (embodiment such as, shown in Fig. 2), source region 19 includes Dual Well Structure, and leaks Polar region domain 20 includes Dual Well Structure.Second trap 23 of drain electrode 20 can surround the trap 24 of more high doped, and thus two traps are all mixed It is miscellaneous to have the second conductivity type.
The trap 25 of the more high doped of source region 19 may extend into the source side 26 of grid 21, and extend to main body Outside the lateral extent of contact area 18.Compared with the trap 25 of more high doped, source region 19 it is more lightly doped Trap 27 is extended more deeply into substrate 11, and the distance extended is more slightly smaller than the distance that channel region 17 extends, and can be complete In body contact region 18.The embodiment shown in ldmos transistor 14 and the remainder and Fig. 1 of RESURF structures 15 It is identical.
In the embodiment shown in fig 1 and 2, the doping buried layer 16 of RESURF structures 15, which continuously extends through, partly leads The side zones of body substrate 11, and continuously under the source region 19 of ldmos transistor 14, grid 21 and drain region 20 Fang Yanshen.Doping buried layer 16 is separated by a part for Semiconductor substrate 11 with drift region 22 and channel region 17. It is big and smaller than the concentration of dopant of channel region 17 to adulterate concentration of dopant of the buried layer 16 with than Semiconductor substrate 11 Concentration of dopant.
RESURF structures 15 are provided to reduce the electric field and in particular on the preceding surface 12 of Semiconductor substrate 11, in grid The electric field on the preceding surface 12 of Semiconductor substrate 11 in the direction at the drain side edge 28 of pole 21 and along drain region 20. RESURF structures 15 can be used for the breakdown voltage for increasing transistor, while keep low on-resistance.
In addition to adulterating buried layer 16, RESURF structures 15 may also include other feature to reduce in Semiconductor substrate The electric field on 11 preceding surface 12.In certain embodiments, RESURF structures include at least one field plate.Field plate can be from the court of grid 21 Drain region 20 to extend.The doping of field plate, the size for adulterating buried layer 16 and position, doping buried layer 16 and drift region 22 Horizontal and profile can be chosen so as to produce less than the electric field for it is expected threshold value (for example, 0.5 MV/cm) on preceding surface 12.
Semiconductor device 10 of Fig. 3 diagrams with RESURF structures 15, RESURF structures 15 include doping buried layer 16 simultaneously And comprise additionally in field plate 33.Semiconductor device 10 includes the first dielectric layer 30 on the preceding surface 12 of Semiconductor substrate 11 (for example, TEOS layers).First dielectric layer 30 is constructed and had：Opening above drain contact areas 23, described Drain metal contacts portion 31 is formed in opening；With the opening above source region 25, source electrode gold is formed in said opening Belong to contact site 32.First dielectric layer 30 covers grid 21, and source side gate edge 26 and source metal contact site 32 it Between and extend between drain side gate edge 28 and drain metal contacts portion 31.
RESURF structures include field plate 33, and field plate 33 is located on the first dielectric layer 30 of the top of grid 21, along drain metal The direction of contact site 31 extends on the first dielectric layer 30.
Second dielectric layer 34 is deposited, to cause it to be located at source electrode in source metal contact site 32, the first dielectric layer 30 Upper between Metal contacts 32 and field plate 33, above grid 21, field plate 33, the first dielectric layer 30 in field plate The upper extended between 33 and drain metal contacts portion 31 and the extension above drain metal contacts portion 31.Second dielectric Layer 34 may include the silica in two or more sublayers, such as the first sublayer and the first sublayer of silicon oxynitride (SiON) (SiO2) the second sublayer.
Grid cover 35 is disposed on the second dielectric layer 34 of the top of grid 21, and is prolonged along the direction of source region 19 Stretch.Grid cover 35 can be conformally deposited on the second dielectric layer 34, and grid side that can be partly with field plate 33 is handed over It is folded.
In this embodiment, RESURF structures 15 include doping buried layer 16, lightly doped drain region 22 and field plate 33. The size of Fig. 4 diagram RESURF structures 15 and LDMOS transistor structure, the size can be optimized to reduce on preceding surface 12 The electric field of (especially, in the drain side edge 28 of grid 21).
In order to reduce preceding surface 12 and particularly the drain side edge 28 of grid 21 given transistor arrangement it is (all Such as, the transistor arrangement shown in Fig. 2) electric field, the drain side edge 28 of grid 21 and the drain side edge 36 of field plate 33 it Between field plate length LFP, grid 21 length LG, the drain side edge 28 of grid 21 and the grid in drain metal contacts portion 31 The length L of drift region between lateral edges 37LDD, field plate above drift region height DFP, drift region is relative to preceding surface 12 Depth DLDDIt can be suitably selected and optimize relative to the depth D on preceding surface 12 with doping buried layer 16.
The suitably sized of transistor arrangement can be different according to the voltage class of transistor unit.For 28 V to 30 V Voltage class, length LFPIt can be in 0.8 μm to 1.2 μm of scope, length LGIt can be at 0.2 μm to 0.5 μm of model In enclosing, length LLDDIt can be in 2.5 μm to 3.2 μm of scope, height DFPIt can be in 0.1 μm to 0.2 μm of scope, Depth DLDDIt can be in 0.1 μm to 0.5 μm of scope, and the depth D for adulterating buried layer can be at 0.5 μm to 2.5 μm Scope in.
For 18V voltage class, length LFPIt can be in 0.4 μm to 1.0 μm of scope, length LGIt can be at 0.15 μm into 0.3 μm of scope, length LLDDIt can be in 0.8 μm to 2.5 μm of scope, height DFP0.05 μm is can be to arrive In 0.15 μm of scope, depth DLDDIt can be in 0.1 μm to 0.5 μm of scope, and the depth D for adulterating buried layer can locate In 0.3 μm to 2.0 μm of scope.
For 50V voltage class, length LFPIt can be in 0.8 μm to 2.0 μm of scope, length LGIt can be at 0.3 μm into 0.8 μm of scope, length LLDDIt can be in 3.0 μm to 8.0 μm of scope, height DFP0.15 μm is can be to arrive In 0.35 μm of scope, depth DLDDIt can be in 0.1 μm to 1.0 μm of scope, and the depth D for adulterating buried layer can locate In 0.5 μm to 3.0 μm of scope.
Semiconductor device can show at least 60 volts of breakdown voltage, while support at least 0.15 A/mm saturation electricity Stream.
Source region 19 can be coupled to the rear surface 13 of Semiconductor substrate 11, and especially, be coupled to after being arranged in Conductive layer 37 on surface 13.Conductive layer 37 can provide for semiconductor device 10 being installed to substrate and/or the Horizon of encapsulation Engagement pad on face.In certain embodiments, the connection between source region 19 and the rear surface 13 of Semiconductor substrate 11 is by extremely The conductive path being at least partially located in Semiconductor substrate 11 provides.The example of conductive path workable for the diagrams of Fig. 5 and 6.
Fig. 5 diagrams provide the embodiment of substrate through vias (TSV) 40, and TSV 40 prolongs from the preceding surface 12 of Semiconductor substrate 11 Reach the rear surface 13 of Semiconductor substrate 11.TSV 40 may include the conductive material 41 (such as, tungsten) for filling TSV 40.TSV 40 It may include outmost dielectric liner so that the doped region of the conductive path in TSV 40 and Semiconductor substrate 11 electricity is exhausted Edge.One or more backing layers, diffusion impervious layer and/or the Seed Layer for providing adhesion promotion are disposed in the side for defining TSV 40 Between the material and conductive material 41 of the Semiconductor substrate 11 of wall.Conductive material 41 can be by being arranged in the preceding surface 12 of substrate 11 On metallization structure 42 a part and be electrically coupled to source region 19.TSV 40, which is extended through, is arranged in preceding table Dielectric layer 43 on face 12, and the metal level 44 being arranged on dielectric layer 43 is coupled to, metal level 44 is led further through another Electric through-hole 45 and be coupled to source region 19, another conductive through hole 45 extend through dielectric layer 43 reach source metal connect Contact portion 32.Metal level 44 may include aluminium.
Fig. 6 illustrates the structure according to the substrate through vias (TSV) 50 of another embodiment, and TSV 50 is from Semiconductor substrate 11 Preceding surface 12 extends to the rear surface 13 of Semiconductor substrate 11.Pictorial illustration ldmos transistor 14 and the electrical connection with TSV 50 Zoomed-in view.
TSV 50 includes the first current-carrying part 51 positioned at its bottom, and it is (all that the first current-carrying part 51 includes conductive material Such as, high purity copper).In bottom, conductive material filling TSV 50 volume and the part on surface 13 after formation, with cause it with Conductive layer 37 on the rear surface 13 of Semiconductor substrate 11 directly contacts.TSV 50 also includes conformal electrically conductive layers 52, conformal Conductive layer 52 is disposed in the side wall of through hole and is arranged at the upper surface of the current-carrying part 51 positioned at the bottom of through hole Circumference on.Conformal electrically conductive layers 52 may also include high purity copper.Conductive layer 52 can define space 53, space in TSV 50 top 53 for example can be sealed to form gap 55 in TSV 50 top by conductive layer or semiconductor layer or dielectric layer 54 at top.
TSV 50 upper region is surrounded by body contact region 17.TSV 50 can be arranged in substrate according to row or array The region between neighbouring ldmos transistor in one of multiple TSV.One TSV or multiple TSV can be coupled to two The source region of individual neighbouring ldmos transistor.
Conformal electrically conductive layers 52 can also extend above the preceding surface 12 of Semiconductor substrate 11, and can be placed directly and lead Coupled in electric layer 56 and electronically with conductive layer 56, conductive layer 56 is coupled to source in the position adjacent with source region 19 Pole Metal contacts 32.
One or more other layers can be disposed on TSV 50 wall, as adhesion-promoting layer, diffusion impervious layer and/ Or Seed Layer, for example, physical vapour deposition (PVD) and/or chemical vapour deposition technique can be used to come depositing Ti, TiN and Cu Seed Layers, And deposit Part I 51 and conformal electrically conductive layers 52 by electro-deposition techniques.
In this embodiment, dual damascene technology can be used to form conformal electrically conductive layers 52.Usable electroplating technology is formed altogether Shape conductive layer 52 and current-carrying part 51.For example, the condition for the first current-carrying part of electro-deposition 51 may differ from being used for first Those conditions of the electro-deposition above of current-carrying part 51 conformal electrically conductive layers 52.
First current-carrying part 51 and conformal electrically conductive layers 52 can have diverse microcosmic structure, such as different average grain sizes.
Fig. 7 illustrates to be used to process with RESURF structures according to one or more embodiments described herein The flow chart 80 of the method for ldmos transistor, wherein the RESURF structures include doping buried layer.
In block 81, methods described includes：With body resistivity ρ >=100 Ohm.cm Semiconductor substrate in inject Concentration of dopant with the first conductivity type from depletion layer；And in block 82, it is brilliant that LDMOS is formed in the preceding surface of substrate Body pipe, to cause source region, channel region, drift region and drain region by a part for substrate and with dividing from depletion layer Separate and body contact region extends to from depletion layer and coupled with from depletion layer.
It can be injected into from depletion layer, to cause it continuously to extend through the side zones of substrate.Substrate, channel layer and from Depletion layer is doped with the first conductivity type, so that the concentration of dopant derived from depletion layer is more than the concentration of dopant of substrate and is less than The doping concentration of channel region.Body contact region has denseer than the dopant of channel region doped with the first conductivity type Spend big concentration of dopant.Can be by forming channel layer and body contact region from the injection of preceding surface and subsequent diffusion.It can lead to Cross from the injection of preceding surface and then spread to form drift region.
Source region, drift region and drain region have the concentration of dopant of the second conductivity type, the second conductivity type and the One conductivity type is opposite.Compared with drift region, source region and drain region are more highly adulterated.Also can be by from preceding table Face is injected to form source region, drift region and drain region.
After ldmos transistor is formed, methods described can be advanced further to block 83, and including by blind via hole or envelope Enclosed through hole is inserted into the preceding surface of substrate, so that obtaining body contact region surrounds through hole, in block 84, conductive material is inserted Enter into blind via hole, and in block 85, conductive material is electronically coupled to source region.
In certain embodiments, conductive material is inserted into through hole includes：Conductive material is inserted into through hole and The Part I of filling through hole is formed in the bottom of through hole, and conductive material is inserted into the top of through hole, the conduction The side wall of material small pieces of cloth used for patches through hole is to surround space.Methods described can be advanced further to block 86, and including remove substrate after Conductive layer is put on rear surface by the part on surface to expose the conductive material in through hole on rear surface, and in block 87 And conductive material.
According to the one or more for including one or more ldmos transistors of any one embodiment described herein Semiconductor device can be used for high-frequency power amplifying circuit, such as be operated with the frequency in 700 MHz to 3.6 GHz scope Power conversion and Doherty (Doherty) in RF power amplification circuits, cellular communications networks for cellular communication is with storing Big circuit.
Space relative terms (such as, " ... below ", " ... lower section ", " under ", " ... top ", " on " etc.) in order to Easily describe and be used to explain positioning of the element relative to the second element.These terms be intended to include except with accompanying drawing The different azimuth of described device outside the different orientation in those orientation of middle description.In addition, " first ", " second " etc. Term also be used to describe various elements, region, part etc., and it is restricted to be not intended to.Identical term is describing In represent identical element all the time.
As used herein, term " having ", " containing ", "comprising", " comprising " etc. are open-ended terms, the opening The element of formula term instruction statement or the presence of feature, but it is not excluded for other element or feature.Article " a (one) ", " an (one) " and " the (being somebody's turn to do) " are intended to include plural number and odd number, unless the context clearly dictates otherwise.It should be understood that unless Particularly point out in addition, otherwise the feature of various embodiments described herein can be combined with each other.
Although illustrating and describing specific embodiment herein, it will be recognized by those of ordinary skill in the art that Without departing from the scope of the invention, the specific reality that various replacements and/or equivalent implementations alternatively show and described Apply example.The application is intended to any modification or change for including specific embodiments discussed herein.Accordingly, it is intended to the present invention only by Claim and its equivalent limitation.

Claims (27)

1. a kind of semiconductor device, including：
Semiconductor substrate, there is the Ohm.cm of body resistivity ρ >=100, preceding surface and rear surface；
At least one LDMOS (sideways diffusion metal-oxide semiconductor (MOS)) transistor, in Semiconductor substrate；With
RESURF structures, including doping buried layer, doping buried layer is arranged in the semiconductor substrate, with preceding surface and rear surface Separate certain distance, and with least one region couples in the channel region and body contact region of ldmos transistor.
2. semiconductor device as claimed in claim 1, wherein the doping buried layer continuously extends through Semiconductor substrate Side zones.
3. semiconductor device as claimed in claim 1, wherein the doping buried layer the source region of ldmos transistor, Continuously extend below grid and drain region.
4. semiconductor device as claimed in claim 1, wherein the substrate, the channel layer and the doping buried layer doping There is the first conductivity type, and the concentration of dopant of buried layer is more than the concentration of dopant of substrate and less than the doping of channel region Thing concentration.
5. semiconductor device as claimed in claim 4, wherein the body contact region is doped with the first conductivity type, and have There is the concentration of dopant bigger than the concentration of dopant of channel region.
6. semiconductor device as claimed in claim 1, wherein the doping buried layer is that oneself exhausts and by source ground.
7. semiconductor device as claimed in claim 1, wherein the RESURF structures are also included from grid towards LDMOS crystal The lightly doped region of the drain region extension of pipe.
8. semiconductor device as claimed in claim 1, wherein the RESURF structures also include at least one field plate.
9. semiconductor device as claimed in claim 1, wherein the RESURF structures are sized, to cause in grid and The electric field on preceding surface in region between drain region is less than 0.5 MV/cm.
10. semiconductor device as claimed in claim 1, in addition to：Field plate, have from the drain side edge of grid to drain electrode 0.8 μm to 1.2 μm of length L of grid lateral edgesFPWith 0.1 μm to 0.2 μm of height D above drift regionFP, wherein The grid has 0.2 μm to 0.5 μm of length LG, drift region has from the drain side edge of grid to drain metal contacts 2.5 μm to 3.2 μm of length L of the grid lateral edges in portionLDDWith 0.1 μm to 0.5 μm of the depth relative to preceding surface DLDD, and the doping buried layer has 0.5 μm to 2.5 μm of the depth D relative to preceding surface.
11. semiconductor device as claimed in claim 1, in addition to：Field plate, have from the drain side edge of grid to drain electrode 0.4 μm to 1.0 μm of length L of grid lateral edgesFPWith 0.05 μm to 0.15 μm of height D above drift regionFP, its Described in grid there is 0.15 μm to 0.3 μm of length LG, drift region has from the drain side edge of grid to drain metal 0.8 μm to 2.5 μm of length L of the grid lateral edges of contact siteLDDWith 0.1 μm to 0.5 μm of the depth relative to preceding surface Spend DLDD, and the doping buried layer has 0.3 μm to 2.0 μm of the depth D relative to preceding surface.
12. semiconductor device as claimed in claim 1, in addition to：Field plate, have from the drain side edge of grid to drain electrode 0.8 μm to 2.0 μm of length L of grid lateral edgesFPWith 0.15 μm to 0.35 μm of height D above drift regionFP, its Described in grid there is 0.3 μm to 0.8 μm of length LG, drift region has from the drain side edge of grid to be connect to drain metal 3.0 μm to 8.0 μm of length L of the grid lateral edges of contact portionLDDWith 0.1 μm to 1.0 μm of the depth relative to preceding surface DLDD, and the doping buried layer has 0.5 μm to 3.0 μm of the depth D relative to preceding surface.
13. semiconductor device as claimed in claim 1, wherein the semiconductor device has at least 60 volts of breakdown potential Pressure, while support at least 0.15 A/mm saturation current.
14. semiconductor device as claimed in claim 1, in addition to：Conductive through hole, substrate is extended to from the preceding surface of substrate Surface afterwards.
15. semiconductor device as claimed in claim 14, wherein the conductive through hole is coupled to the source electrode of ldmos transistor Region.
16. semiconductor device as claimed in claim 14, wherein the conductive through hole extends through body contact region.
17. semiconductor device as claimed in claim 14, wherein the conductive through hole includes filling through hole and rear surface phase The second current-carrying part of adjacent the first current-carrying part and arrangement over the first portion, the side wall of the second current-carrying part small pieces of cloth used for patches through hole is simultaneously And surround space.
18. a kind of method, including：
Including body resistivity ρ >=100 Ohm.cm Semiconductor substrate in injection with the first conductivity type concentration of dopant From depletion layer；And
Ldmos transistor is formed in the preceding surface of substrate, to cause source region, channel region, drift region and drain region Domain by a part for substrate and with being separated from depletion layer, wherein the body contact region extend to from depletion layer and with Coupled from depletion layer.
19. method as claimed in claim 18, wherein consumable layer to the greatest extent continuously extends through the side zones of substrate.
20. method as claimed in claim 18, wherein the substrate, channel layer and from depletion layer doped with the first conductivity type, And it is more than the concentration of dopant of substrate and less than the doping concentration of channel region from the concentration of dopant of depletion layer.
21. method as claimed in claim 20, wherein the body contact region is doped with the first conductivity type, and with than The big concentration of dopant of the concentration of dopant of channel region.
22. method as claimed in claim 18, in addition to：Through hole is inserted into the preceding surface of substrate, connect so as to obtain main body Touch region and surround through hole；
Conductive material is inserted into through hole；And
Conductive material is electronically coupled to source region.
23. method as claimed in claim 22, wherein conductive material is inserted into through hole includes：Conductive material is inserted into With in the Part I of the bottom of through hole formation filling through hole in through hole；And conductive material is inserted into the top of through hole, The side wall of the conductive material small pieces of cloth used for patches through hole surrounds the Part II in space to be formed.
24. method as claimed in claim 22, in addition to：
The part on the rear surface of substrate is removed to expose the conductive material in through hole on rear surface；And
Conductive layer is put on into rear surface and conductive material.
25. a kind of semiconductor device, including：
Semiconductor substrate, there is the Ohm.cm of body resistivity ρ >=100, preceding surface and rear surface；
At least one ldmos transistor, in Semiconductor substrate, the ldmos transistor includes source region, drain region Domain, channel region, drift region and body contact region, wherein source region are coupled to the conduction on the rear surface of substrate Layer；
Adulterate buried layer, be arranged in the substrate, and preceding surface and rear spaced apart from surfaces certain distance, and with LDMOS crystal The body contact region coupling of pipe；
Grid cover, extend from grid towards the source region of ldmos transistor；With
Field plate, extend from grid towards the drain region of ldmos transistor.
26. semiconductor device as claimed in claim 25, in addition to：Conductive substrates through hole, electronically by LDMOS crystal It is coupled to the conductive layer on rear surface in the source region of pipe.
27. semiconductor device as claimed in claim 26, wherein the conductive through hole includes filling through hole and rear surface phase The second current-carrying part of adjacent the first current-carrying part and arrangement over the first portion, the side wall of the second current-carrying part small pieces of cloth used for patches through hole is simultaneously And surround space.
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