CN107509036A - A kind of video camera large nuber of images compression method based on FPGA - Google Patents
A kind of video camera large nuber of images compression method based on FPGA Download PDFInfo
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- CN107509036A CN107509036A CN201710876818.3A CN201710876818A CN107509036A CN 107509036 A CN107509036 A CN 107509036A CN 201710876818 A CN201710876818 A CN 201710876818A CN 107509036 A CN107509036 A CN 107509036A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/80—Camera processing pipelines; Components thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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Abstract
The invention discloses a kind of video camera large nuber of images compression method based on FPGA.High-resolution, high frame per second large nuber of images compression problem are difficult to solve conventional images compression method, the present invention performs selective intake operation to pixel in camera review gatherer process using FPGA, and the mass image data Real Time Compression synchronous with pixel clock can be achieved.The inventive method can be used for industrial camera, high speed camera large nuber of images Fast Compression.
Description
Technical field
The invention mainly relates to digital imaging technology field, especially high-speed imaging technology field, refer in particular to one kind and be based on
FPGA video camera large nuber of images compression method.
Background technology
Visual imaging technology be widely used it is military, industrial, civilian, consumption etc. numerous areas.With digital imaging technology
Fast development, imaging sensor imaging resolution is increasing, image frame per second more and more higher, magnanimity is produced in imaging process
Picture signal, carry out immense pressure to IMAQ and storage tape.View data is high redundancy, can be pressed which dictates that it has
Contracting.Therefore, by compression of images, image data amount can be greatly reduced under the premise of certain information content is ensured, in favor of figure
As storage and transmission.
At present, in consumer electronics field, more using MPEG, H.264, H.265 etc. compressed format is pressed image
Contracting.In industrial vision field, particularly high-speed imaging technology field, above-mentioned method for compressing image is difficult to meet video camera magnanimity figure
As real time compression task demand.
The content of the invention
The technical problem to be solved in the present invention is：Conventional images compression method, computation complexity height be present, it is difficult to meet
Video camera large nuber of images Real Time Compression demand.
To solve the above problems, the present invention discloses a kind of video camera large nuber of images compression method based on FPGA, its feature
It is：It is characterized in that：FPGA (1) and video camera imaging sensor (2) are directly connected to, imaging sensor (2) output field synchronization
Signal V, line synchronising signal H, pixel clock CLK, pixel data D；FPGA (1) is connected with memory (3), and memory is deposited in (3)
There is compression of images to mark matrix F, F dimension is w*h, and wherein w is to gather picture traverse, h to gather picture altitude, and w, h's takes
It is that element value is 0 or 1 in 1~100000, F to be worth scope；FPGA (1) drives clock using pixel clock CLK as compression of images,
According to field sync signal V, line synchronising signal H, input pixel quantity is counted, and thus calculate current pixel P image coordinate
(i, j), i span is 0~w-1, and j span is 0~h-1；FPGA (1) reads compression of images in memory (3)
Mark (i, j) individual element in matrix F：F (i, j), as F (i, j)=0, current pixel P is not sampled, as F (i, j)=1,
The origin coordinates of element is (0,0) in sampling current pixel P, wherein F；After a line compression of images is completed, current line is compressed
In image deposit memory (3)；The compression of h rows image pixel is sequentially completed, obtains compressing image；The memory (3) includes
FLASH, DDR, SD storage chip.
Preferably, element F (i, j) value is random in compression of images mark matrix F.
Preferably, element F (i, j) value meets bi-distribution in compression of images mark matrix F：
F (i, j)=b (r) (1)
Wherein, b is Binomial Distributing Function, and r is the probability that Binomial Distributing Function output valve is equal to 1, r spans are 0~
1；Image compression ratio is equal with bi-distribution b () input parameter r, and image compression ratio is adjusted by adjusting r.
To ensure that pixel quantity is equal in compression image per a line, make all row vector F in compression of images mark matrix F
(i,:) interior element sum S (i) is equal, wherein, F (i,:) it is the vector that all elements are formed in the rows of F i-th, i span is
0~h-1.When h S (i) is unequal in the compression of images mark matrix F of bi-distribution generation, the average M of h S (i) is taken, and
M' is obtained to M round numbers；Manual modification compression of images mark matrix F in row vector F (i,:) interior element, make all S (i) in F=
M'；During repairing changes, the element of modification be dispersed evenly to row vector F (i,:) in.
To lift FPGA picture compression efficiencies, 2 twoport Block RAM are set to cache on FPGA：Buffer A、
Buffer B, wherein Buffer A are used for a row element in cache image compact token matrix F：F(i,:), Buffer B are used for
One-row pixels after caching collection compression of images；Buffer A size is：w bits；Buffer B size is m*w*d
Bits, wherein d are video camera imaging pixel bit wides, and span is that 1~100, m is that compression of images marks h S (i) in matrix F
Maximum；Buffer A first interface is connected with memory (3), for reading a line in compression of images mark matrix F
Element F (i,:), Buffer A second interface is used for the synchronous mark value f for reading current pixel and whether being dropped；Buffer
B first interface is used to store compressed images, and Buffer B second interface is connected with memory (3), for storing
The one-row pixels of compression.
The FPGA compression of images course of work of the present invention is：
Pixel clock CLK drives image compression process, sets image linage-counter Cr, sets image column pixel counter
Cc, Buffer B first interface address calculator Cd；
Described calculator Cr, Cc, Cd are register variable, and the renewal to them just comes into force in next clock cycle；
When detecting that field sync signal V is invalid, the 0th row member in compression of images mark matrix F is read from memory (3)
Plain F (0,:), the first interface through Buffer A is stored in Buffer A；
When detecting field sync signal V trailing edge, make Cr=0, Cc=0, Cd=0；
When detecting line synchronising signal H trailing edge, make Cc=0, Cd=0, cumulative Cr；
When detecting that line synchronising signal H is effective, added up Cc, and the is read in Buffer A from Buffer A second interface
Cc bit；As mark value f (Cc)=1 of reading, first interface of the current pixel through Buffer B is stored in Buffer B
Cd opening positions and cumulative Cd；As mark value f (Cc)=0 of reading, do not store, do not add up Cd；
When detecting line synchronising signal H trailing edge, the is read in compression of images mark matrix F from the memory (3)
Cr row elements F (Cr,:) Buffer A are arrived, and by a line stored in Buffer B compression image deposit memory (3).
Present invention has the advantages that：With prior art image pressure is carried out in image frequency domain (such as JPEG, H.264, H.265)
The algorithm principle of contracting is different, and the inventive method directly performs pixel and abandon or retain behaviour directly in image acquisition process
Make, realize compression of images.Directly pixel abandon operating and realize that the advantages of compressing is：It can be realized by hardware such as FPGA
With pixel clock synchronous compression, processing time is only 1 pixel clock, with the existing frequency domain method for compressing image based on image block
Compare, complexity is lower.Benefit caused by the method for compressing image of this single pixel clock is：Cost is low, low in energy consumption, as long as
Image device can be imaged, you can realize the compression of images of arbitrary resolution, arbitrary frame-rate.Therefore, the inventive method, not only may be used
For industrial camera, the compression of high-speed camera large nuber of images can be also used for.
Brief description of the drawings
Fig. 1 compression of images operation principles of the present invention
Wherein, Fig. 1 (a) is input picture, and Fig. 1 (b) is compression of images mark matrix F, and Fig. 1 (c) is that pixel abandons result,
Fig. 1 (d) is compression image, and Fig. 1 (e) is original pixels, and Fig. 1 (f) is to abandon pixel；
Fig. 2 compresses image reconstruction principle
Wherein, Fig. 2 (a) is compression image, and Fig. 2 (b) is compression of images mark matrix F, and Fig. 2 (c) is compression image rearrangement
Sequence result, Fig. 2 (d) are compression image reconstruction results, and Fig. 2 (e) is known pixels in compression image, and Fig. 2 (f) is in compression image
Unknown pixel, Fig. 2 (g) are compression image reconstruction pixels；
Fig. 3 image pixels abandon and repairing effect example
Wherein, Fig. 3 (a) input pictures, Fig. 3 (b) abandon pixel image, and Fig. 3 (c) repairs image, for ease of display, Fig. 3
(b) pixel is abandoned in and is set to 0；
Fig. 4 FPGA compression of images hardware elementary diagrams
Wherein, 1, FPGA, 2, camera image sensor, 3, memory, 4, compression of images mark matrix F, 5, compression figure
Picture, 6, Buffer A, 7, Buffer B, 8 image Compression units；
Fig. 5 compression of images timing diagrams of the present invention
Fig. 6 compression of images of the present invention and reconstructed results example
Wherein, Fig. 6 (a) input pictures, the compression ratio images of Fig. 6 (b) 99%, the compression ratio images of Fig. 6 (c) 95%, Fig. 6 (d)
90% compression image, the compression ratio image reconstruction results of Fig. 6 (e) 99%, the compression ratio image reconstruction results of Fig. 6 (f) 95%, Fig. 6 (g)
90% compression ratio image reconstruction result, for ease of display, compress and pixel is abandoned in image with 0 replacement.
Embodiment
In order that the purpose of the present invention, technical scheme and beneficial effect are more clearly understood, below in conjunction with the accompanying drawings and implement
Example, the present invention will be described in further detail.It should be noted that specific embodiment described herein is only explaining this hair
It is bright, it is not intended to limit the present invention.
Compression of images general principle proposed by the present invention is：Image is high redundancy and local height is similar, is such as schemed
Shown in 1, a width input picture (Fig. 1 (a)) is given, matrix F (Fig. 1 (b)) is marked according to compression of images, abandoned in the input image
Partial pixel (Fig. 1 (c)), then sort left to right to obtain compression image (Fig. 1 (c)) to abandoning pixel, black disk (Fig. 1 in figure
(e) it is) original pixels, white space (Fig. 1 (f)) represents that the position pixel is dropped in Fig. 1 (c).
Fig. 2 gives compression image reconstruction process：Matrix F (Fig. 2 (b)) is first marked according to compression of images, to compressing image
Pixel is resequenced in (Fig. 2 (a)), obtains the compression figure comprising known pixels (Fig. 2 (e)) and unknown pixel (Fig. 2 (f))
As reordering result (Fig. 2 (c)), further according to known pixels (Fig. 2 (e)) in compression image, using image local similarity feature,
Using local neighborhood image rebuilding method, unknown pixel (Fig. 2 (f)) value (Fig. 2 (g)) is estimated, for obtaining compression figure
As reconstruction image (Fig. 2 (d)).
Fig. 3 gives an image discarding and repairing effect example, for proving the validity of the inventive method.Such as Fig. 3
Shown, wherein Fig. 2 (a) is Lena images, image resolution ratio 512*512, and bit wide is 8bits gray level image, random drop
70% pixel in Lena images, it is dropped pixel position for ease of being shown in and is arranged to 0, obtains abandoning pixel shown in Fig. 3 (b)
Image, and the compression image of the present invention, then, picture is abandoned using known pixels compensation in pixel image (Fig. 3 (b)) is abandoned
Element, specific method are：For some discarding pixel P (i, j), (i, j) is image coordinate, s*s sizes is taken centered on (i, j)
Neighborhood, in neighborhood, all known pixels are found out, and calculate the intermediate value of these known pixels, as discarding pixel P's (i, j)
Estimate, and it is filled into (i, the j) opening position for abandoning image.Fig. 3 (c) is to use the big small neighbourhood repairing effect figures of 3*3.From reparation
As a result as can be seen that proposed by the present invention realize that the method for image Fast Compression is feasible by abandoning partial pixel.
Fig. 6 gives the compression of images result in the case of 90%, 95%, 99% compression ratio, and uses the big small neighbourhoods of 9*9
Reconstructed results.As can be seen that the inventive method can well reconstruct original image in 90% compression ratio.
The generation method of compression of images mark matrix F of the present invention includes：
Method 1：
It is 0 or 1 to manually set element in F.
Method 2：
Element F (i, j)=b (r) in compression of images matrix is generated using bi-distribution b (), wherein, r is bi-distribution letter
Several input parameters, r are the probability that Binomial Distributing Function b () output valve is 1.
It is compared with method 1, the advantages of method 2：Element value in the F generated by bi-distribution random function, in image
In more uniformly spread, be advantageous to lifting compression image reconstruction effect.And it is possible to the value by adjusting input parameter r, real
Existing image compression ratio adjustment.
Method 3：
First using method 2 generate compression of images matrix F, and judge row vector F in F (i,:) in element sum S (i) whether
It is equal, if unequal, the average M of all row vector element sum S (i) is calculated, and M is rounded, obtain M'；Pass through hand again
Dynamic method of adjustment, change element value in row vector, make in F that element sum is equal to M' in all row vectors.
FPGA of the present invention carries out compression of images hardware configuration principle as shown in figure 4, FPGA (1) and video camera image sensing
Device (2) is directly connected to, imaging sensor (2) output field sync signal V, line synchronising signal H, pixel clock CLK, pixel data D；
FPGA (1) is connected with memory (3), and memory (3) is used for storage image compact token matrix (4) and compression image (5)；FPGA
There are two twoport Block RAM cachings inside：Buffer A (6) and Buffer B (7)；Wherein Buffer A are used for cache image
A row element in compact token matrix F, Buffer B are used to cache the one-row pixels after collection compression of images；Buffer A's
First interface is connected with memory (3), for read compression of images mark matrix F in a row element, the second of Buffer A
Individual interface is used for the synchronous mark value for reading current pixel and whether being dropped；Buffer B first interface, which is used to store, to be compressed
Image afterwards, Buffer B second interface are connected with memory (3), for storing compressed a line image pixel；FPGA
On there is image Compression unit (8) to be used for compression of images.
The workflow of image Compression unit (8) is as follows：
Pixel clock CLK drives image compression process, sets image linage-counter Cr, sets image column pixel counter
Cc, Buffer B first interface address calculator Cd；
Described calculator Cr, Cc, Cd are register variable, are just updated in next clock cycle；
When detecting that field sync signal V is invalid, the 0th row member in compression of images mark matrix F is read from memory (3)
Plain F (0,:), the first interface through Buffer A is stored in Buffer A；
When detecting field sync signal V rising edge and trailing edge, make Cr=0, Cc=0, Cd=0；
When detecting line synchronising signal H trailing edge, make Cr=Cr+1；
When detecting that line synchronising signal H is effective, added up Cc, and the is read in Buffer A from Buffer A second interface
Cc bit；When readout is 1, first interface of the current pixel through Buffer B is stored in Cd opening positions in Buffer B, simultaneously
Cumulative Cd；When readout is 0, do not store, Cd does not add up；
When detecting line synchronising signal H trailing edge, the is read in compression of images mark matrix F from the memory (3)
Cr row elements F (Cr,:) Buffer A are arrived, and by a line stored in Buffer B compression image deposit memory (3).
Fig. 5 gives the timing diagram of the inventive method, and wherein field sync signal V, line synchronising signal H are that high level has
Effect, the second interface that compact token value f is Buffer A read value signal；When compact token value is high, samples and preserve and work as
Preceding pixel value D, when compact token value is low, does not sample and do not preserve current pixel value D, thus can realize synchronous with pixel clock
Compression of images, and then realize large nuber of images Real Time Compression.
Claims (7)
- A kind of 1. video camera large nuber of images compression method based on FPGA, it is characterised in that：FPGA (1) and video camera image pass Sensor (2) is directly connected to, imaging sensor (2) output field sync signal V, line synchronising signal H, pixel clock CLK, pixel data D；FPGA (1) is connected with memory (3), has compression of images mark matrix F in memory (3), F dimension is w*h, wherein w It is to gather picture traverse, h to gather picture altitude, w, h span are that element value is 0 or 1 in 1~100000, F； FPGA (1) drives clock using pixel clock CLK as compression of images, according to field sync signal V, line synchronising signal H, to inputting picture Prime number gauge number, and thus calculate current pixel P image coordinate (i, j), i span are 0~w-1, j span For 0~h-1；FPGA (1) reads compression of images in memory (3) and marks (i, j) individual element in matrix F：F (i, j), when F (i, When j)=0, current pixel P is not sampled, as F (i, j)=1, samples current pixel P, and the origin coordinates of element is in wherein F (0,0)；After a line compression of images is completed, in current line compression image deposit memory (3)；It is sequentially completed h row image slices Element compression, obtain compressing image；The memory (3) includes FLASH, DDR, SD storage chip.
- 2. according to claim 1, element F (i, j) value is random in compression of images mark matrix F.
- 3. according to claim 1 and 2, element F (i, j) value meets bi-distribution in compression of images mark matrix F：F (i, j)=b (r) (1)Wherein, b is Binomial Distributing Function, and r is the probability that Binomial Distributing Function output valve is equal to 1, and r spans are 0~1；Figure Picture compression ratio is equal with bi-distribution b () input parameter r, and image compression ratio is adjusted by adjusting r.
- 4. according to claim 1, make all row vector F in compression of images mark matrix F (i,:) interior element sum S (i) is equal, To ensure that pixel quantity is equal in compression image per a line, wherein, F (i,:) be in the rows of F i-th all elements form vector, i Span be 0~h-1.
- 5. according to Claims 1 to 4, when h S (i) is unequal in the compression of images mark matrix F of bi-distribution generation, h is taken The average M of individual S (i), and M' is obtained to M round numbers；Manual modification compression of images mark matrix F in row vector F (i,:) in member Element, make all S (i)=M' in F；During repairing changes, the element of modification be dispersed evenly to row vector F (i,:) in.
- 6. according to Claims 1 to 5,2 twoport Block RAM are set to cache on FPGA：Buffer A, Buffer B, its Middle Buffer A are used for a row element in cache image compact token matrix F：F(i,:), Buffer B are used to cache collection image One-row pixels after compression；Buffer A size is：w bits；Buffer B size is m*w*d bits, and wherein d is to take the photograph Camera imaging pixel bit wide, span are that 1~100, m is the maximum that compression of images marks h S (i) in matrix F； Buffer A first interface is connected with memory (3), for reading a row element F in compression of images mark matrix F (i,:), Buffer A second interface is used for the synchronous mark value f for reading current pixel and whether being dropped；Buffer B's First interface is used to store compressed images, and Buffer B second interface is connected with memory (3), is compressed for storing One-row pixels.
- 7. it is according to claim 1 and 6, FPGA the compression of images course of work：Pixel clock CLK drives image compression process, set image linage-counter Cr, set image column pixel counter Cc, Buffer B first interface address calculator Cd；Described calculator Cr, Cc, Cd are register variable, and the renewal to them just comes into force in next clock cycle；When detecting that field sync signal V is invalid, the 0th row element F in compression of images mark matrix F is read from memory (3) (0,:), the first interface through Buffer A is stored in Buffer A；When detecting field sync signal V trailing edge, make Cr=0, Cc=0, Cd=0；When detecting line synchronising signal H trailing edge, make Cc=0, Cd=0, cumulative Cr；When detecting that line synchronising signal H is effective, added up Cc, and Cc are read in Buffer A from Buffer A second interface bit；As mark value f (Cc)=1 of reading, first interface of the current pixel through Buffer B is stored in Cd positions in Buffer B Put the Cd that locates and add up；As mark value f (Cc)=0 of reading, do not store, do not add up Cd；When detecting line synchronising signal H trailing edge, Cr rows in compression of images mark matrix F are read from memory (3) Element F (Cr,:) Buffer A are arrived, and by a line stored in Buffer B compression image deposit memory (3).
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Application publication date: 20171222 |