CN107453823B - Single body test system and method for optical fiber distributed repeater - Google Patents
Single body test system and method for optical fiber distributed repeater Download PDFInfo
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- CN107453823B CN107453823B CN201710641603.3A CN201710641603A CN107453823B CN 107453823 B CN107453823 B CN 107453823B CN 201710641603 A CN201710641603 A CN 201710641603A CN 107453823 B CN107453823 B CN 107453823B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract
The invention belongs to the technical field of repeater test, and discloses a single body test system and a single body test method of an optical fiber distributed repeater, wherein the system comprises the following steps: the system comprises an FPGA module, a CPU module, a clock module, an Ethernet physical layer chip PHY, a FLASH memory and a DDR module; in the method, a single testing system is connected with a computer through a network port, the single testing system is connected with tested equipment through an optical port, and the tested equipment is a near-end machine or a far-end machine of the optical fiber distributed repeater. The invention solves the problems of low testing efficiency and high testing cost of the repeater in the prior art, and achieves the technical effects of improving the testing efficiency of the repeater and reducing the testing cost.
Description
Technical Field
The invention relates to the technical field of repeater test, in particular to a single body test system and a single body test method of an optical fiber distributed repeater.
Background
With the development of wireless communication, repeaters become important components of mobile communication signal coverage systems. The optical fiber distributed repeater is a repeater for signal transmission by means of optical fibers, and has the characteristics of low transmission loss, convenience in wiring and suitability for long-distance transmission. For villages, towns, tourist areas, roads and the like which can not receive base station signals, the signal coverage can be effectively realized by using the optical fiber distributed repeater; for large high-rise regional buildings (groups), cells and the like with higher requirements, the optical fiber distributed repeater can effectively solve the existing signal coverage problem.
The optical fiber distributed repeater mainly comprises an optical near-end machine, an optical fiber and an optical far-end machine (covering unit). In the conventional testing of the optical fiber distributed repeater, as shown in fig. 1 and fig. 2, the repeater complete machine connected by the near-end machine, the optical fiber and the far-end machine is used as a test object, a signal source is adopted to generate a signal, the signal is received by a frequency spectrograph after passing through the repeater complete machine, and then the signal is analyzed, so that various indexes of the repeater complete machine are tested.
In practice, there is also usually an expansion unit connected between the near-end unit and the far-end unit, so that one near-end unit can transmit signals to a large number of far-end units. Therefore, in the conventional test of the optical fiber distributed repeater, particularly in batch production, a large number of signal sources and frequency spectrometers are needed to ensure the accuracy and consistency of indexes of factory test equipment, and the test cost is high; in actual application, the product form is usually the condition that one near-end machine corresponds to a large number of far-end machines, which results in that the number of the far-end machines actually produced is far more than that of the near-end machines, and therefore, taking the repeater complete machine connected by the near-end machine, the optical fiber and the far-end machine as a test object results in low test efficiency and high test cost.
Disclosure of Invention
The embodiment of the application provides a single testing system and a single testing method for an optical fiber distributed repeater, and solves the problems of low testing efficiency and high testing cost of the repeater in the prior art.
The embodiment of the application provides a monomer test system of an optical fiber distributed repeater, which comprises: the system comprises an FPGA module, a CPU module, a clock module, an Ethernet physical layer chip PHY, a FLASH memory and a DDR module;
the FPGA module is respectively connected with the CPU module, the clock module and the DDR module, and is connected with an optical port through a Serdes interface; the CPU module is connected with the Ethernet physical layer chip PHY and the FLASH memory; the Ethernet physical layer chip PHY is connected with the clock module and the network port.
Preferably, the DDR module includes a first DDR chip and a second DDR chip, the first DDR chip is configured to store data in a transmission direction, and the second DDR chip is configured to store data in a reception direction.
Preferably, the clock module has a first reference clock and a second reference clock, the first reference clock is a local crystal oscillator, and the second reference clock is provided for the FPGA module; the clock module outputs a system clock to the FPGA module, and the clock module outputs a PHY reference clock to the Ethernet physical layer chip PHY.
On the other hand, the embodiment of the application provides a single testing method of an optical fiber distributed repeater, wherein a single testing system is connected with a computer through a network port, the single testing system is connected with tested equipment through an optical port, and the tested equipment is a near-end machine or a far-end machine of the optical fiber distributed repeater.
Preferably, in the downlink test, the single test system sends a signal to the tested equipment, and the tested equipment is connected with the frequency spectrograph through the radio frequency port; the signal is one of a single tone signal, a double tone signal, a sweep frequency signal and a modulation signal;
the single tone signal and the sweep frequency signal are generated by a digital control oscillator NCO in the FPGA module; the diphone signal is formed by generating an image on the basis of the monophonic signal; the modulation signal is a waveform file, the waveform file is stored in a FLASH memory, a CPU module extracts the waveform file and transmits the waveform file to the FPGA module, and the FPGA module receives the waveform file, writes the waveform file into a first DDR chip for storage, and reads the waveform file after the storage is finished.
Preferably, the FPGA module performs power adjustment on the signals, selects one of the signals to be transmitted into the Cpri framing module for framing according to the monitoring information, and transmits the signal to the optical port through the Serdes interface.
Preferably, in the uplink test, the signal source is connected with the tested device through the radio frequency port, and the single test system receives data of the tested device.
Preferably, the FPGA module performs Cpri deframing on the data to obtain signal data; and the FPGA module carries out power detection on the signal data and transmits the detected signal power to the CPU module in the form of monitoring information.
Preferably, the FPGA module writes the signal data into a second DDR chip for storage, and reads out the signal data after storage is completed, and transmits the signal data to the CPU module.
Preferably, the CPU module transmits the signal data to a computer through a PHY chip, and performs index calculation on the signal data through Matlab.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
in the embodiment of the application, a single testing system of an optical fiber distributed repeater is provided, which comprises an FPGA module, a CPU module, a clock module, an Ethernet physical layer chip PHY, a FLASH memory and a DDR module, and the single testing system of the optical fiber distributed repeater is used for testing a near-end machine or a far-end machine. A single testing system is adopted to replace a signal source to send signals, and the signals are sent to the tested equipment through an optical port; and the single testing system is adopted to replace a frequency spectrograph to receive signals, and the signals from the tested equipment are transmitted to the single testing system through the optical port. The signal transmission and reception between the single testing system and the tested equipment are through the optical ports, so that the near-end machine and the far-end machine of the optical fiber distributed repeater are separately and independently tested, the testing efficiency of the repeater is effectively improved, and the testing cost is reduced.
Drawings
In order to more clearly illustrate the technical solution of the present embodiment, the drawings needed to be used in the description of the embodiment will be briefly introduced below, and it is obvious that the drawings in the following description are one embodiment of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a block diagram of a downlink test of a conventional optical fiber distributed repeater;
FIG. 2 is a block diagram of a conventional uplink test of a complete optical fiber distributed repeater;
FIG. 3 is a block diagram of a single testing system of an optical fiber distributed repeater according to an embodiment of the present invention;
FIG. 4 is a block diagram of a single testing system for an optical fiber distributed repeater according to an embodiment of the present invention for performing uplink and downlink tests on a remote terminal;
FIG. 5 is a block diagram of an uplink and downlink test of a near-end unit by using the single testing system of an optical fiber distributed repeater according to an embodiment of the present invention;
FIG. 6 is a FPGA transmit direction block diagram;
fig. 7 is an FPGA receive direction block diagram.
Detailed Description
The embodiment of the application provides a single testing system and a single testing method for an optical fiber distributed repeater, and solves the problems of low testing efficiency and high testing cost of the repeater in the prior art.
In order to solve the technical problems, the general idea of the embodiment of the application is as follows:
a single testing system of an optical fiber distributed repeater comprises: the system comprises an FPGA module, a CPU module, a clock module, an Ethernet physical layer chip PHY, a FLASH memory and a DDR module;
the FPGA module is respectively connected with the CPU module, the clock module and the DDR module, and is connected with an optical port through a Serdes interface; the CPU module is connected with the Ethernet physical layer chip PHY and the FLASH memory; the Ethernet physical layer chip PHY is connected with the clock module and the network port.
On the other hand, the single testing method of the optical fiber distributed repeater comprises the steps that a single testing system is connected with a computer through a network port, the single testing system is connected with tested equipment through an optical port, and the tested equipment is a near-end machine or a far-end machine of the optical fiber distributed repeater.
The invention provides a single testing system of an optical fiber distributed repeater, which comprises an FPGA module, a CPU module, a clock module, an Ethernet physical layer chip PHY, a FLASH memory and a DDR module. A single testing system is adopted to replace a signal source to send signals, and the signals are sent to the tested equipment through an optical port; and the single testing system is adopted to replace a frequency spectrograph to receive signals, and the signals from the tested equipment are transmitted to the single testing system through the optical port. The signal transmission and reception between the single testing system and the tested equipment are through the optical ports, so that the near-end machine and the far-end machine of the optical fiber distributed repeater are separately and independently tested, the testing efficiency of the repeater is effectively improved, and the testing cost is reduced.
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
The embodiment provides a single testing system of an optical fiber distributed repeater, as shown in fig. 3, including: the system comprises an FPGA module, a CPU module, a clock module, an Ethernet physical layer chip PHY, a FLASH memory and a DDR module.
The FPGA module is respectively connected with the CPU module, the clock module and the DDR module, and is connected with an optical port through a Serdes interface; the CPU module is connected with the Ethernet physical layer chip PHY and the FLASH memory; the Ethernet physical layer chip PHY is connected with the clock module and the network port.
The DDR module comprises a first DDR chip and a second DDR chip, wherein the first DDR chip is used for storing data in a sending direction, and the second DDR chip is used for storing data in a receiving direction.
The clock module is provided with a first reference clock and a second reference clock, the first reference clock is a local crystal oscillator, and the second reference clock is provided for the FPGA module; the clock module outputs a system clock to the FPGA module, and the clock module outputs a PHY reference clock to the Ethernet physical layer chip PHY.
Specifically, the connection relationship of the single testing system of the optical fiber distributed repeater is as follows:
the FPGA module is connected with the read-write interfaces of the first DDR chip and the second DDR chip, is connected with the CPU module through the spi interface, outputs a clock serving as a second reference clock of the clock module, and is provided with a serdes interface to be connected to an optical port of the system.
The CPU module is connected with the FPGA module through an spi interface and is connected with the Ethernet physical layer chip PHY through an mii interface.
The FLASH memory is connected with the CPU module and is used as the file storage device of the CPU module.
The clock module is provided with a local crystal oscillator as a first reference clock, the second reference clock is provided for the FPGA module, and the clock module outputs a clock to the FPGA module and the Ethernet physical layer chip PHY.
The Ethernet physical layer chip PHY is connected with the CPU module through an mii interface, and the other end of the Ethernet physical layer chip PHY is connected with the network port.
The first DDR chip and the second DDR chip are both connected with the FPGA module.
The function of each module is as follows:
the FPGA module is used as the core of the system, single tone, double tone, frequency sweep and signal modulation are created in the sending direction, and finally the signals are sent to an optical port through cpri framing through a serdes interface, and data are transmitted to the tested equipment through optical fibers. The modulation signal is used for judging the bandwidth of the CPU and transmitting a corresponding waveform file to the FPGA module, the FPGA module transmits the waveform file data to the first DDR chip for storage, and the data are circularly read out and sent after the storage is finished. In the receiving direction, data transmitted by the tested equipment is received through the optical port, signal data is obtained through cpri frame decoding, power detection is carried out, the data is written into the second DDR chip for storage, and then the data is read out and sent to the CPU module.
And the CPU module calls a corresponding waveform file from the FLASH memory to transmit to the FPGA module through judging the bandwidth set by the system in the transmitting direction. In the receiving direction, the signal data transmitted by the FPGA module is packaged, finally transmitted to the network port through the mii interface and the PHY chip, transmitted to the computer through the network port, and the error vector magnitude evm and the sensitivity index of the data are calculated on the computer through Matlab software.
The FLASH memory is used for storing files required by the CPU module, including system codes, waveform files and configuration tool files.
The clock module has two reference clocks, one is a local crystal oscillator, and the other is provided for the FPGA module. When testing the far-end machine of the optical fiber distributed repeater, because the system clock of the far-end machine is recovered from the optical port data, the system is used as a source of a synchronous clock, a local clock is selected as a clock chip as a reference, and the system clock required by the FPGA module and the Ethernet physical layer chip PHY is output. When the near-end machine of the optical fiber distributed repeater is tested, the local clock is used by the near-end machine, so that the system needs to recover the clock from the optical port because the clock synchronization is needed, the FPGA module recovers the clock from the servers data and outputs the clock to the clock chip as a second reference, and the clock chip selects the clock provided by the FPGA module as the reference to output the system clock.
The ethernet physical layer chip PHY transmits the ethernet data transmitted from the CPU mii to the computer through the network port, and the network port also undertakes the interaction of monitoring data between the computer and the CPU.
The first DDR chip is used for storing a waveform file in a sending direction, and the second DDR chip is used for storing data in a receiving direction.
The embodiment provides a single testing method of an optical fiber distributed repeater, as shown in fig. 4 and 5, a single testing system is connected with a computer through a network port, the single testing system is connected with tested equipment through an optical port, and the tested equipment is a near-end machine or a far-end machine of the optical fiber distributed repeater.
In the downlink test, the single test system sends a signal to the tested equipment, and the tested equipment is connected with the frequency spectrograph through the radio frequency port. In the uplink test, a signal source is connected with the tested equipment through a radio frequency port, and the single test system receives the data of the tested equipment.
Specifically, in the downlink test, the signal sent by the single testing system is one of a single tone signal, a double tone signal, a frequency sweep signal and a modulation signal; the single tone signal and the sweep frequency signal are generated by a digital control oscillator NCO in the FPGA module; the diphone signal is formed by generating an image on the basis of the monophonic signal; the modulation signal is a waveform file, the waveform file is stored in a FLASH memory, a CPU module extracts the waveform file and transmits the waveform file to the FPGA module, and the FPGA module receives the waveform file, writes the waveform file into a first DDR chip for storage, and reads the waveform file after the storage is finished.
The FPGA module is used for adjusting the power of the signals, selecting one of the signals according to monitoring information, transmitting the selected signal into the Cpri framing module for framing, and transmitting the signal to an optical port through a Serdes interface.
The transmission direction link, as shown in fig. 6:
1. the transmitting direction is to the near-end machine or far-end machine of the detected optical fiber distributed repeater, and the data is transmitted to the detected equipment from the optical port.
2. The transmitted signals are single tone signals, double tone signals, frequency sweep signals and modulation signals.
3. The single-tone signal is generated inside the FPGA and is realized by using NCO inside the FPGA, and the frequency offset of the single-tone signal can be controlled by controlling a control word of the NCO.
4. The double-tone signal is delayed on the basis of the single-tone signal to form a phase difference, an image of the signal is created to form the double-tone signal, the frequency deviation of the double-tone signal is also controlled by a control word of the NCO, after the double-tone signal is formed, the frequency mixing is carried out through another NCO, the deviation of a central frequency point can be completed, and the deviation of the central frequency point of the double-tone signal is controlled by the control word of the other NCO. The two-tone signal is mainly used for testing the signal intermodulation index of the equipment.
5. The frequency sweep signal is generated by the NCO as the single tone signal, and the moving single tone signal is formed by controlling the increment of the NCO control word, namely the frequency sweep signal.
6. The modulation signal is a waveform file, the waveform file is stored in FLASH of the system according to different bandwidth requirements, the CPU judges that the system sets bandwidth, extracts the corresponding waveform file and transmits the waveform file to the FPGA through an spi interface, the FPGA writes the waveform file into DDR storage in the sending direction after receiving the signal, and the signal is read out from DDR internal circulation after the storage is finished.
7. The power of the 4 signals is adjusted in the FPGA, the power is controllable through a multiplier and bit cutting operation, and the power control is controlled by the coefficient of the multiplier.
8. The type of a sending signal set by a decision making system in the FPGA is any one of a single tone, a double tone, a frequency sweep and a modulation signal, the corresponding signal is transmitted into a cppri framing module to be framed, and an optical port is transmitted out through serdes.
9. The SPI interface of the FPGA and the CPU not only serves as a data transmission channel, but also serves as a monitoring information channel, and the CPU can control various control information inside the FPGA through the SPI interface, including signal type selection, signal power setting, signal bandwidth, single-tone signal frequency offset, double-tone signal center frequency offset, frequency sweep stepping and other monitoring information.
The operation of partial monitoring quantity in the single test system is completed by a computer, such as the type of the transmitted signal, the power of the transmitted signal and the bandwidth of the transmitted signal.
Specifically, in the uplink test, the single test system receives data of the tested equipment, and the FPGA module performs Cpri deframing on the data to obtain signal data; and the FPGA module carries out power detection on the signal data and transmits the detected signal power to the CPU module in the form of monitoring information.
And the FPGA module writes the signal data into a second DDR chip for storage, reads out the signal data after storage is finished, and transmits the signal data to the CPU module.
And the CPU module transmits the signal data to a computer through a PHY chip, and index calculation is carried out on the signal data through Matlab.
Receive direction link, as shown in fig. 7:
1. the receiving direction is for the near-end machine or far-end machine of the measured optical fiber distributed repeater, and the data of the measured equipment is received from the optical port.
2. And carrying out cpri frame decoding operation on the received optical port data in the FPGA to obtain pure signal data.
3. And carrying out power detection on the signal data in the FPGA, and transmitting the detected power to the CPU through spi in the form of monitoring information for calculating the power gain of the equipment.
4. And writing the received signal data into the DDR in the receiving direction, and then reading the signal data and transmitting the read signal data to the CPU through an spi interface. Because the optical interface signal is clocked quickly and the spi interface is slow, it needs to be dumped via DDR.
5. The CPU receives the signal data, frames the signal data through Ethernet, transmits the signal data into the PHY chip through an mii interface, and finally transmits the signal data to a computer through a network interface.
6. Evm and sensitivity index calculation are carried out on the signal data through Matlab on the computer, and the computer can control the monitoring quantity of the single testing system while calculating.
The single testing system of the optical fiber distributed repeater provided by the embodiment of the invention at least comprises the following technical effects:
in the embodiment of the application, a single testing system of an optical fiber distributed repeater is provided, which comprises an FPGA module, a CPU module, a clock module, an Ethernet physical layer chip PHY, a FLASH memory and a DDR module, and the single testing system of the optical fiber distributed repeater is used for testing a near-end machine or a far-end machine. A single testing system is adopted to replace a signal source to send signals, and the signals are sent to the tested equipment through an optical port; and the single testing system is adopted to replace a frequency spectrograph to receive signals, and the signals from the tested equipment are transmitted to the single testing system through the optical port. The signal transmission and reception between the single testing system and the tested equipment are through the optical ports, so that the near-end machine and the far-end machine of the optical fiber distributed repeater are separately and independently tested, the testing efficiency of the repeater is effectively improved, and the testing cost is reduced.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (10)
1. A monomer test system of an optical fiber distributed repeater is characterized by comprising: the system comprises an FPGA module, a CPU module, a clock module, an Ethernet physical layer chip PHY, a FLASH memory and a DDR module;
the FPGA module is respectively connected with the CPU module, the clock module and the DDR module, and is connected with an optical port through a Serdes interface; the CPU module is connected with the Ethernet physical layer chip PHY and the FLASH memory; the Ethernet physical layer chip PHY is connected with the clock module and the network port;
the FPGA module is used for creating single tone, double tone, frequency sweep and modulation signals in the sending direction, finally sending the signals to an optical port through cpri framing through a Serdes interface, and transmitting data to the tested equipment through optical fibers; the CPU module is used for receiving data transmitted by the tested equipment through an optical port in a receiving direction, obtaining signal data through cpri de-framing, carrying out power detection, writing the data into the DDR module for storage, and then reading and transmitting the data to the CPU module;
the CPU module is used for calling out a corresponding waveform file from the FLASH memory to be transmitted to the FPGA module through judging the bandwidth set by the system in the transmitting direction; and the FPGA module is used for packaging the signal data transmitted by the FPGA module in the receiving direction and finally transmitting the signal data to the network port through an mii interface and the Ethernet physical layer chip PHY.
2. The monomer test system of the optical fiber distributed repeater according to claim 1, wherein the DDR module comprises a first DDR chip and a second DDR chip, the first DDR chip is used for storing data in a transmission direction, and the second DDR chip is used for storing data in a reception direction.
3. The monomer test system of the optical fiber distributed repeater according to claim 1, wherein the clock module has a first reference clock and a second reference clock, the first reference clock is a local crystal oscillator, and the second reference clock is provided for the FPGA module; the clock module outputs a system clock to the FPGA module, and the clock module outputs a PHY reference clock to the Ethernet physical layer chip PHY.
4. A single testing method of an optical fiber distributed repeater is characterized in that a single testing system of the optical fiber distributed repeater as claimed in any one of claims 1 to 3 is adopted, the single testing system is connected with a computer through a network port, the single testing system is connected with tested equipment through an optical port, and the tested equipment is a near-end machine or a far-end machine of the optical fiber distributed repeater.
5. The monomer test method of the optical fiber distributed repeater according to claim 4, wherein in a downlink test, the monomer test system sends a signal to the tested equipment, and the tested equipment is connected with a frequency spectrograph through a radio frequency port; the signal is one of a single tone signal, a double tone signal, a sweep frequency signal and a modulation signal;
the single tone signal and the sweep frequency signal are generated by a digital control oscillator NCO in the FPGA module; the diphone signal is formed by generating an image on the basis of the monophonic signal; the modulation signal is a waveform file, the waveform file is stored in a FLASH memory, a CPU module extracts the waveform file and transmits the waveform file to the FPGA module, and the FPGA module receives the waveform file, writes the waveform file into a first DDR chip for storage, and reads the waveform file after the storage is finished.
6. The method of claim 5, wherein the FPGA module adjusts power of the signals, selects one of the signals according to the monitoring information, transmits the selected signal to the Cpri framing module for framing, and transmits the framing to the optical port through the Serdes interface.
7. The monomer test method of the optical fiber distributed repeater according to claim 4, wherein in the uplink test, the signal source is connected with the tested device through the radio frequency port, and the monomer test system receives the data of the tested device.
8. The method for testing the monomers of the optical fiber distributed repeater according to claim 7, wherein the FPGA module performs Cpri deframing on the data to obtain signal data; and the FPGA module carries out power detection on the signal data and transmits the detected signal power to the CPU module in the form of monitoring information.
9. The method of claim 8, wherein the FPGA module writes the signal data into a second DDR chip for storage, reads the signal data after storage, and transmits the signal data to the CPU module.
10. The method of claim 9, wherein the CPU module transmits the signal data to a computer via a PHY chip, and performs index calculation on the signal data via Matlab.
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| CN110022356B (en) * | 2019-03-08 | 2021-11-30 | 北京三快在线科技有限公司 | Distributed system and unmanned equipment with same |
| CN115913373A (en) * | 2022-11-03 | 2023-04-04 | 四川天邑康和通信股份有限公司 | Input signal frequency spectrum detection method of digital optical fiber repeater |
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