CN107452349B - Drive circuit and liquid crystal display device - Google Patents
Drive circuit and liquid crystal display device Download PDFInfo
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- CN107452349B CN107452349B CN201710698828.2A CN201710698828A CN107452349B CN 107452349 B CN107452349 B CN 107452349B CN 201710698828 A CN201710698828 A CN 201710698828A CN 107452349 B CN107452349 B CN 107452349B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a driving circuit and a liquid crystal display device, wherein the driving circuit is provided with a time controller, a grid driving circuit and a source driving circuit; when the power-saving display mode is started, the gate driving signals output by each gate driving unit in the same sub-gate driving circuit are the same, and the switching frequency of the source driving signals output by the source driving circuit is m times of that of the color mode, so that the output signals of the gate driving circuit and the source driving circuit are changed, the power consumption can be effectively saved, and the display picture can be switched from the color mode to the black-and-white mode.
Description
Technical Field
The invention relates to the technical field of display, in particular to a driving circuit and a liquid crystal display device.
Background
A Liquid Crystal Display (LCD) has the advantages of good picture quality, small size, light weight, low driving voltage, low power consumption, no radiation, and relatively low manufacturing cost, and is currently dominant in the field of flat panel displays. With the development and progress of liquid crystal display technology, people have made higher demands on the characteristics of liquid crystal display, such as display quality, appearance design, high resolution, low power consumption, etc.
Fig. 1 is a schematic diagram of a partial equivalent circuit structure of a conventional liquid crystal display device. The liquid crystal display device comprises a display panel and a driving circuit. The display panel includes a plurality of pixel units, each including a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The basic working principle of the liquid crystal display panel and the driving circuit is as follows: the gate driving circuit sends a gate driving signal Gn (only G1, G2, G3 are shown in fig. 1) to the scan lines through pull-up transistors electrically connected to the scan lines to sequentially turn on Thin Film Transistors (TFTs) of each row, and sends a data signal Dn (only D1, D2, D3 are shown in fig. 1) to the data lines through the source driving circuit, thereby simultaneously charging the pixel cells of an entire row to respective required voltages to display different gray scales. That is, the thin film transistor of the first row is first turned on by the gate driving circuit of the first row through the pull-up transistor thereof, and then the sub-pixels of the first row are charged by the source driving circuit. When the pixel units in the first row are charged, the grid driving circuit turns off the thin film transistors in the row, then the grid driving circuit in the second row turns on the thin film transistors in the second row through the pull-up transistors of the grid driving circuit in the second row, and the source driving circuit charges and discharges the sub-pixels in the second row. In this sequence, when the pixel cells in the last row are charged, the charging is started again from the first row.
When a picture is displayed, each pixel is scanned line by line, and the output signal frequency of each row of grid driving circuit is matched with that of each column of source driving circuit. However, no matter what picture mode is displayed, the power consumption of the display device is always unchanged, and the requirement of people for low power consumption of the liquid crystal display cannot be met.
Disclosure of Invention
Accordingly, the present invention is directed to a driving circuit and a liquid crystal display device to solve the requirement of low power consumption of the liquid crystal display.
Specifically, the driving circuit provided by the invention is used for driving a display panel and comprises a time schedule controller, a grid driving circuit and a source driving circuit; the time sequence controller is used for outputting a grid time sequence signal to the grid driving circuit and outputting a source time sequence signal to the source driving circuit; the grid driving circuit comprises a plurality of sub-grid driving circuits which are sequentially arranged, each sub-grid driving circuit comprises m grid driving units, and each stage of grid driving unit is used for outputting a stage of grid driving signal to a corresponding sub-pixel according to the grid time sequence signal; the source driving circuit is used for generating a source driving signal according to a source time sequence signal input by the time sequence controller; when in the power-saving display mode, the gate driving signals output by each gate driving unit in the same sub-gate driving circuit are the same, and the number of times of switching the source driving signals output by the source driving circuit is m times of that of the color mode.
In one embodiment of the present invention, each sub-gate driving circuit includes m gate driving units, where m is equal to 3 or 4.
In an embodiment of the invention, in the power saving display mode, the frequency of the gate driving signal output by the sub-gate driving circuit is the same as the frequency in the color mode, and the frequency of the source driving signal output by the source driving circuit is m times of the frequency in the color mode.
In one embodiment of the present invention, the sub-pixels corresponding to the sub-gate driving circuits include red, green, and blue sub-pixels.
In one embodiment of the present invention, the sub-pixels corresponding to the sub-gate driving circuits include red, green, blue and white sub-pixels.
In an embodiment of the invention, all the sub-pixels of each pixel unit are located in the same row, and the arrangement manner of the sub-pixels of each pixel unit is the same.
In one embodiment of the present invention, the timing controller receives a mode switching command, and outputs a corresponding gate timing signal according to the mode switching command, where the command is input by a user through an input device.
In an embodiment of the invention, in the power-saving display mode, the gate timing signals output by the timing controller to each gate driving unit in the same sub-gate driving circuit are the same.
In one embodiment of the present invention, the gate driving unit includes: the first switch element comprises a first path end, a second path end and a first control end, wherein the first control end receives a first pulse signal, and the first path end receives a reference high voltage; a second switching element including a third path terminal, a fourth path terminal, and a second control terminal, the second control terminal receiving the second pulse signal, the fourth path terminal receiving the reference high voltage; a third switching element including a fifth path terminal, a sixth path terminal and a third control terminal, wherein the fifth path terminal is connected to the first gate timing signal, the sixth path terminal outputs the present-stage gate driving signal, and the third control terminal is connected to the second path terminal of the first switching element and the third path terminal of the second switching element; a fourth switching element including a seventh path terminal, an eighth path terminal, and a fourth control terminal, wherein the seventh path terminal is connected to the sixth path terminal of the third switching element, the eighth path terminal receives the reference low voltage, and the fourth control terminal is connected to the fourth gate timing signal; the first pulse signal is an upper three-stage grid timing signal output by a grid driving unit with an upward difference of three stages except for a front three-stage grid driving unit; except the last three-stage grid driving unit, the second pulse signal is a lower three-stage grid timing signal output by the grid driving unit with a downward phase difference of three stages.
The invention also provides a liquid crystal display device which comprises the drive circuit and the display panel.
When the driving circuit and the liquid crystal display device of the invention start the power-saving display mode, the gate driving signals output by each gate driving unit in the same sub-gate driving circuit are the same, and the switching frequency of the source driving signals output by the source driving circuit is one m times of that of the color mode, thus changing the output signals of the gate driving circuit and the source driving circuit, effectively saving power consumption and realizing the switching of the display picture from the color mode to the black and white mode.
Drawings
Fig. 1 is a schematic diagram of a partial equivalent circuit structure of a conventional liquid crystal display device.
Fig. 2 is a schematic structural diagram of a driving circuit according to a first embodiment of the invention.
Fig. 3 is a circuit diagram of a gate driving unit according to a first embodiment of the invention.
Fig. 4 is a schematic structural diagram of a gate driving circuit according to a first embodiment of the invention.
Fig. 5 is a timing diagram of gate timing signals output by the timing controller in the color mode according to the first embodiment of the present invention.
Fig. 6 is a timing diagram of gate timing signals output by the timing controller in the power-saving display mode according to the first embodiment of the invention.
FIG. 7 is a timing diagram of the gate driving signals and the source driving signals outputted by the driving circuit in the color mode according to the first embodiment of the invention.
Fig. 8 is a timing diagram of the gate driving signal and the source driving signal outputted by the driving circuit in the power-saving display mode according to the first embodiment of the invention.
Fig. 9 is a schematic structural diagram of a driving circuit according to a second embodiment of the invention.
Fig. 10 is a circuit diagram of a gate driving unit according to a second embodiment of the invention.
Fig. 11 is a timing diagram of gate timing signals output by the timing controller in the color mode according to the second embodiment of the present invention.
Fig. 12 is a timing diagram of gate timing signals output by the timing controller in the power-saving display mode according to the second embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings.
First embodiment
Fig. 2 is a schematic structural diagram of a driving circuit according to a first embodiment of the present invention. As shown in fig. 2, the driving circuit provided by the present invention is used for driving the display panel 101. The driving circuit includes a timing controller 110, a gate driving circuit 120, and a source driving circuit 130.
The timing controller 110 is configured to output a gate timing signal to the gate driving circuit 120 and output a source timing signal to the source driving circuit 130.
The gate driving circuit 120 includes a plurality of sub-gate driving circuits arranged in sequence, each sub-gate driving circuit includes m gate driving units, specifically, m may be equal to 3 or 4, m is equal to 3 in this embodiment, and each stage of gate driving unit is configured to output a present stage of gate driving signal Gn (N is equal to 1, 2, 3 … … N) to a corresponding sub-pixel according to a gate timing signal, where N is an integer greater than or equal to m.
The source driving circuit 130 is configured to generate a source driving signal Sn (only S1, S2, S3 are shown in fig. 2) according to a source timing signal input from the timing controller 110.
In the color mode, the driving circuit scans each pixel row by row, the frequency of the gate driving signal Gn output by each gate driving unit is matched with the frequency of the source driving signal Sn output by each row of data lines, and the source driving circuit 130 charges only the sub-pixels in a certain row at a time.
In the power saving display mode, the gate driving signals output by each stage of gate driving units in the same sub-gate driving circuit are the same, such as the gate driving signals G1, G2 and G3 output by each stage of gate driving units in the first sub-gate driving circuit G1X in fig. 2. The number of times of switching of the source drive signal Sn output from the source drive circuit 130 is m times that in the color mode. At this time, the gate driving circuit 120 does not scan each sub-pixel row by row, but scans m rows simultaneously, so the source driving signal Sn output by the source driving circuit 130 charges the sub-pixels of the m rows each time, the number of times of switching of the source driving signal Sn is m times of that in the color mode, and thus the refresh frequency of the source driving signal Sn is reduced, thereby reducing the power consumption of the system.
In this embodiment, in the power saving display mode, the frequency of the gate driving signal Gn output by the gate driving circuit 120 is the same as the frequency in the color mode, and the frequency of the source driving signal Sn output by the source driving circuit 130 is one third of the frequency in the color mode, so that the power saving effect is achieved. In addition, each gate driving unit of the same sub-gate driving circuit outputs a high-level gate driving signal to a corresponding pixel unit, so that the sub-pixels on the three rows of scanning lines are charged by the source driving signal Sn at the same time, and the source driving circuit 130 is controlled to output the corresponding source driving signal Sn, thereby achieving the switching from the color mode to the black-and-white mode.
Preferably, the sub-pixels corresponding to the sub-gate driving circuit of this example are a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The light colors emitted by the three sub-pixels are the three primary colors of light, and the light can present different colors after being mixed. Therefore, in the power-saving display mode, the source driving circuit 130 outputs the specific source driving signal Sn, and the driving circuit can drive the display panel 101 to switch between the color mode and the black-and-white mode.
Preferably, all the sub-pixels of each pixel unit are located in the same row, and the arrangement manner of the sub-pixels of each pixel unit is the same, in this embodiment, the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B of the pixel unit are located in the same row, and the arrangement manner of the sub-pixels of each pixel unit is the same, as shown in fig. 2, the sub-pixels of each pixel unit are all sequentially arranged.
Preferably, the timing controller 110 receives a mode switching command and outputs a corresponding gate timing signal according to the mode switching command. The instructions may be, but are not limited to being, input by a user through an input device.
In the embodiment, the gate timing signals provided by the timing controller 110 to each gate driving unit in the same sub-gate driving circuit in the power-saving display mode are the same and are the gate timing signals provided to the first gate driving unit in the sub-gate driving circuit in the color mode. For example, the gate driving signals G1, G2 and G3 output by each stage of gate driving unit in the first sub-gate driving circuit G1X are the same, and the gate driving signals G1, G2 and G3 are all the gate timing signals provided to the first gate driving unit in the first sub-gate driving circuit G1X in the color mode.
Fig. 3 is a circuit diagram of a gate driving unit according to a first embodiment of the invention. Each stage of the gate driving unit includes a first switching element T1, a second switching element T2, a third switching element T3, and a fourth switching element T4.
Fig. 3 is a diagram illustrating a first stage gate driving unit according to a first embodiment of the present invention. The first switching element T1 includes a first path terminal, a second path terminal, and a first control terminal, the first control terminal receives the first pulse signal, and the first path terminal receives the reference high voltage VDD. The second switching element T2 includes a third path terminal, a fourth path terminal, and a second control terminal, the second control terminal receives the second pulse signal, and the fourth path terminal receives the reference low voltage VSS. The third switching element T3 includes a fifth path terminal connected to the first gate timing signal CLK1, a sixth path terminal outputting the present gate driving signal Gn, and a third control terminal connected to the second path terminal of the first switching element T1 and the third path terminal of the second switching element T2. And a fourth switching element T4 including a seventh path terminal, an eighth path terminal and a fourth control terminal, wherein the seventh path terminal is connected to the sixth path terminal of the third switching element T3, the eighth path terminal receives the reference low voltage VGL, and the fourth control terminal is connected to the fourth gate timing signal CLK 4. The first pulse signal is an upper three-level grid timing signal Gn-3 output by the grid driving unit with an upward difference of three levels except the previous three-level grid driving unit; except the last three stages of gate driving units, the second pulse signal is a lower three-stage gate timing signal Gn +3 output by the gate driving unit with a downward phase difference of three stages. The first pulse signal received by the gate driving unit of the first level and the second pulse signal received by the gate driving unit of the second level are both provided by an external signal circuit, because the gate driving unit of the first level has no gate driving unit with a difference of three levels upwards and the gate driving unit of the second level has no gate driving unit with a difference of three levels downwards.
In the first embodiment of the present invention, each stage of the gate driving unit further includes a stabilizing unit for maintaining the gate driving signal Gn at the reference low voltage VGL when the gate driving signal Gn is at a low voltage.
Fig. 4 is a schematic structural diagram of a gate driving circuit according to a first embodiment of the invention. Fig. 4 shows only the circuit connections of the gate driving units of the first six stages, and the circuit connections of the gate driving circuits are illustrated by way of example. As can be seen from fig. 4, each stage of the gate driving unit includes five input terminals and one output terminal. The i-th stage gate driving unit has five input terminals respectively receiving the reference high voltage VDD, the gate timing signal CLKi, the gate timing signal CLK (i +3), the reference low voltage VSS and the reference low voltage VGL, and an output terminal for outputting the present stage gate driving signal Gn. As shown in fig. 4, the first stage gate driving unit is configured to receive the first gate timing signal CLK1 and the fourth gate timing signal CLK4 and output a first stage gate driving signal G1. The second stage gate driving unit outputs a second stage gate driving signal G2, and receives a second gate timing signal CLK2 and a fifth gate timing signal CLK 5. And with 9 gate timing signals as a repeating cycle, it can be deduced that the seventh stage gate driving unit receives the seventh gate timing signal CLK7 and the first gate timing signal CLK1, and so on for each stage of connection of the gate driving units.
Besides the gate driving units of the previous three stages, the first pulse signal received by the gate driving unit is the upper three-stage gate timing signal Gn-3 output by the gate driving unit with an upward difference of three stages, as shown in fig. 4, the fourth stage gate driving unit receives the upper three-stage gate timing signal G1, and the fifth stage gate driving unit receives the upper three-stage gate timing signal G2; the second pulse signal is a gate timing signal Gn +3 of a lower level, which is outputted by a gate driving unit that is shifted downward by three levels, except for the gate driving units of the last level, as shown in fig. 4, the gate driving unit of the first level receives a gate timing signal G4 of an upper level, the gate driving unit of the second level receives a gate timing signal G5 of an upper level, and so on. Since the gate driving units of the front three stages do not have a gate driving unit with a difference of three stages upwards and the gate driving units of the rear three stages do not have a gate driving unit with a difference of three stages downwards, the first pulse signal received by the gate driving units of the front three stages and the second pulse signal received by the gate driving units of the rear three stages are both provided by an external signal circuit, as shown in fig. 4, the first gate driving unit receives an external signal STV1, the second gate driving unit receives an external signal STV2, and the third gate driving unit receives an external signal STV 3.
Fig. 5 is a timing diagram of gate timing signals output by the timing controller in the color mode according to the first embodiment of the present invention. As shown in fig. 5, the first to ninth gate timing signals CLK1 to CLK9 sequentially turn from low to high in the color mode, the periods of the first to ninth gate timing signals CLK1 to CLK9 are the same, and the interval between the first to ninth gate timing signals CLK1 to CLK9 turning from low to high is one ninth period.
Fig. 6 is a timing diagram of gate timing signals output by the timing controller in the power-saving display mode according to the first embodiment of the invention. The first gate timing signal CLK1, the second gate timing signal CLK2 and the third gate timing signal CLK3 are the same, the fourth gate timing signal CLK4, the fifth gate timing signal CLK5 and the sixth gate timing signal CLK6 are the same, and the seventh gate timing signal CLK7, the eighth gate timing signal CLK8 and the ninth gate timing signal CLK9 are the same. The first gate timing signal CLK1, the fourth gate timing signal CLK4, and the seventh gate timing signal CLK7 sequentially change from low level to high level, the interval time from low level to high level is one third of a period, and the high level maintaining time in each period is one third of a period.
Wherein, when the power saving display mode, the working process of each stage of gate driving unit can be divided into 4 stages of pre-charging stage, pull-up stage, pull-down stage and stable stage:
precharge phase i.e. first phase: the gate driving signal Gn-3 to the third stage, which is outputted to the gate driving unit to the third stage, received by the first control terminal of the first switching element T1, is at a high level, the first switching element T1 is turned on, the voltage at the node Q is pulled high through the turned-on first switching element T1, the voltage at the node Q is precharged with reference to the high voltage VDD through the turned-on first switching element T1, and the third switching element T3 is turned on;
the pull-up stage is the second stage: when the first gate timing signal CLK1 changes from low level to high level, since the node Q has been precharged in the precharge phase, the third switching element T3 is turned on, so that the present stage gate driving signal Gn is pulled high by the first gate timing signal CLK1 through the turned-on third switching element T3;
pull-down phase i.e. third phase: the first gate timing signal CLK1 changes from high level to low level, the third switching element T3 is turned on since the voltage at the node Q is high level in the pull-up stage, the present gate driving signal Gn is pulled down through the turned-on third switching element T3, and at the same time, when the fourth gate signal CLK4 changes from low level to high level, the present gate driving signal Gn is pulled down to the reference low voltage VGL through the turned-on fourth switching element T4;
further, since the gate driving signal Gn +3 of the downward phase difference three stage is changed from the low level to the high level and the second switching element T2 is turned on, the node Q is pulled low by the turned-on second switching element T2 and the third switching element T3 is turned off;
stabilization phase, i.e. fourth phase: since the voltage at the node Q is pulled low during the pull-down phase, the third switching element T3 is turned off, and the influence of the first gate timing signal CLK1 on the present stage gate driving signal Gn is avoided.
As described above, only the preferred embodiment of the present invention is provided, and during the power saving mode, it is not limited that the received gate timing signals of the gate driving units in the same sub-gate driving circuit are the same, and if the specific circuits of the gate driving units in the same sub-gate driving circuit are different, the received gate timing signals of the gate driving units may also be different, and it is the scope of the present invention as long as the gate driving signals output by the same sub-gate driving circuit are the same.
FIG. 7 is a diagram illustrating the relationship between the gate driving signals and the source driving signals in the color mode according to the present invention. As can be seen from fig. 7, in the above embodiment, the gate driving signals Gn (e.g., G1, G2, G3, etc.) sequentially change from low level to high level, the interval time between the low level and the high level of each stage is T, and the source driving signal Sn corresponding to one data line output by the source driving circuit is switched once every T times.
FIG. 8 is a diagram illustrating a relationship between a gate driving signal and a source driving signal in a power-saving display mode according to the present invention. It can be seen that the gate driving signals of the above embodiments are the same as the gate driving signals output by the gate driving units of the same sub-gate driving circuit, such as the first gate driving signal G1, the second gate driving signal G2, and the third gate driving signal G3 are equal, the fourth gate driving signal G4, the fifth gate driving signal G5, and the sixth gate driving signal G6 are equal, and so on. And the gate driving signals output by the gate driving unit are sequentially changed from low level to high level according to the group, the interval time of changing the low level to the high level of each group is 3T, and in addition, the source driving signal Sn corresponding to a data line output by the source driving circuit is switched once every 3T. In other words, compared with the color mode, the frequency of the source driving signal output by the source driving circuit is one third of the original frequency, thereby achieving the purpose of reducing the system power consumption.
The present embodiment further includes a liquid crystal display device, which includes the driving circuit and the display panel.
Second embodiment
Fig. 9 is a schematic structural diagram of a driving circuit according to a second embodiment of the present invention. As shown in fig. 9, the driving circuit provided by the present invention is used for driving the display panel 101. The driving circuit includes a timing controller 110, a gate driving circuit 120, and a source driving circuit 130.
The timing controller 110 is configured to output a gate timing signal to the gate driving circuit 120 and output a source timing signal to the source driving circuit 130.
The gate driving circuit 120 includes a plurality of sub-gate driving circuits arranged in sequence, each sub-gate driving circuit includes 4(m is equal to 4) gate driving units, and each stage of gate driving unit is configured to output a present stage gate driving signal Gn (N is equal to 1, 2, 3 … … N) to a corresponding sub-pixel according to a gate timing signal, where N is an integer greater than or equal to m. The source driving circuit 130 is configured to generate a source driving signal Sn (only S1, S2, S3 are shown in fig. 9) according to a source timing signal input from the timing controller 110.
In the color mode, the driving circuit scans each pixel row by row, the frequency of the gate driving signal Gn output by each gate driving unit is matched with the frequency of the source driving signal Sn output by each row of data lines, and the source driving circuit 130 can charge only the sub-pixels in a certain row at a time.
In the present embodiment, in the power saving display mode, the gate driving signals output by each stage of gate driving units in the same sub-gate driving circuit are the same, as in fig. 9, the gate driving signals G1, G2, G3, and G4 output by each stage of gate driving units in the first sub-gate driving circuit G1X are the same. The number of times of switching of the source driving signal Sn output from the source driving circuit 130 is one fourth of that in the color mode. At this time, the gate driving circuit 120 does not scan each sub-pixel row by row, but simultaneously scans four rows, so the source driving signal Sn output from the source driving circuit 130 charges the four rows of sub-pixels at a time. The frequency of the gate driving signal Gn output by the gate driving circuit 120 is the same as the frequency in the color mode, and the frequency of the source driving signal Sn output by the source driving circuit 130 is one fourth of the frequency in the color mode, so that the refresh frequency of the source driving signal Sn is reduced, thereby reducing the power consumption of the system and achieving the power saving effect. In addition, each gate driving unit of the same sub-gate driving circuit outputs a high-level gate driving signal to a corresponding sub-pixel, so that the sub-pixels on four rows of scanning lines are charged by the source driving signal Sn at the same time, and the source driving circuit 130 is controlled to output a corresponding source driving signal Sn, thereby achieving the switching from the color mode to the black-and-white mode.
In the present embodiment, the sub-pixels are preferably a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W. The light colors emitted by the first three sub-pixels are the three primary colors of light, the light mixture can present different colors, and the white sub-pixel has the function of adjusting the brightness. Therefore, when in the power-saving display mode, the source driving circuit outputs a specific source driving signal, and the circuit can realize the switching between the color mode and the black-and-white mode.
Preferably, all the sub-pixels of each pixel unit are located in the same row, and the arrangement manner of the sub-pixels of each pixel unit is the same, in this embodiment, specifically, the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the white sub-pixel W of each pixel unit are located in the same row, and the arrangement manner of the sub-pixels of each pixel unit is the same, as shown in fig. 9, the sub-pixels of each pixel unit are all sequentially arranged by the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the white sub-pixel W.
Preferably, the timing controller 110 receives a mode switching command and outputs a corresponding gate timing signal according to the mode switching command. The instructions may be, but are not limited to being, input by a user through an input device.
In the embodiment, the gate timing signals provided by the timing controller 110 to each gate driving unit in the same sub-gate driving circuit in the power-saving display mode are the same and are the gate timing signals provided to the first gate driving unit in the sub-gate driving circuit in the color mode. For example, in fig. 9, the gate driving signals G1, G2, G3 and G4 output by each stage of gate driving unit in the first sub-gate driving circuit G1X are the same, and the gate driving signals G1, G2, G3 and G4 are all the gate timing signals provided to the first gate driving unit in the first sub-gate driving circuit G1X in the color mode.
Fig. 10 is a circuit diagram of a gate driving unit according to a second embodiment of the invention. Fig. 10 is a diagram illustrating a first-stage gate driving unit according to a second embodiment of the present invention. Each stage of the gate driving unit includes a first switching element T1, a second switching element T2, a third switching element T3, and a fourth switching element T4.
The first switch element T1 includes a first path terminal, a second path terminal, and a first control terminal, the first control terminal receives the first pulse signal, and the first path terminal receives the reference high voltage VDD. The second switching element T2 includes a third path terminal, a fourth path terminal, and a second control terminal, the second control terminal receives the second pulse signal, and the fourth path terminal receives the reference low voltage VSS. The third switching element T3 includes a fifth path terminal connected to the first gate timing signal CLK1, a sixth path terminal outputting the present gate driving signal Gn, and a third control terminal connected to the second path terminal of the first switching element T1 and the third path terminal of the second switching element T2. And a fourth switching element T4 including a seventh path terminal, an eighth path terminal and a fourth control terminal, wherein the seventh path terminal is connected to the sixth path terminal of the third switching element T3, the eighth path terminal receives the reference low voltage VGL, and the fourth control terminal is connected to the fourth gate timing signal CLK 4. The first pulse signal is an upper four-stage grid timing signal Gn-4 output by the grid driving unit with the upper phase difference of four stages except the front four-stage grid driving unit; except for the last four-stage gate driving unit, the second pulse signal is a lower four-stage gate timing signal Gn +4 output by the gate driving unit with a downward phase difference of four stages. The first pulse signal received by the front-stage gate driving unit and the second pulse signal received by the rear-stage gate driving unit are both provided by an external signal circuit, because the front-stage gate driving unit has no gate driving unit with a difference of four stages upwards and the rear-stage gate driving unit has no gate driving unit with a difference of four stages downwards.
In the second embodiment of the present invention, each stage of the gate driving unit further includes a stabilizing unit for maintaining the gate driving signal Gn at the reference low voltage VGL when the gate driving signal Gn is at a low voltage.
Fig. 11 is a timing diagram of gate timing signals output by the timing controller in the color mode according to the second embodiment of the present invention. As shown in fig. 11, the first to twelfth gate timing signals CLK1 to CLK12 sequentially turn from low level to high level in the color mode, the periods of the first to twelfth gate timing signals CLK1 to CLK12 are the same, and the interval between the first to twelfth gate timing signals CLK1 to CLK12 turning from low level to high level is one twelfth of a period.
Fig. 12 is a timing diagram of gate timing signals output by the timing controller in the power-saving display mode according to the second embodiment of the invention. The first gate timing signal CLK1, the second gate timing signal CLK2, the third gate timing signal CLK3 and the fourth gate timing signal CLK4 are the same, the fifth gate timing signal CLK5, the sixth gate timing signal CLK6, the seventh gate timing signal CLK7 and the eighth gate timing signal CLK8 are the same, and the ninth gate timing signal CLK9, the tenth gate timing signal CLK10, the eleventh gate timing signal CLK11 and the twelfth gate timing signal CLK12 are the same. The first gate timing signal CLK1, the fifth gate timing signal CLK5, and the ninth gate timing signal CLK9 sequentially change from low level to high level, the interval time from low level to high level is one third of a period, and the high level maintaining time in each period is one third of a period.
Wherein, when the power saving display mode, the working process of each stage of gate driving unit can be divided into 4 stages of pre-charging stage, pull-up stage, pull-down stage and stable stage:
precharge phase i.e. first phase: the gate driving signal Gn-4 of the up phase difference four stage outputted from the gate driving unit of the up phase difference four stage received by the first control terminal of the first switching element T1 is at a high level, the first switching element T1 is turned on, the voltage at the node Q is pulled high through the turned-on first switching element T1, the voltage at the node Q is precharged with reference to the high voltage VDD through the turned-on first switching element T1, and the third switching element T3 is turned on;
the pull-up stage is the second stage: when the first gate timing signal CLK1 changes from low level to high level, since the node Q has been precharged in the precharge phase, the third switching element T3 is turned on, so that the present stage gate driving signal Gn is pulled high by the first gate timing signal CLK1 through the turned-on third switching element T3;
pull-down phase i.e. third phase: the first gate timing signal CLK1 changes from high level to low level, the third switching element T3 is turned on since the voltage at the node Q is high level in the pull-up stage, the present gate driving signal Gn is pulled down through the turned-on third switching element T3, and at the same time, when the fourth gate signal CLK4 changes from low level to high level, the present gate driving signal Gn is pulled down to the reference low voltage VGL through the turned-on fourth switching element T4;
further, since the gate driving signal Gn +4 shifted down by four stages is changed from the low level to the high level and the second switching element T2 is turned on, the node Q is pulled low by the turned-on second switching element T2 and the third switching element T3 is turned off;
stabilization phase, i.e. fourth phase: since the voltage at the node Q is pulled low during the pull-down phase, the third switching element T3 is turned off, and the influence of the first gate timing signal CLK1 on the present stage gate driving signal Gn is avoided.
As described above, only the preferred embodiment of the present invention is provided, and during the power saving mode, it is not limited that the received gate timing signals of the gate driving units in the same sub-gate driving circuit are the same, and if the specific circuits of the gate driving units in the same sub-gate driving circuit are different, the received gate timing signals of the gate driving units may also be different, and it is the scope of the present invention as long as the gate driving signals output by the same sub-gate driving circuit are the same.
The present embodiment further includes a liquid crystal display device, which includes the driving circuit and the display panel.
The driving circuit and the liquid crystal display device of the invention are provided with a time controller, a grid driving circuit and a source driving circuit; when the power-saving display mode is started, the gate driving signals output by each gate driving unit in the same sub-gate driving circuit are the same, and the switching frequency of the source driving signals output by the source driving circuit is m times of that of the color mode, so that the output signals of the gate driving circuit and the source driving circuit are changed, the power consumption can be effectively saved, and the display picture can be switched from the color mode to the black-and-white mode.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A drive circuit is used for driving a display panel and is characterized by comprising a time schedule controller, a grid drive circuit and a source drive circuit;
the time sequence controller is used for outputting a grid time sequence signal to the grid driving circuit and outputting a source time sequence signal to the source driving circuit;
the grid driving circuit comprises a plurality of sub-grid driving circuits which are sequentially arranged, each sub-grid driving circuit comprises m grid driving units, and each stage of grid driving unit is used for outputting a stage of grid driving signal to a corresponding sub-pixel according to the grid time sequence signal;
the source driving circuit is used for generating a source driving signal according to the source timing signal input by the timing controller;
in the power-saving display mode, the gate driving signals output by each gate driving unit in the same sub-gate driving circuit are the same, and the number of times of switching the source driving signals output by the source driving circuit is one m of that in the color mode, wherein m is equal to 3 or 4.
2. The driving circuit as claimed in claim 1, wherein in the power-saving display mode, the sub-gate driving circuit outputs the gate driving signal with a frequency equal to a frequency in the color mode, and the source driving circuit outputs the source driving signal with a frequency m times lower than the frequency in the color mode.
3. The driving circuit according to claim 1, wherein the sub-pixels corresponding to the sub-gate driving circuit include red, green, and blue sub-pixels.
4. The driving circuit according to claim 1, wherein the sub-pixels corresponding to the sub-gate driving circuit include red, green, blue, and white sub-pixels.
5. The driving circuit of claim 1, wherein all the sub-pixels of each pixel unit are located in the same row, and the sub-pixels of each pixel unit are arranged in the same manner.
6. The driving circuit of claim 1, wherein the timing controller receives a command for mode switching, and outputs a corresponding gate timing signal according to the command for mode switching, the command being input by a user through an input device.
7. The driving circuit as claimed in claim 6, wherein the timing controller outputs the same gate timing signal to each gate driving unit in the same sub-gate driving circuit in the power saving display mode.
8. The drive circuit according to claim 1, wherein the gate drive unit includes:
the first switch element comprises a first path end, a second path end and a first control end, wherein the first control end receives a first pulse signal, and the first path end receives a reference high voltage;
a second switching element including a third path terminal, a fourth path terminal, and a second control terminal, the second control terminal receiving the second pulse signal, the fourth path terminal receiving the reference low voltage;
a third switching element including a fifth path terminal, a sixth path terminal and a third control terminal, wherein the fifth path terminal is connected to the first gate timing signal, the sixth path terminal outputs the present-stage gate driving signal, and the third control terminal is connected to the second path terminal of the first switching element and the third path terminal of the second switching element;
a fourth switching element including a seventh path terminal, an eighth path terminal, and a fourth control terminal, wherein the seventh path terminal is connected to the sixth path terminal of the third switching element, the eighth path terminal receives the reference low voltage, and the fourth control terminal is connected to the fourth gate timing signal;
the first pulse signal is an upper three-stage grid driving signal output by a grid driving unit with an upward phase difference of three stages except for a front three-stage grid driving unit; except the last three-stage grid driving unit, the second pulse signal is a lower three-stage grid driving signal output by the grid driving unit with downward phase difference of three stages.
9. A liquid crystal display device comprising the driver circuit according to any one of claims 1 to 8 and a display panel.
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| CN112447145B (en) * | 2019-08-29 | 2022-06-24 | 北京小米移动软件有限公司 | Display panel, display mode switching method and device and electronic equipment |
| CN113870757B (en) * | 2020-06-30 | 2023-07-04 | 京东方科技集团股份有限公司 | Driving method, driving circuit and display device of display panel |
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| TWI567724B (en) * | 2015-06-22 | 2017-01-21 | 矽創電子股份有限公司 | Driving module for display device and related driving method |
| CN105047158B (en) * | 2015-08-21 | 2017-11-10 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display |
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| CN106887216B (en) * | 2017-03-09 | 2019-04-19 | 京东方科技集团股份有限公司 | The driving method of gate driving circuit, display panel and gate driving circuit |
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