CN107423159B - A method of LDPC decoding performance is promoted based on flash memory error pattern - Google Patents
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
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Abstract
The invention discloses a kind of method for promoting LDPC decoding performance based on flash memory error pattern, the every unit of TLC nand flash memory, which stores 3 bit datas, has high storage density, but the interference between storage unit more reduces data reliability strongly.In order to guarantee data reliability, the LDPC code with strong error correcting capability is used, however LDPC code has high decoding complexity, will cause the decline of decoding performance when could be used without optimised LDPC code.Therefore, in order to improve LDPC decoding performance, the present invention analyzes the error pattern of TLC nand flash memory first, then external information required for LDPC is decoded is converted by error pattern, the external information is dissolved into the decoding process of LDPC, promotes the decoding performance of LDPC with this and then reduces decoding latency.
Description
Technical field
The invention belongs to solid-state disk technical field of memory, are promoted more particularly, to one kind based on flash memory error pattern
The method of LDPC decoding performance.
Background technique
Nowadays, three-level unit (Triple-Level Cell, abbreviation TLC) nand flash memory cell is widely used, reason
It is, every unit is stored with 3 bit datas, thus memory capacity with higher.
Along with the interference enhancing between TLC nand flash memory cell, so that the bit data of storage in the cells is easy hair
Raw mistake, therefore the data reliability in flash cell can be reduced.In order to guarantee data reliability, error correcting code (Error
Correction Codes, abbreviation ECC) it is widely used, wherein low-density checksum (Low Density Parity
Check, abbreviation LDPC) code is a kind of most common error correcting code.
However, existing LDPC error correction algorithm can not there are one in terms of the data reliability for guaranteeing TLC nand flash memory
The problem of ignoring, i.e., existing LDPC error correction algorithm complexity is high, be easy to cause decoding performance low, and decoding latency is high.
Summary of the invention
Aiming at the above defects or improvement requirements of the prior art, the present invention provides one kind is promoted based on flash memory error pattern
The method of LDPC decoding performance, it is intended that by the error pattern for analyzing TLC nand flash memory channel first, it then will be wrong
Accidentally mode is converted into the external information for being conducive to LDPC decoding, and the decoding that finally external information is dissolved into LDPC was adjudicated
Journey, while the optimization that LDPC decodes initial soft decision information is carried out using the external information, it is entangled so as to solve existing LDPC
Wrong algorithm complexity is high, be easy to cause decoding performance low and the high technical problem of decoding latency.
To achieve the above object, according to one aspect of the present invention, it provides a kind of based on the promotion of flash memory error pattern
The method of LDPC decoding performance is to apply in flash memory system, the described method comprises the following steps:
(1) it is 0 and 1 test matrix H that generating, which has cyclic shift characteristic and element, wherein the size of the matrix H be m ×
N, and 0 number of elements of the number of elements greater than 1, wherein m=n (1-r), m indicate the redundancy to be generated in an encoding process
Position, and the code word size to be generated during n=k/r, n presentation code, k indicate flash memory pages size, and r indicates code rate；
(2) sending sequence write order, according to the sequence write order and using generation test matrix H in step (1) to length
For the bit sequence of nIt is encoded, to generate length as the redundant digit of mAnd the bit sequence that coding will have been completedIt is transferred in page register；
(3) by the bit sequence in page registerIt is written to MSB pages of TLC nand flash memory, to other bit sequence
ColumnWithStep (2) are repeated respectively, and will be obtained
Complete the bit sequence of codingCSB pages of TLC nand flash memory is written, it willThe LSB page of TLC nand flash memory is written；
(4) original bit sequence being stored in MSB pages, CSB pages and LSB page is extracted respectively WithDue to by
The interference of TLC nand flash memory channel noise and bit-errors occur and are formed by new bit sequenceWithJust
Beginning soft decision information, using belief propagation algorithm to new bit sequenceWithInitial soft decision information carry out LDPC decoding, to obtain the corresponding soft letter of decoding result
Breath obtains the corresponding external information of LSB according to initial soft decision information Soft Inform ation corresponding with decoding result；
(5) the corresponding external information of LSB is decoded using belief propagation algorithm, decoding latency is counted,
And host side is sent by decoding latency and decoding result.
Preferably, flash memory pages size is equal to 2aBit, wherein a is the natural number more than or equal to 9 and less than or equal to 14),
The value range of r is between 0.75 to 0.95.
Preferably, the coding rule in step (2) is
Preferably,Indicate known bit sequence,Indicate unknown redundancy
Position, the length is m,WithCollectively form the bit sequence for having completed coding
Preferably, belief propagation algorithm is standard minimum and/or layered min-sum algorithm.
Preferably, the error pattern packet of TLC nand flash memory is extracted in step (4) according to three bit sequences of extraction
Include following sub-step:
(4-1) obtains new bit sequence using detection levelInitial MSB soft sentence
Certainly informationInitial MSB soft decision information is carried out using belief propagation algorithm
LDPC decoding, to obtain the corresponding MSB Soft Inform ation of decoding result
(4-2) obtains new bit sequence using detection levelInitial CSB soft-decision letter
BreathLDPC is carried out to initial CSB soft decision information using belief propagation algorithm to translate
Code, to obtain the corresponding CSB Soft Inform ation of decoding result
The initial MSB soft decision information that (4-3) is obtained according to step (4-1) MSB Soft Inform ation corresponding with decoding result, with
And the initial CSB soft decision information CSB Soft Inform ation corresponding with decoding result that step (4-2) obtains is to new bit sequenceInitial LSB soft decision informationIt is handled, to obtain
The corresponding external information of LSB
Preferably, step (4-3) specifically:
If decoding the corresponding MSB Soft Inform ation of resultIn RmjIt is tied greater than 0 with decoding
The corresponding CSB Soft Inform ation of fruitIn RcjGreater than 0, and initial MSB soft decision informationInGreater than 0 and initial CSB soft decision information
InGreater than 0, then it is correctly, during LDPC decoding, LSB to be arranged that the LSB bit value read, which has biggish probability,
External information valueInFor new bit sequence
Initial LSB soft decision informationIn2.5 times, i.e.,Its
In 1≤j≤n；
If decoding the corresponding MSB Soft Inform ation of resultIn RmjGreater than 0, initial MSB
Soft decision informationInGreater than 0, and decode the corresponding CSB Soft Inform ation of resultIn RcjMultiplied by initial CSB soft decision informationIn
'sLess than 0, i.e.,A possibility that then original LSB bit value is 1 is larger, during LDPC decoding, setting
The external information value of LSBInIt is 2, i.e.,To rapidly make LSB bit value
Converge to bit 1；
If decoding the corresponding MSB Soft Inform ation of resultIn Rmj(1≤j≤n) is less than
0, initial MSB soft decision informationInLess than 0, and it is soft to decode the corresponding CSB of result
InformationIn RcjMultiplied by initial CSB soft decision informationInLess than 0, i.e.,A possibility that then original LSB bit value is 1 is larger, during the decoding of LDPC, setting
The external information value of LSBInIt is 2, i.e.,To rapidly make LSB bit
Value converges to bit 1；
If decoding the corresponding MSB Soft Inform ation of resultIn Rmj(1≤j≤n) multiplied by
Initial MSB soft decision informationInLess than 0, i.e.,Decoding
As a result corresponding CSB Soft Inform ationIn RcjGreater than 0, and initial CSB soft decision informationInGreater than 0, then it is bit 0 that original LSB bit value, which has biggish probability,
During the decoding of LDPC, the external information value of LSB is setInIt is -2, i.e.,To rapidly make LSB bit value converge to bit 0；
If decoding the corresponding MSB Soft Inform ation of resultIn RmjIt is soft multiplied by initial MSB
Discriminative informationInLess than 0, i.e.,And decoding result is corresponding
CSB Soft Inform ationIn RcjMultiplied by initial CSB soft decision informationInLess than 0, i.e.,The LSB bit value then read has biggish
Probability is correctly, during the decoding of LDPC, the external information value of LSB to be arrangedIn
'sFor new bit sequenceInitial LSB soft decision information
In2.5 times, i.e.,
Preferably, initial MSB soft decision information, initial CSB soft decision information and initial LSB soft decision information are by such as
Lower formula is calculated；
Wherein L (MSB), L (CSB) and L (LSB) respectively indicate initial MSB soft decision information, initial soft CSB discriminative information
With initial LSB soft decision information,Expression is the probability density distribution of the threshold voltage of TLC nand flash memory cell, and is taken
From normal distribution, V1And V2Respectively indicate the reference voltage lower limit value and upper limit value of detection level.
A kind of LDPC decoding performance is promoted based on flash memory error pattern it be it is another aspect of this invention to provide that provides
System, is applied in flash memory system, the system comprises:
First module has cyclic shift characteristic and element for 0 and 1 test matrix H, wherein the matrix H for generating
Size be m × n, and 0 number of elements be greater than 1 number of elements, wherein m=n (1-r), m expression wanted in an encoding process
The redundant digit of generation, and the code word size to be generated during n=k/r, n presentation code, k indicate flash memory pages size, r table
Show code rate.
Second module is used for sending sequence write order, examines square according to the sequence write order and using generating in step (1)
The bit sequence that battle array H is n to lengthIt is encoded, to generate length as the redundant digit of mAnd the bit sequence that coding will have been completedIt is transferred in page register；
Third module, for by the bit sequence in page registerIt is written to MSB pages of TLC nand flash memory, to another
Outer bit sequenceWithIt repeats respectively step (2), and will
What is obtained has completed the bit sequence of codingCSB pages of TLC nand flash memory is written, it willThe LSB page of TLC nand flash memory is written；
4th module, for extracting the original bit sequence being stored in MSB pages, CSB pages and LSB page respectivelyWithBit-errors occur and are formed by new bit sequence due to the interference by TLC nand flash memory channel noiseWithIt is initial soft
Discriminative information, using belief propagation algorithm to new bit sequenceWithInitial soft decision information carry out LDPC decoding, to obtain the corresponding soft letter of decoding result
Breath obtains the corresponding external information of LSB according to initial soft decision information Soft Inform ation corresponding with decoding result；
5th module, for being decoded using belief propagation algorithm to the corresponding external information of LSB, to decoding latency
It is counted, and sends host side for decoding latency and decoding result.
In general, through the invention it is contemplated above technical scheme is compared with the prior art, can obtain down and show
Beneficial effect:
(1) method of the invention by step (4) to step (5) its can using TLC nand flash memory error pattern and just
Beginning MSB and CSB soft decision information and MSB CSB Soft Inform ation corresponding with decoding result optimize initial LSB soft decision information and obtain
More accurate LSB external information decode to LSB external information being therefore able to solve present in existing LDPC algorithm again
Miscellaneous degree is high, be easy to cause decoding performance low, the high problem of decoding latency；
(2) it can be examined method of the invention during executing LDPC decoding by step (4-1) to step (4-3)
Consider influence of the TLC nand flash memory error pattern to decoding, TLC nand flash memory error pattern is fused to during LDPC decoding
Therefore it is able to ascend LDPC decoding performance and reduces LDPC decoding latency
(3) method of the invention can be improved LDPC decoding judgement precision, and high-efficient, speed is fast, saves cost.
(4) present invention can preferably promote the performance of the continuous read operation of TLC nand flash memory.
Detailed description of the invention
Fig. 1 is the design structure diagram that the method for LDPC decoding performance is promoted the present invention is based on flash memory error pattern.
Fig. 2 is the flow chart that the method for LDPC decoding performance is promoted the present invention is based on flash memory error pattern.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in the various embodiments of the present invention described below
Not constituting a conflict with each other can be combined with each other.
Design structure diagram of the invention is as shown in Figure 1, bit sequence is transferred to the page after LDPC encoder coding
In register, in write TLC nand flash memory first MSB pages, other bit sequences encoded write CSB pages and LSB in succession
In page.The bit data being stored in TLC nand flash memory page is interfered by channel noise and mistake occurs.At this point, TLC NAND
The error pattern of flash memory is extracted, and during decoding, initial MSB soft decision information is extracted first is then transmitted to the page
Then register is transferred to ldpc decoder by page register and is decoded, on the one hand MSB pages of decoding result is output to
On the one hand host side will decode the corresponding Soft Inform ation storage of result into a buffer.After MSB pages of decoding terminates, just
Beginning CSB soft decision information is extracted and then is read in page register by transmission, and then is transferred to LDPC by page register and translates
Code device is decoded, on the one hand CSB pages of decoding result is output to host side, on the one hand will decode the corresponding Soft Inform ation of result
It stores in another buffer.When completing CSB pages of decoding, initial LSB soft decision information is read in page register,
At this point, the error pattern of the corresponding Soft Inform ation of decoding result of MSB and CSB and TLC nand flash memory is dissolved into initial
In LSB soft decision information, optimize the soft decision information of initial LSB to promote LDPC decoding performance and then accelerate to decode.
As shown in Fig. 2, the present invention is based on the method that flash memory error pattern promotes LDPC decoding performance being applied in flash memory
In system, and the following steps are included:
(1) it is 0 and 1 test matrix H that generating, which has cyclic shift characteristic and element, wherein the size of the matrix H be m ×
N, and 0 number of elements of the number of elements greater than 1, wherein m=n (1-r), m expression to be generated in following cataloged procedure
Redundant digit, n=k/r, n indicate that the code word size to be generated in following cataloged procedure, k indicate flash memory pages size (its
Value is 2aBit, wherein a can be the natural number more than or equal to 9 and less than or equal to 14), r indicates code rate, value range
Between 0.75 to 0.95；
Specifically, the matrix with cyclic shift characteristic means that the next line of the matrix can be by the lastrow of matrix
Cyclic shift obtains.
The advantages of this step is: the test matrix with cyclic shift characteristic that flash controller generates is conducive to compile
The realization of code can reduce encoder complexity and save hardware spending.
(2) sending sequence write order, according to the sequence write order and using generation test matrix H in step (1) to length
For the bit sequence of nEncoded that (wherein coding rule is), to generate length
For the redundant digit of mAnd the bit sequence that coding will have been completedIt is transferred in page register；
Specifically,Indicate known bit sequence,Indicate unknown redundancy
Position, the length is m,WithCollectively form the bit sequence for having completed codingMj(1≤j≤k) indicates bit 0 or 1.
The advantages of this step is: when flash memory system sending sequence write order, bit sequence encoded is with sequential write
MSB pages of TLC nand flash memory is written in mode first, followed by CSB pages, is finally LSB page, is sequentially written in and advantageously reduces TLC
Nand flash memory channel noise interference, to reduce bit error rate.
(3) by the bit sequence in page registerIt is written to MSB pages of TLC nand flash memory, to other bit sequence
ColumnWithStep (2) are repeated respectively, and will be obtained
Complete the bit sequence of codingCSB pages of TLC nand flash memory is written, it willThe LSB page of TLC nand flash memory is written；
The advantages of this step, is: will first write the bring of congestion in bit sequence write-in register encoded with reduction
Etc. expense to be delayed；Furthermore it is possible to execute the sequence write order that flash memory system issues well, data are sequentially written in Hash memory pages
In.
(4) original bit sequence being stored in MSB pages, CSB pages and LSB page is extracted respectively WithDue to by
The interference of TLC nand flash memory channel noise and bit-errors occur and are formed by new bit sequenceWithJust
Beginning soft decision information, using belief propagation algorithm to new bit sequenceWithInitial soft decision information carry out LDPC decoding, to obtain the corresponding Soft Inform ation of decoding result,
The corresponding external information of LSB is obtained according to initial soft decision information Soft Inform ation corresponding with decoding result；
Specifically, can be standard minimum and (Normalized min-sum), layering using belief propagation algorithm
Minimum and (Layered min-sum) etc..
In the present invention, external information refers to using the error pattern extracted in TLC nand flash memory channel and initial
MSB soft decision information and initial CSB soft decision information optimize initial LSB soft decision information, and obtained more accurate LSB is soft to be sentenced
Certainly information, this information are referred to as the corresponding external information of LSB.
Specifically, including following step according to the error pattern that the three of extraction bit sequences extract TLC nand flash memory
It is rapid:
(4-1) obtains new bit sequence using detection levelInitial MSB soft sentence
Certainly informationInitial MSB soft decision information is carried out using belief propagation algorithm
LDPC decoding, to obtain the corresponding MSB Soft Inform ation of decoding result
(4-2) obtains new bit sequence using detection levelInitial CSB soft-decision letter
BreathLDPC is carried out to initial CSB soft decision information using belief propagation algorithm to translate
Code, to obtain the corresponding CSB Soft Inform ation of decoding result
The initial MSB soft decision information that (4-3) is obtained according to step (4-1) MSB Soft Inform ation corresponding with decoding result, with
And the initial CSB soft decision information CSB Soft Inform ation corresponding with decoding result that step (4-2) obtains is to new bit sequenceInitial LSB soft decision informationIt is handled, to obtain
The corresponding external information of LSBSpecifically:
1. if the corresponding MSB Soft Inform ation of decoding resultIn Rmj(1≤j≤n)
The CSB Soft Inform ation corresponding with decoding result greater than 0In Rcj(1≤j≤n) be greater than 0, and
Initial MSB soft decision informationInGreater than 0 and initial CSB is soft
Discriminative informationInGreater than 0, then the LSB bit value read has biggish
Probability is correctly, during LDPC decoding, the external information value of LSB to be arrangedInFor new bit sequenceInitial LSB soft decision informationIn2.5 times, i.e.,
2. if the corresponding MSB Soft Inform ation of decoding resultIn Rmj(1≤j≤n)
Greater than 0, initial MSB soft decision informationInGreater than 0, and translate
The corresponding CSB Soft Inform ation of code resultIn Rcj(1≤j≤n) is multiplied by initial CSB soft-decision
InformationInLess than 0, i.e.,It is then original
LSB bit value a possibility that being 1 it is larger, during LDPC decoding, the external information value of LSB is setInIt is 2, i.e.,To rapidly make LSB ratio
Paricular value converges to bit 1；
3. if the corresponding MSB Soft Inform ation of decoding resultIn Rmj(1≤j≤n)
Less than 0, initial MSB soft decision informationInLess than 0, and translate
The corresponding CSB Soft Inform ation of code resultIn Rcj(1≤j≤n) is multiplied by initial CSB soft-decision
InformationInLess than 0, i.e.,It is then original
LSB bit value a possibility that being 1 it is larger, during the decoding of LDPC, the external information value of LSB is setInIt is 2, i.e.,To rapidly make LSB bit
Value converges to bit 1；
4. if the corresponding MSB Soft Inform ation of decoding resultIn Rmj(1≤j≤n)
Multiplied by initial MSB soft decision informationInLess than 0, i.e.,Decode the corresponding CSB Soft Inform ation of resultIn Rcj
(1≤j≤n) is greater than 0, and initial CSB soft decision informationInGreatly
In 0, then it is bit 0 that original LSB bit value, which has biggish probability, and during the decoding of LDPC, the external letter of LSB is arranged
Breath valueInIt is -2, i.e.,To rapidly make LSB
Bit value converges to bit 0；
5. if the corresponding MSB Soft Inform ation of decoding resultIn Rmj(1≤j≤n)
Multiplied by initial MSB soft decision informationInLess than 0, i.e.,And the corresponding CSB Soft Inform ation of decoding resultIn Rcj(1
≤ j≤n) multiplied by initial CSB soft decision informationInLess than 0, i.e.,The LSB bit value then read have biggish probability be correctly, during the decoding of LDPC,
The external information value of LSB is setInFor new bit sequenceInitial LSB soft decision informationIn
2.5 times, i.e.,
The advantages of this step, is: the bit sequence that mistake occurs is labeled asWithBe conducive to distinguish original
Stored bit sequence；In addition, by the error pattern of the TLC nand flash memory of extraction and initial MSB and CSB soft decision information
MSB and CSB Soft Inform ation corresponding with decoding result optimizes initial LSB soft decision information and obtains needed for more accurate LDPC decoding
The LSB external information wanted is conducive to improve LDPC decoding judgement precision, one can be done to the correctness of read bit fastly
Judge fastly.
Initial MSB soft decision information, initial CSB soft decision information and initial LSB soft decision information are by following formula
It is calculated；
Wherein L (MSB), L (CSB) and L (LSB) respectively indicate initial MSB soft decision information, initial soft CSB discriminative information
With initial LSB soft decision information,Expression is the probability density distribution of the threshold voltage of TLC nand flash memory cell, and is taken
From normal distribution, V1And V2Respectively indicate the reference voltage lower limit value and upper limit value of detection level.
If initial soft decision information is greater than 0, corresponding bit value is 1.If initially soft decision information is less than 0,
Bit value is 0.
(5) the corresponding external information of LSB is decoded using belief propagation algorithm, decoding latency is counted,
And host side is sent by decoding latency and decoding result.
The advantages of this step is: the corresponding external information of LSB is optimized soft decision information, to external information
It carries out decoding to be conducive to improve decoding speed and performance, statistical decoding postpones the promotion that can be well reflected out decoding performance.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should all include
Within protection scope of the present invention.
Claims (7)
1. a kind of method for promoting LDPC decoding performance based on flash memory error pattern, is applied in flash memory system, feature
It is, the described method comprises the following steps:
(1) generating has cyclic shift characteristic and element for 0 and 1 test matrix H, and wherein the size of the matrix H is m × n, and
0 number of elements is greater than 1 number of elements, wherein m=n (1-r), and m indicates the redundant digit to be generated in an encoding process, and
The code word size to be generated during n=k/r, n presentation code, k indicate flash memory pages size, and r indicates code rate；
(2) sending sequence write order is n's to length according to the sequence write order and using test matrix H is generated in step (1)
Bit sequenceIt is encoded, to generate length as the redundant digit of m
And the bit sequence that coding will have been completedIt is transferred in page register；
(3) by the bit sequence in page registerIt is written to MSB pages of TLC nand flash memory, to other bit sequenceWithIt repeats respectively step (2), and complete by what is obtained
At the bit sequence of codingCSB pages of TLC nand flash memory is written, it willThe LSB page of TLC nand flash memory is written；
(4) original bit sequence being stored in MSB pages, CSB pages and LSB page is extracted respectively WithDue to by TLC
The interference of nand flash memory channel noise and bit-errors occur and are formed by new bit sequenceWithJust
Beginning soft decision information, using belief propagation algorithm to new bit sequenceWithInitial soft decision information carry out LDPC decoding, to obtain the corresponding soft letter of decoding result
Breath obtains the corresponding external information of LSB according to initial soft decision information Soft Inform ation corresponding with decoding result；Root in step (4)
Include following sub-step according to the error pattern that three bit sequences of extraction extract TLC nand flash memory:
(4-1) obtains new bit sequence using detection levelInitial MSB soft-decision letter
BreathLDPC is carried out to initial MSB soft decision information using belief propagation algorithm
Decoding, to obtain the corresponding MSB Soft Inform ation of decoding result
(4-2) obtains new bit sequence using detection levelInitial CSB soft decision informationLDPC decoding is carried out to initial CSB soft decision information using belief propagation algorithm,
To obtain the corresponding CSB Soft Inform ation of decoding result
(4-3) is according to the initial MSB soft decision information MSB Soft Inform ation corresponding with decoding result that step (4-1) obtains, Yi Jibu
Suddenly the initial CSB soft decision information that (4-2) is obtained CSB Soft Inform ation corresponding with decoding result is to new bit sequenceInitial LSB soft decision informationIt is handled, to obtain
The corresponding external information of LSBStep (4-3) specifically:
If decoding the corresponding MSB Soft Inform ation of resultIn RmjGreater than 0 and decoding result pair
The CSB Soft Inform ation answeredIn RcjGreater than 0, and initial MSB soft decision informationInGreater than 0 and initial CSB soft decision information
InGreater than 0, then it is correctly, during LDPC decoding, LSB to be arranged that the LSB bit value read, which has biggish probability,
External information valueInFor new bit sequence
Initial LSB soft decision informationIn2.5 times, i.e.,Its
In 1≤j≤n；
If decoding the corresponding MSB Soft Inform ation of resultIn RmjGreater than 0, initial MSB
Soft decision informationInGreater than 0, and decode the corresponding CSB Soft Inform ation of resultIn RcjMultiplied by initial CSB soft decision information
InLess than 0, i.e.,A possibility that then original LSB bit value is 1 is larger, during LDPC decoding, if
Set the external information value of LSBInIt is 2, i.e.,To rapidly make LSB ratio
Paricular value converges to bit 1；
If decoding the corresponding MSB Soft Inform ation of resultIn Rmj(1≤j≤n) less than 0,
Initial MSB soft decision informationInLess than 0, and decode the corresponding CSB of result
Soft Inform ationIn RcjMultiplied by initial CSB soft decision information
InLess than 0, i.e.,A possibility that then original LSB bit value is 1 is larger, during the decoding of LDPC,
The external information value of LSB is setInIt is 2, i.e.,To rapidly make LSB
Bit value converges to bit 1；
If decoding the corresponding MSB Soft Inform ation of resultIn Rmj(1≤j≤n) multiplied by
Initial MSB soft decision informationInLess than 0, i.e.,Decoding knot
The corresponding CSB Soft Inform ation of fruitIn RcjGreater than 0, and initial CSB soft decision informationInGreater than 0, then it is bit 0 that original LSB bit value, which has biggish probability,
During the decoding of LDPC, the external information value of LSB is setInIt is -2, i.e.,To rapidly make LSB bit value converge to bit 0；
If decoding the corresponding MSB Soft Inform ation of resultIn RmjMultiplied by initial MSB soft-decision
InformationInLess than 0, i.e.,And the corresponding CSB of decoding result is soft
InformationIn RcjMultiplied by initial CSB soft decision information
InLess than 0, i.e.,It is correctly, in the decoding of LDPC that the LSB bit value then read, which has biggish probability,
In the process, the external information value of LSB is setInFor new bit sequenceInitial LSB soft decision informationIn's
2.5 times, i.e.,
(5) the corresponding external information of LSB is decoded using belief propagation algorithm, decoding latency is counted, and will
Decoding latency and decoding result are sent to host side.
2. the method according to claim 1, wherein flash memory pages size is equal to 2aBit, wherein a be greater than etc.
In 9 and be less than or equal to 14 natural number), the value range of r is between 0.75 to 0.95.
3. the method according to claim 1, wherein the coding rule in step (2) is
4. the method according to claim 1, whereinIndicate known bit sequence,Indicate unknown redundant digit, the length is m,WithCollectively form the bit sequence for having completed coding
Column
5. the method according to claim 1, wherein belief propagation algorithm is that standard is minimum and/or layering is minimum
And algorithm.
6. the method according to claim 1, wherein initial MSB soft decision information, initial CSB soft decision information
It with initial LSB soft decision information is calculated by following formula；
Wherein L (MSB), L (CSB) and L (LSB) respectively indicate initial MSB soft decision information, initial soft CSB discriminative information and just
Beginning LSB soft decision information,Expression is the probability density distribution of the threshold voltage of TLC nand flash memory cell, and is obeyed just
State distribution, V1And V2Respectively indicate the reference voltage lower limit value and upper limit value of detection level.
7. a kind of system for promoting LDPC decoding performance based on flash memory error pattern, is applied in flash memory system, feature
It is, the system comprises:
First module, for generating the test matrix H that with cyclic shift characteristic and element is 0 and 1, wherein the matrix H is big
Small is m × n, and 0 number of elements be greater than 1 number of elements, wherein m=n (1-r), m expression to be generated in an encoding process
Redundant digit, and n=k/r, n presentation code during the code word size to be generated, k indicate flash memory pages size, r expression code
Rate；
Second module is used for sending sequence write order, according to the sequence write order and uses generation test matrix H in step (1)
The bit sequence for being n to lengthIt is encoded, to generate length as the redundant digit of mAnd the bit sequence that coding will have been completedIt is transferred in page register；
Third module, for by the bit sequence in page registerIt is written to MSB pages of TLC nand flash memory, to other
Bit sequenceWithStep (2) are repeated respectively, and will be obtained
Completed coding bit sequenceCSB pages of TLC nand flash memory is written, it willThe LSB page of TLC nand flash memory is written；
4th module, for extracting the original bit sequence being stored in MSB pages, CSB pages and LSB page respectivelyWithBy
Bit-errors occur and are formed by new bit sequence in the interference by TLC nand flash memory channel noiseWithIt is initial soft
Discriminative information, using belief propagation algorithm to new bit sequenceWithInitial soft decision information carry out LDPC decoding, to obtain the corresponding soft letter of decoding result
Breath obtains the corresponding external information of LSB according to initial soft decision information Soft Inform ation corresponding with decoding result；Root in 4th module
Include following submodule according to the error pattern that three bit sequences of extraction extract TLC nand flash memory:
First submodule, for obtaining new bit sequence using detection levelIt is initial
MSB soft decision informationInitial MSB soft-decision is believed using belief propagation algorithm
Breath carries out LDPC decoding, to obtain the corresponding MSB Soft Inform ation of decoding result
Second submodule, for obtaining new bit sequence using detection levelInitial CSB it is soft
Discriminative informationInitial CSB soft decision information is carried out using belief propagation algorithm
LDPC decoding, to obtain the corresponding CSB Soft Inform ation of decoding result
Third submodule, the initial MSB soft decision information MSB corresponding with decoding result for being obtained according to the first submodule are soft
The initial CSB soft decision information that information and second submodule obtain CSB Soft Inform ation corresponding with decoding result is to new bit sequence
ColumnInitial LSB soft decision informationIt is handled, to obtain
The corresponding external information of LSBThird submodule specifically:
If decoding the corresponding MSB Soft Inform ation of resultIn RmjGreater than 0 and decoding result pair
The CSB Soft Inform ation answeredIn RcjGreater than 0, and initial MSB soft decision informationInGreater than 0 and initial CSB soft decision informationInGreater than 0, then it is correct that the LSB bit value read, which has biggish probability,
, during LDPC decoding, the external information value of LSB is setInFor new bit
SequenceInitial LSB soft decision informationIn2.5 times, i.e.,Wherein 1≤j≤n；
If decoding the corresponding MSB Soft Inform ation of resultIn RmjGreater than 0, initial MSB
Soft decision informationInGreater than 0, and decode the corresponding CSB Soft Inform ation of resultIn RcjMultiplied by initial CSB soft decision information
InLess than 0, i.e.,A possibility that then original LSB bit value is 1 is larger, during LDPC decoding, if
Set the external information value of LSBInIt is 2, i.e.,To rapidly make LSB ratio
Paricular value converges to bit 1；
If decoding the corresponding MSB Soft Inform ation of resultIn Rmj(1≤j≤n) less than 0,
Initial MSB soft decision informationInLess than 0, and decode the corresponding CSB of result
Soft Inform ationIn RcjMultiplied by initial CSB soft decision informationInLess than 0, i.e.,Then original LSB bit value is 1 possibility
Property is larger, and during the decoding of LDPC, the external information value of LSB is arrangedInFor
2, i.e.,To rapidly make LSB bit value converge to bit 1；
If decoding the corresponding MSB Soft Inform ation of resultIn Rmj(1≤j≤n) multiplied by
Initial MSB soft decision informationInLess than 0, i.e.,Decoding knot
The corresponding CSB Soft Inform ation of fruitIn RcjGreater than 0, and initial CSB soft decision informationInGreater than 0, then it is bit 0 that original LSB bit value, which has biggish probability,
During the decoding of LDPC, the external information value of LSB is setInIt is -2, i.e.,To rapidly make LSB bit value converge to bit 0；
If decoding the corresponding MSB Soft Inform ation of resultIn RmjMultiplied by initial MSB soft-decision
InformationInLess than 0, i.e.,And the corresponding CSB of decoding result
Soft Inform ationIn RcjMultiplied by initial CSB soft decision information
InLess than 0, i.e.,It is correctly, in the decoding of LDPC that the LSB bit value then read, which has biggish probability,
In the process, the external information value of LSB is setInFor new bit sequenceInitial LSB soft decision informationIn's
2.5 times, i.e.,
5th module carries out decoding latency for being decoded using belief propagation algorithm to the corresponding external information of LSB
Statistics, and host side is sent by decoding latency and decoding result.
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