CN107369678A - A kind of system-in-a-package method and its encapsulation unit - Google Patents
A kind of system-in-a-package method and its encapsulation unit Download PDFInfo
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- CN107369678A CN107369678A CN201610312643.9A CN201610312643A CN107369678A CN 107369678 A CN107369678 A CN 107369678A CN 201610312643 A CN201610312643 A CN 201610312643A CN 107369678 A CN107369678 A CN 107369678A
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- chip
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- stacked dies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of system-in-a-package method and its encapsulation unit.Wherein, methods described includes：Capacity cell and resistive element are independently arranged, forms capacitance resistance array；By predetermined packing forms, some really excellent chips are formed；Capacitance resistance array described in storehouse and really excellent chip are to form the first 3D stacked dies；Using the array comprising active device and the integrated circuit of different fabrication techniques as the second nude film, with remaining the 2nd 3D stacked dies of excellent chip-stacked formation really；It is system in package unit by first and second described 3D stacked die and multi-chip package unit and multi-chip modules assembling.The above-mentioned method for packing being independently arranged, using the teaching of the invention it is possible to provide more preferable IC design flexibilitys and reliability.And active component and a variety of IC the second nude film are further developed, together with other really excellent chip, as layer stack into system in package unit, without using printed circuit board (PCB), can further reduce cost and volume.
Description
Technical field
The present invention relates to chip encapsulation technology field, more particularly to a kind of system-in-a-package method and its encapsulation unit.
Background technology
During traditional chip package, IC products can be assemblied in various encapsulation by a variety of different packaged types
In structure.Then, it is loaded into box or module, forms the final product that dispatches from the factory.And with the continuous development of technology, market
The requirement more and more higher of integrated level and volume for IC products.Thus, based on new multi-chip package and modular technology
Occur (MCP, MCM etc.) so that can be set in single module, integrate more components.
And system in package (SIP) is recent state-of-the-art technology, a variety of different components can be installed to one it is public
In substrate, multiple functional modules are integrated on one chip, and are connected with each other, play system level function.
But during existing system in package, because the integrated level of component is very high, needed between each functional module
The layout designs of complexity are carried out, coordinates and avoids interference that may be present between element.The time of IC designs is longer, spirit
Active deficiency, causes the manufacturing time of product and cost higher.
Therefore, prior art is also to be developed.
The content of the invention
In view of in place of above-mentioned the deficiencies in the prior art, it is an object of the invention to provide a kind of system-in-a-package method and its
Encapsulation unit, it is intended to solve the complex designing of system in package in the prior art, the problem of manufacturing cost is high.
In order to achieve the above object, this invention takes following technical scheme：
A kind of system-in-a-package method, wherein, the system-in-a-package method includes：
Capacity cell and resistive element are independently arranged, forms capacitance resistance array；
By predetermined packing forms, some really excellent chips are formed；
Capacitance resistance array described in storehouse and really excellent chip are to form the first 3D stacked dies；
It is and remaining using the array comprising active device and the integrated circuit of different fabrication techniques as the second nude film
Really the 2nd 3D stacked dies of excellent chip-stacked formation；
It is system-level envelope by first and second described 3D stacked die and multi-chip package unit and multi-chip modules assembling
Fill unit.
Described system-in-a-package method, wherein, the method for the formation 3D stacked dies includes：
Dielectric isolation layer is set between really excellent chip and the capacitance resistance array；
According to predetermined design requirement, the metal level with corresponding line layout is set；
The capacitance resistance array and really excellent chip are connected by the through hole being arranged between dielectric isolation layer.
Described system-in-a-package method, wherein, using the 2nd 3D stacked dies as one layer, storehouse to system-level envelope
Fill in unit.
Described system-in-a-package method, wherein, the capacitance resistance array includes what is be arranged in order, has different resistance
Some resistive elements of value and some capacity cells with different capacitances；
According to predetermined chip layout design between the capacity cell and resistive element, arranges value and electricity corresponding to formation
Hold the connection between element or resistive element.
A kind of system in package unit, wherein, the system in package unit includes at least one electric capacity as described above
Electric resistance array.
Beneficial effect：A kind of system-in-a-package method and its encapsulation unit provided by the invention, by large bulk capacitance, resistance
Or the high interference element and peripheral circuit element of inductance etc. are independently arranged, and turn into independent one layer in the first 3D stacked dies,
During SIP can simplified topology and lifting Anti-interference Design, effectively save space, improve performance.
In addition, the above-mentioned method for packing for being independently arranged capacitance resistance array, using the teaching of the invention it is possible to provide more preferable IC design flexibilitys and
Reliability, the development structure of this array is simple, and processing cost is low, and layout method is flexible, can be good at being applied.
And it is further to develop active component and a variety of IC the second nude film using the method for being independently set to one layer,
Together with other really excellent chip, as layer stack into system in package unit, without using printed circuit board (PCB), Neng Goujin
The reduction cost and volume of one step.
Brief description of the drawings
Fig. 1 is the instantiation schematic diagram of existing system-in-a-package method.
Fig. 2 is the method flow diagram of the system-in-a-package method of the specific embodiment of the invention.
Fig. 3 is the structural representation of the first 3D stacked dies of the system-in-a-package method of the specific embodiment of the invention.
Fig. 4 is the structural representation of the resistance capacitance array of the system-in-a-package method of the specific embodiment of the invention.
Fig. 5 is the structural representation of the 2nd 3D stacked dies of the system-in-a-package method of the specific embodiment of the invention.
Embodiment
The present invention provides a kind of system-in-a-package method and its encapsulation unit.For make the purpose of the present invention, technical scheme and
Effect is clearer, clear and definite, and the present invention is described in more detail for the embodiment that develops simultaneously referring to the drawings.It should be appreciated that herein
Described specific embodiment only to explain the present invention, is not intended to limit the present invention.
As shown in figure 1, the assemble flow example for system in package (SIP) unit.Also a variety of IC products (had into spy
Determine the module or chip of function), discrete component (electric capacity, resistance, active component etc.) and multi-chip package (MCP) and multicore
Piece module (MCM) is assembled in a printed circuit board (PCB).
First, true excellent chip (Know Good Die KGD) is assembled into different encapsulation, for example, low profile J-
(its specifically used encapsulation shape such as lead (SOJ), quad flat package (QFP), pin grid array (PGA), ball grid array (BGA)
Formula depends on actual use demand or the requirement of client).
Some of which is positioned in less encapsulation (small with as KGD die sizes), so as to form chip chi
Very little encapsulation (CSP).And multiple CSP heaps are then installed to that a multi-chip package (MCP) is inner or multiple chip modules together
(MCM), it is assembled in system in package (SiP) unit.
Finally, all these IC chips, SIP and discrete component are installed on printed circuit board (PCB) (PCB), are had on circuit board
The metal wire (being used to connect all electronic systems) laid in advance, is finally placed in shell, forms consumer and be commonly seen most
Finished product.
As shown in figure 1, encapsulated type 1,2 and 3 is loaded into CSM and MCP respectively.In addition CSP, CSP and CSP, can be
BGA types encapsulate, and they are stacked together by ball bonding.In most cases, BGA is sealed with memory chip using identical
Dress.But in other cases, can be by the way of the mixing of Digital Logical Circuits, memory or analog chip.Unless in core
Piece design phase, engineer are designed using layout design tool to complete layout of metallic layer.
As shown in Fig. 2 the system-in-a-package method for the specific embodiment of the invention.Wherein, the system-in-a-package method
Including：
S1, capacity cell and resistive element are independently arranged, form capacitance resistance array.The capacitance resistance array is one
Several different electric capacity and resistive element are integrated on nude film, and corresponding connection end is provided and can customize the connection of programming.
S2, pass through predetermined packing forms, some really excellent chips of formation.
Capacitance resistance array described in S3, storehouse and really excellent chip are to form the first 3D stacked dies.
S4, using the array comprising active device and the integrated circuit of different fabrication techniques as the second nude film, it is and surplus
Remaining the 2nd 3D stacked dies of excellent chip-stacked formation really.
S5, first and second 3D stacked die and multi-chip package unit and multi-chip modules assembling are system-level by described in
Encapsulation unit.
It should be noted that the order of foregoing description can not be used to carry out in above-mentioned steps, can be according to actual conditions
It is adjusted, it is only necessary to the first 3D stacked dies and the 2nd 3D stacked dies corresponding to being formed, as one layer in SIP i.e.
The object of the invention can be achieved.
In system-in-a-package method of the present invention, can use with shown in Fig. 1, existing encapsulation process is identical
Or similar concrete operations flow (can specifically be determined according to actual conditions), difference, which is to employ, includes electric capacity
First 3D stacked dies of electric resistance array and the 2nd 3D stacked dies for including the second nude film.
Due to being arranged in these element independent sets in specific capacitance resistance array or the second nude film, in encapsulation process
Single one layer can be used as, it is possible thereby to further simplify design and occupy-place, reduces production cost.
Specifically, the method for the formation 3D stacked dies includes：
First, dielectric isolation layer is set between really excellent chip and the 3D stacked die.Then, according to predetermined design
It is required that metal level corresponding to setting and connecting the capacitance resistance array and really excellent core by through hole between dielectric isolation layer
Piece.
In the present embodiment, there is the KGD (i.e. KGD1, KGD2, KGD3, KGD4, KGD5, KGD6) of six kinds of different encapsulation.Such as
It is the schematic diagram of the specific embodiment of the first 3D stacked dies of the present invention, Fig. 5 is the 2nd 3D of the present invention shown in Fig. 3
The schematic diagram of the specific embodiment of stacked die.
Wherein, KGD1, KGD2, KGD3 and resistance capacitance array RCA are stacked.Be provided between each layer dielectric isolation layer P with
And metal level M.Connection can be realized between each layer by connecting through hole VIA.
Generally, KGD encapsulates with memory chip for identical.But sometimes can also use Digital Logical Circuits,
Way as memory or analog chip hybrid package.Unless in chip design stage, designer uses layout designs work
Have to provide the path of metal level connection.
Above-mentioned 3D stacked dies module and MCP1 and MCM are assembled in system in package (SIP) unit, then, with IC
Chip and miscellaneous discrete component (such as active device) together, are assembled on PCB, and finally all devices, which load in box, to be formed
Final products.Such mode can reduce the cost and volume of SIP encapsulation, simplified topology design.
2nd 3D stacked dies, which include one layer of nude film by including active device array, either has specific function,
The IC to be formed (unencapsulated) the second nude film DIE2 is processed using multiple technologies.
KGD4, KGD5, KGD6 and the second nude film DIE2 are stacked.It is similar, be provided between each layer dielectric isolation layer P with
And metal level M.Connection is realized by the connection through hole VIA being arranged in dielectric isolation layer between each layer.
By way of the 2nd 3D stacked dies are set, volume can be further reduced, realizes miniaturization and lifting system
System performance., as one layer, storehouse, without using pcb board, reduces cost and volume into system in package unit for it.
As shown in figure 4, the schematic diagram of the capacitance resistance array for the specific embodiment of the invention.It can include：Arrange successively
Row, some resistive elements with different resistance values and some capacity cells with different capacitances.Electric capacity C and resistance R
Specific region is taken respectively.
According to predetermined chip layout design between the capacity cell and resistive element, arranges value and electricity corresponding to formation
Hold the connection between element or resistive element.
It as shown in figure 4, the structure of the capacitance resistance array is simple, can use existing, lower-cost chip adds
Work technology is quickly manufactured and (in general, completed using more than 1U low resolution and the mask step no more than 6).
In actual manufacturing process, a variety of different types of elements can be integrated on substrate, are selected according to the demand of reality
Resistance value and capacitance corresponding to selecting.Use existing suitable instrument, there is provided customized programmable metallization connection configuration (foundation
User or the needs of actual conditions).
Such capacitance resistance array, electric capacity and resistance value that almost all needs, the process technology used can be included
Simply, there is provided electric capacity, the resistance option of a variety of various combinations, be built on relatively small nude film, there is low-down cost.
Its overall development is simple in construction, and processing cost is low, and layout method is flexible.
Said system level packaging methods, pass through simplified topology and Anti-interference Design and parts processed (such as bulky capacitor, ohmic leakage
Device or inductance) method, the storehouse IC nude films in SIP environment, with save space and improve performance.In addition, resistance capacitance array
(RCA) method (and product) provides the flexibility of IC designs and more preferable reliability, while saves what is assembled and manufacture
Time and cost.And space-consuming can be reduced using capacitance resistance array, so as to reduce the size of final products, and it is group
The further integration and improvement of dress product create space.
Present invention also offers a kind of system in package unit.Wherein, the system in package unit includes at least one
Capacitance resistance array as described above.
This system-in-a-package method and encapsulation unit based on capacitance resistance array can reduce the complexity of encapsulation, carry
High reliability, reduce footprint and reduce cost.State-of-the-art design, processing and package technique are integrated, height can be produced
The SIP of level, can be applied to a variety of electronic terminal products.
It is understood that for those of ordinary skills, can be with technique according to the invention scheme and this hair
Bright design is subject to equivalent substitution or change, and all these changes or replacement should all belong to the guarantor of appended claims of the invention
Protect scope.
Claims (5)
1. a kind of system-in-a-package method, it is characterised in that the system-in-a-package method includes：
Capacity cell and resistive element are independently arranged, forms capacitance resistance array；
By predetermined packing forms, some really excellent chips are formed；
Capacitance resistance array described in storehouse and really excellent chip are to form the first 3D stacked dies；
It is really excellent with residue using the array comprising active device and the integrated circuit of different fabrication techniques as the second nude film
The 2nd 3D stacked dies of chip-stacked formation；
It is system in package list by first and second described 3D stacked die and multi-chip package unit and multi-chip modules assembling
Member.
2. system-in-a-package method according to claim 1, it is characterised in that the method bag of the formation 3D stacked dies
Include：
Dielectric isolation layer is set between really excellent chip and the capacitance resistance array；
According to predetermined design requirement, the metal level with corresponding line layout is set；
The capacitance resistance array and really excellent chip are connected by the through hole being arranged between dielectric isolation layer.
3. system-in-a-package method according to claim 1, it is characterised in that using the 2nd 3D stacked dies as one
Layer, storehouse is into system in package unit.
4. system-in-a-package method according to claim 1, it is characterised in that the capacitance resistance array includes arranging successively
Row, some resistive elements with different resistance values and some capacity cells with different capacitances；
According to predetermined chip layout design between the capacity cell and resistive element, arranges value corresponding to formation and electric capacity member
Connection between part or resistive element.
5. a kind of system in package unit, it is characterised in that the system in package unit includes at least one such as claim
1-4 any described the first 3D stacked dies and the 2nd 3D stacked dies.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610312643.9A CN107369678A (en) | 2016-05-13 | 2016-05-13 | A kind of system-in-a-package method and its encapsulation unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610312643.9A CN107369678A (en) | 2016-05-13 | 2016-05-13 | A kind of system-in-a-package method and its encapsulation unit |
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| CN107369678A true CN107369678A (en) | 2017-11-21 |
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| CN201610312643.9A Pending CN107369678A (en) | 2016-05-13 | 2016-05-13 | A kind of system-in-a-package method and its encapsulation unit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115274645A (en) * | 2022-07-01 | 2022-11-01 | 苏州吾爱易达物联网有限公司 | System-in-package SIP chip and test method thereof |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316102A (en) * | 1998-06-02 | 2001-10-03 | 薄膜电子有限公司 | Data storage processing apparatus, and method for fabricating |
| CN1739197A (en) * | 2003-10-22 | 2006-02-22 | 大动力有限公司 | DC-DC converter implemented in a land grid array package |
| CN101000876A (en) * | 2006-12-31 | 2007-07-18 | 徐中祐 | Bare chip building block packaging method |
| CN101199434A (en) * | 2006-12-11 | 2008-06-18 | 通用电气公司 | Modular sensor assembly and methods of fabricating the same |
| CN102106194A (en) * | 2006-12-14 | 2011-06-22 | 英特尔公司 | Ceramic package substrate with recessed device |
| CN102341899A (en) * | 2009-03-06 | 2012-02-01 | 优特香港有限公司 | Leadless array plastic package with various ic packaging configurations |
| CN102763217A (en) * | 2010-02-10 | 2012-10-31 | 高通股份有限公司 | Semiconductor die package structure |
| CN104269388A (en) * | 2010-12-22 | 2015-01-07 | 美国亚德诺半导体公司 | Vertically Integrated Systems |
| CN105474391A (en) * | 2013-08-09 | 2016-04-06 | 苹果公司 | Multi-die fine grain integrated voltage regulation |
-
2016
- 2016-05-13 CN CN201610312643.9A patent/CN107369678A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316102A (en) * | 1998-06-02 | 2001-10-03 | 薄膜电子有限公司 | Data storage processing apparatus, and method for fabricating |
| CN1739197A (en) * | 2003-10-22 | 2006-02-22 | 大动力有限公司 | DC-DC converter implemented in a land grid array package |
| CN101199434A (en) * | 2006-12-11 | 2008-06-18 | 通用电气公司 | Modular sensor assembly and methods of fabricating the same |
| CN102106194A (en) * | 2006-12-14 | 2011-06-22 | 英特尔公司 | Ceramic package substrate with recessed device |
| CN101000876A (en) * | 2006-12-31 | 2007-07-18 | 徐中祐 | Bare chip building block packaging method |
| CN102341899A (en) * | 2009-03-06 | 2012-02-01 | 优特香港有限公司 | Leadless array plastic package with various ic packaging configurations |
| CN102763217A (en) * | 2010-02-10 | 2012-10-31 | 高通股份有限公司 | Semiconductor die package structure |
| CN104269388A (en) * | 2010-12-22 | 2015-01-07 | 美国亚德诺半导体公司 | Vertically Integrated Systems |
| CN105474391A (en) * | 2013-08-09 | 2016-04-06 | 苹果公司 | Multi-die fine grain integrated voltage regulation |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115274645A (en) * | 2022-07-01 | 2022-11-01 | 苏州吾爱易达物联网有限公司 | System-in-package SIP chip and test method thereof |
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