CN107369653A - A kind of system-in-a-package method of high interference component, structure and separation array structure - Google Patents

A kind of system-in-a-package method of high interference component, structure and separation array structure Download PDF

Info

Publication number
CN107369653A
CN107369653A CN201610312645.8A CN201610312645A CN107369653A CN 107369653 A CN107369653 A CN 107369653A CN 201610312645 A CN201610312645 A CN 201610312645A CN 107369653 A CN107369653 A CN 107369653A
Authority
CN
China
Prior art keywords
package
package method
separation
array
separation array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610312645.8A
Other languages
Chinese (zh)
Inventor
萧建成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
China Power Grid (beijing) Dsy Technology Ltd
BEIJING CHINA ECNET CO LTD
Original Assignee
China Power Grid (beijing) Dsy Technology Ltd
BEIJING CHINA ECNET CO LTD
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by China Power Grid (beijing) Dsy Technology Ltd, BEIJING CHINA ECNET CO LTD filed Critical China Power Grid (beijing) Dsy Technology Ltd
Priority to CN201610312645.8A priority Critical patent/CN107369653A/en
Publication of CN107369653A publication Critical patent/CN107369653A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)

Abstract

The invention discloses a kind of system-in-a-package method and its encapsulating structure of high interference component.Wherein, the system-in-a-package method includes：The inductor of component and/or antenna are separated, integrate the separation array being arranged to comprising multiple inductors and/or antenna element；The nude film of the separation array is manufactured by low temperature assembly technology；According to default processing procedure, system in package is carried out.By the high interference component in independent separation IC, using the setting of separation array, it is positioned in single nude film, can be good at reducing production cost, there is provided more preferable unfailing performance.It is additionally, since footprints reduction so that final encapsulating products are minimized, and space is provided for further integrated assembling.

Description

A kind of system-in-a-package method of high interference component, structure and separation array structure
Technical field
The present invention relates to System-in-Package technology field, more particularly to a kind of system-in-a-package method of high interference component, Structure and separation array structure.
Background technology
With the continuous progress of packaging and testing technology, the combination of various high voltages, low-voltage IC, discrete is active/nothing Source element can be easily integrated in an encapsulating structure, i.e. system in package (SIP).
At present, existing state-of-the-art encapsulating structure is 25 μm thin mould, panel (mould bases), redistributing layer (RDL) and generally acknowledged Good chips (KGD).Outstanding encapsulation technology can at most stack 16 nude films (Die) in an encapsulating structure.
But in general, as shown in figure 1, the antenna part on metal level would generally be included on existing RF chip layouts (i.e. inductance coil).In order to prevent electromagnetic interference, it forbids overlapping with other working regions, so, can cause chip area Waste (area more than 20% can not use).
In addition, inductor or antenna traces used in many Vertical collection communication systems can be arranged on it is complicated and intensive IC chip in (need to be placed in glitch-free environment, such as faraday cup), such structure setting can take substantial amounts of nude film face Product.It is further to influence addible die count on per wafer in the case where considering design and processing factors, add The burden of production, cause rise of total system production cost etc..
Therefore, prior art is also to be developed.
The content of the invention
In view of in place of above-mentioned the deficiencies in the prior art, it is an object of the invention to provide a kind of the system-level of high interference component Method for packing, structure and separation array structure, it is intended to which high interference modular construction occupancy die area is more in the prior art for solution, is The problem of system encapsulation production cost is high.
In order to achieve the above object, this invention takes following technical scheme：
A kind of system-in-a-package method of high interference component, wherein, the system-in-a-package method includes：
The inductor of component and/or antenna are separated, integrate point being arranged to comprising multiple inductors and/or antenna element From array；
The nude film of the separation array is manufactured by low temperature assembly technology；
According to default processing procedure, system in package is carried out.
Described system-in-a-package method, wherein, the low temperature assembly technology includes：
Be placed in oxide/polymer is heavy at the top of the metal level of substrate, by mask formed the first predetermined connection end and First through hole；
Heavy metal of putting on substrate, being filled in the through hole, and with the metal level good contact；
By chemical etching, unnecessary deposited metal and oxide or polymer are removed, forms predetermined metal interconnection layer；
Sunk on the metal interconnection layer and put oxide/polymer, and form the second predetermined through hole；
Another metal interconnection layer is formed using RDL and chemical etching, as second connection end.
Described system-in-a-package method, wherein, one or more inductor and/or antenna element of the separation array Part is attached by the RDL programmings of metal interconnection layer.
Described system-in-a-package method, wherein, the oxide/polymer includes polyimides.
One kind separation array structure, wherein, the separation array structure includes some inductors and/or day set in length and breadth The element of line；
The first and second connection ends included for connection of the element.
A kind of system-in-package structure, wherein, the system-in-package structure includes separation battle array as claimed in claim 1 The nude film of row.
Beneficial effect：System-in-a-package method, structure and the separation array structure of high interference component provided by the invention, lead to The high interference component crossed in independent separation IC, using the setting of separation array, it is positioned in single nude film, can be very Good reduction production cost, there is provided more preferable unfailing performance.It is additionally, since footprints reduction so that final encapsulating products Minimized, space is provided for further integrated assembling.
Brief description of the drawings
Fig. 1 is RF chip layouts schematic diagram of the prior art.
Fig. 2 is the method flow diagram of the system-in-a-package method of the specific embodiment of the invention.
Fig. 3 is the process chart of the low temperature assembly technology of the system-in-a-package method of the specific embodiment of the invention.
Fig. 4 is the schematic diagram of the separation array of the specific embodiment of the invention.
Fig. 5 is the SIP packaging technology flow figures of the specific embodiment of the invention.
Embodiment
System-in-a-package method, structure and the separation array structure of high interference component provided by the invention.To make the present invention Purpose, technical scheme and effect it is clearer, clear and definite, the embodiment that develops simultaneously referring to the drawings to the present invention further specifically It is bright.It should be appreciated that specific embodiment described herein is not intended to limit the present invention only to explain the present invention.
As shown in Fig. 2 the specific embodiment of the system-in-a-package method for the high interference component of the present invention.It is described system-level Method for packing can include：
S1, the inductor of component and/or antenna separated, be independently set to include multiple inductors and/or antenna element Separation array.
S2, the nude film by the low temperature assembly technology manufacture separation array.The low temperature assembly technology refers to and routine The relative techniques of high temperature semiconductors technology production IC.With the assembling of lower temperature to establish outer member, can avoid in IC More step and extra mask are used in manufacturing process, causes unnecessary EM waveform interference problems.
S3, according to default processing procedure, carry out system in package.
As shown in figure 1, in the design of existing chip, inductor/antenna traces and EM insulators almost account for whole The a quarter of individual die size, occupy the expensive real estate in chip, in submicron technology there is it is very big the problem of.
And in above-mentioned method for packing, assemble the component of high interference type using the separation array being independently arranged or have Source device, and technique carries out SIP encapsulation corresponding to use, can reduce footprints.Separation array is additionally, since independently to set Put, can be designed for IC and more preferable flexibility and reliability are provided, moreover it is possible to the further time cost for reducing assembling and manufacture.
Specifically, as shown in figure 3, the low temperature assembly technology may include steps of：
S21, it is placed in oxide/polymer is heavy at the top of substrate S metal level M.It can be delineated by mask, form connection Contact (i.e. first through hole VIA1).Then the heavy anti-light material put is exposed, make corresponding to it is zone-hardened after, carry out chemistry Processing, goes unless hardening region.These hardening regions are the first connection end of predetermined inductance/antenna.It is it is preferred that described Oxide/polymer is polyimides, so as to shield electromagnetic interference.
S22, heavy aluminium/metal of putting at the top of the substrate for completing step S21, make its fill the first through hole VIA1 and with institute State the metal level good contact of substrate.
S23, to complete step S22 after substrate chemical etching, remove unnecessary deposited metal and oxide or polymer. The only default lead to the hole site of those next steps of residue and associated metal layout layer.
S24, the step S23 structural tops formed continue it is heavy put oxide/polymer, formed predetermined positioned at another layer The second through hole VIA2.Composition structure between first through hole VIA1 and the second through hole VIA2 is identical.
After the completion of the second through hole VIA2, RDL and chemical etching can be used to form another layer of metal wiring pattern, as The second connection end of inductance/antenna.
As shown in Figure 3 and Figure 4, it is the schematic diagram for separating array of the specific embodiment of the invention.After the completion of final assembling Separation array in, include inductor/antenna element (L1 to Ln) that multiple edges are set in length and breadth.The element includes providing First and second connection ends of connection, make it as outside antenna element.
Wherein, the RDL that one or more inductor of the separation array and/or antenna element pass through metal interconnection layer Programming is attached.
As shown in figure 5, it is a kind of assemble flow of system in package (SIP) provided by the invention.It applies above-mentioned separation Array, smaller szie, more preferable performance and more inexpensive device can be obtained.It includes multiple different KGD, and by its envelope Loaded in a system-in-package structure.Then, it is fixed on substrate and forms final product.
It is understood that for those of ordinary skills, can be with technique according to the invention scheme and this hair Bright design is subject to equivalent substitution or change, and all these changes or replacement should all belong to the guarantor of appended claims of the invention Protect scope.

Claims (6)

1. a kind of system-in-a-package method of high interference component, it is characterised in that the system-in-a-package method includes：
The inductor of component and/or antenna are separated, integrate the separation battle array being arranged to comprising multiple inductors and/or antenna element Row；
The nude film of the separation array is manufactured by low temperature assembly technology；
According to default processing procedure, system in package is carried out.
2. system-in-a-package method according to claim 1, it is characterised in that the low temperature assembly technology includes：
By the heavy metal level top for being placed in substrate of oxide/polymer, predetermined the first connection end and first is formed by mask Through hole；
Heavy metal of putting on substrate, being filled in the through hole, and with the metal level good contact；
By chemical etching, unnecessary deposited metal and oxide or polymer are removed, forms predetermined metal interconnection layer；
Sunk on the metal interconnection layer and put oxide/polymer, and form the second predetermined through hole；
Another metal interconnection layer is formed using RDL and chemical etching, as second connection end.
3. system-in-a-package method according to claim 2, it is characterised in that it is described separation array one or more Inductor and/or antenna element are attached by the RDL programmings of metal interconnection layer.
4. system-in-a-package method according to claim 2, it is characterised in that the oxide/polymer includes polyamides Imines.
5. one kind separation array structure, it is characterised in that it is described separation array structure include some inductors set in length and breadth and/ Or the element of antenna；
The first and second connection ends included for connection of the element.
6. a kind of system-in-package structure, it is characterised in that the system-in-package structure includes as claimed in claim 1 point From the nude film of array.
CN201610312645.8A 2016-05-13 2016-05-13 A kind of system-in-a-package method of high interference component, structure and separation array structure Pending CN107369653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610312645.8A CN107369653A (en) 2016-05-13 2016-05-13 A kind of system-in-a-package method of high interference component, structure and separation array structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610312645.8A CN107369653A (en) 2016-05-13 2016-05-13 A kind of system-in-a-package method of high interference component, structure and separation array structure

Publications (1)

Publication Number Publication Date
CN107369653A true CN107369653A (en) 2017-11-21

Family

ID=60303484

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610312645.8A Pending CN107369653A (en) 2016-05-13 2016-05-13 A kind of system-in-a-package method of high interference component, structure and separation array structure

Country Status (1)

Country Link
CN (1) CN107369653A (en)

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1369914A (en) * 2000-02-18 2002-09-18 阿尔卡塔尔公司 Packed integrated circuit
CN1383206A (en) * 2001-04-17 2002-12-04 卡西欧计算机株式会社 Semiconductor device
CN1711633A (en) * 2002-11-08 2005-12-21 皇家飞利浦电子股份有限公司 Flexible device and method of manufacturing the same
CN101305315A (en) * 2005-11-11 2008-11-12 株式会社半导体能源研究所 Layer having functionality, method for forming flexible substrate having the same and method for preparing semiconductor device
CN101390253A (en) * 2004-10-01 2009-03-18 L.皮尔·德罗什蒙 Ceramic antenna module and methods of manufacture thereof
CN101854203A (en) * 2008-12-31 2010-10-06 英特尔公司 Integrated array transmit/receive module
CN102013410A (en) * 2009-09-07 2011-04-13 上海宏力半导体制造有限公司 Inductance element and forming method thereof
CN102576657A (en) * 2009-10-08 2012-07-11 高通股份有限公司 Three dimensional inductor and transformer
CN103346144A (en) * 2013-07-05 2013-10-09 南开大学 Artificial magnetic conductor shaped like Chinese character 'jing' and used for 60GHz on-chip antenna and implement method
CN103782448A (en) * 2011-05-05 2014-05-07 英特尔公司 High performance glass-based 60 GHz/mm-wave phased array antennas and methods of making same
CN103779319A (en) * 2012-10-19 2014-05-07 英飞凌科技股份有限公司 Semiconductor package having integrated antenna and method for forming the same
CN104638008A (en) * 2013-11-14 2015-05-20 英飞凌科技股份有限公司 Transistor and tunable inductance
CN104716122A (en) * 2013-12-13 2015-06-17 英飞凌科技股份有限公司 Semiconductor package with integrated microwave component

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1369914A (en) * 2000-02-18 2002-09-18 阿尔卡塔尔公司 Packed integrated circuit
CN1383206A (en) * 2001-04-17 2002-12-04 卡西欧计算机株式会社 Semiconductor device
CN1711633A (en) * 2002-11-08 2005-12-21 皇家飞利浦电子股份有限公司 Flexible device and method of manufacturing the same
CN101390253A (en) * 2004-10-01 2009-03-18 L.皮尔·德罗什蒙 Ceramic antenna module and methods of manufacture thereof
CN101305315A (en) * 2005-11-11 2008-11-12 株式会社半导体能源研究所 Layer having functionality, method for forming flexible substrate having the same and method for preparing semiconductor device
CN101854203A (en) * 2008-12-31 2010-10-06 英特尔公司 Integrated array transmit/receive module
CN102013410A (en) * 2009-09-07 2011-04-13 上海宏力半导体制造有限公司 Inductance element and forming method thereof
CN102576657A (en) * 2009-10-08 2012-07-11 高通股份有限公司 Three dimensional inductor and transformer
CN103782448A (en) * 2011-05-05 2014-05-07 英特尔公司 High performance glass-based 60 GHz/mm-wave phased array antennas and methods of making same
CN103779319A (en) * 2012-10-19 2014-05-07 英飞凌科技股份有限公司 Semiconductor package having integrated antenna and method for forming the same
CN103346144A (en) * 2013-07-05 2013-10-09 南开大学 Artificial magnetic conductor shaped like Chinese character 'jing' and used for 60GHz on-chip antenna and implement method
CN104638008A (en) * 2013-11-14 2015-05-20 英飞凌科技股份有限公司 Transistor and tunable inductance
CN104716122A (en) * 2013-12-13 2015-06-17 英飞凌科技股份有限公司 Semiconductor package with integrated microwave component

Similar Documents

Publication Publication Date Title
CN103681367B (en) Method for packing and packaging
EP2549532B1 (en) Method of electroplating pads on a semiconductor wafer
CN106129020A (en) Semiconductor package
CN103579114B (en) Integrated-semiconductor device and its wafer scale manufacture method
US8704354B2 (en) Package on package structures and methods for forming the same
US10074472B2 (en) InFO coil on metal plate with slot
CN109037160A (en) Semiconductor device packages
US8368172B1 (en) Fused buss for plating features on a semiconductor die
KR20190038563A (en) Package containing switches and filters
CN105826209A (en) Package structure and method to fabricate same
US9166593B2 (en) Flexible, space-efficient I/O circuitry for integrated circuits
CN113421873A (en) Integration of wafer level passive devices
CN105895538A (en) Manufacture method for chip packaging structure and chip packaging structure
US9716056B2 (en) Integrated circuit with back side inductor
US9852941B2 (en) Stacked conductor structure and methods for manufacture of same
CN109716514A (en) For preventing the part metals filling of extremely low K dielectric layering
CN107887698A (en) Electronic package structure and method for fabricating the same
US9775246B2 (en) Circuit board and manufacturing method thereof
US20120038065A1 (en) Method for Producing an Electrical Circuit and Electrical Circuit
US20140091441A1 (en) Ic wafer having electromagnetic shielding effects and method for making the same
CN113130428A (en) Semiconductor element packaging structure
KR20160056379A (en) Chip using triple pad configuration and packaging method thereof
CN107369653A (en) A kind of system-in-a-package method of high interference component, structure and separation array structure
US9281293B2 (en) Microelectronic packages having layered interconnect structures and methods for the manufacture thereof
CN103943585B (en) Mainboard, chip packaging module and motherboard

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20171121

DD01 Delivery of document by public notice
DD01 Delivery of document by public notice

Addressee: Gao Zhiming

Document name: Notification that Application Deemed to be Withdrawn