CN107357666A - A kind of multi-core parallel concurrent system processing method based on hardware protection - Google Patents
A kind of multi-core parallel concurrent system processing method based on hardware protection Download PDFInfo
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Abstract
The invention discloses a kind of multi-core parallel concurrent system processing method based on hardware protection; using the multi-core DSP processor based on KeyStone frameworks; by the division of multi-core DSP processor for main core and from core; each core runs embedded real-time operating system; master control core operating system is run on main core, operation acceleration core operating system, master control core operating system are responsible for control from core; core operating system is accelerated to be responsible for calculating, master control core operating system and the core operating system that accelerates complete the initialization of highly reliable function jointly.Mistake when this method finds embedded software running in time by hardware anomalies event detection, so as to which anti-locking system performs the action of mistake, improve the reliability of embedded multi-core parallel system；Log recording function is provided simultaneously, and the information of performing environment can be collected when occurring extremely, contributes to ex-post analysis and investigation mistake；Abnormal restoring function is provided by background task, after occurring extremely system can be maintained to continue to run with without out of control.
Description
Technical field
The invention belongs to the reliability design technology field of multinuclear embedded system, and in particular to one kind is based on hardware protection
Multi-core parallel concurrent system processing method.
Background technology
With the application demand that parallel computation is increasingly intensive, built-in field processor is from monokaryon to polycaryon processor
Develop rapidly, multi-core parallel concurrent is calculated as built-in field important development direction.With answering for multi-core parallel concurrent system
With more and more extensive, the function of multi-core parallel concurrent system is increasingly improved and complicated, how for multi-core parallel concurrent system to provide reliability work(
The design method of energy is very urgent.
Often interacted between multi-core parallel concurrent system center, also imply that and access main body (such as DSP core) may access should not
The space of access, and access and be divided into reading and writing, perform three types, if access main body or address are incorrect, can produce illegal
Reading and writing, process performing, ultimately result in system it is unstable in addition collapse.Multi-core DSP based on TI KeyStone frameworks has
Hardware protection mechanism, the mechanism can be utilized to set corresponding access rights, so as to lift the reliable of whole multi-core parallel concurrent system
Property.
It there is no the design side that multi-core parallel concurrent system reliability is realized based on TI KeyStone framework hardware protection mechanism at present
Method, a kind of hardware protection mechanism of the invention based on TI KeyStone, it is proposed that design side of highly reliable multi-core parallel concurrent system
Method, guaranteed reliability is provided for a whole set of multi-core parallel concurrent system.
The content of the invention
In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is that providing one kind is based on hardware
The multi-core parallel concurrent system processing method of protection so that multi-core parallel concurrent system can operationally have stronger reliability, simultaneously
When an anomaly occurs, recording exceptional information in order to ex-post analysis, and background task adapter system can be waken up to maintain in time
The operation of system is without out of control.
The present invention uses following technical scheme：
A kind of multi-core parallel concurrent system processing method based on hardware protection, using the multi-core DSP based on KeyStone frameworks
Processor, multi-core DSP processor division is run to embedded real-time operation system for main core and from core, main core and from core
Unite, master control core operating system is run on main core, operation acceleration core operating system, master control core operating system are responsible for control from core,
Accelerate core operating system to be responsible for calculating, share exclusive equipment in equipment and core outside master control core operating system initialization core, accelerate core
Exclusive equipment in operating system initialization core, master control core operating system and acceleration core operating system complete highly reliable function jointly
Initialization.
Preferably, comprise the following steps：
S1, write log task in master control core operating system；
S2, write high priority background task in each core operating system；
S3, write exception service program in each core operating system；
S4, cycle timer interrupt service routine is write, L2 cache L2 is refreshed in interrupt service routine, made
The automatic refresh function of energy multinuclear shared drive, realizes the EDC error detection and correction to multinuclear shared drive bit；
S5, determine to need the anomalous event number caught, and event number is associated with not maskable interrupts, enable abnormal inspection
Look into, complete the configuration of abnormal examination；
S6, write from the calculating application task on core, and each core will be deployed to from the run time stack for assessing calculation application task
In corresponding multinuclear shared drive；
The length range of each program segment and region is determined after S7, compiling link, accesses main body and read-write-execution attribute；
S8, it will be connected with the identical program segment for accessing main body and read-write-execution attribute and region by linking script file
Continuous arrangement, granularity alignment is protected between the program segment and region of different access main body and read-write-execution attribute by internal memory,
Each program segment and region are loaded into L2 cache L2；
S9, corresponding access rights are configured by said procedure section and zone length scope in operating system initialization,
Configure the error correcting and detecting function of internal memories at different levels.
Preferably, in step S1, the log task reads the log buffer area of each core periodically, and will according to configuration
Log information in log buffer area is transferred to PC first day of the lunar year will resolution servers or storage to Target Board by ICP/IP protocol
Flash in.
Preferably, in step S2, the priority of the high priority background task is higher than all application tasks to ensure it
Operation more early than all application tasks, hangs up the background task after operation, be until being waken up and being taken in exception service program
System, wait the instruction from the external world or the calculating application task of reconstruct triggering exception.
Preferably, in step S6, multinuclear shared memory space is distributed equally according to processor check figure, and configure master
Core and the access rights that shared drive is answered from verification.
Preferably, main core and during core operating system initialization configure multinuclear shared drive in each core corresponding region
Hardware protection authority：
Determine the address realm of multinuclear shared drive corresponding to each core；
Register is protected by the internal memory for configuring multinuclear shared drive, main core is set and from multinuclear shared drive corresponding to core
Initial address, length range, access main body and read-write-execution authority.
Preferably, in step S7, link is compiled to operating system and application, by the executable file for checking generation
ELF header information determine the length range and read-write-execution attribute of each program segment and region.
Preferably, in step S8, program segment and region on this core are included by read-write-execution attribute：The read-only code of program
Section, program read-only data section, program read-write data segment, data interaction area and log buffer area, the read-only code segment of described program, journey
Sequence read-only data section and the access main body of program read-write data segment are defined to only allow this core to access, the visit in the data interaction area
Ask that main body is defined to allow other cores and main equipment to access, the interaction of data is calculated during for multi-core parallel concurrent system operation, it is described
The access main body in log buffer area is defined to allow main core reading and the write-in of this core, and the log task on main core can be from this
The log information of each core is read in region, and is write Flash or transmitted by ICP/IP protocol.
Preferably, the attribute of the read-only code segment of described program is reading-execution, is made up of .text sections；Described program reading
It is read-only according to the attribute of section, is made up of program segments such as .const .rodata .cinit；Described program reads and writes the attribute of data segment
For read-write, it is made up of remaining readable writeable program segment, the attribute in the data interaction area and log buffer area is read-write.
Preferably, each attribute programs section in L2 cache L2 is configured in main core and during core operating system initialization
With the hardware protection authority in region, it is specially：
Determine main core and each program segment from core L2 cache L2 after operating system loaded and the address in region
Scope；
By configuring main core and protecting register from core L2 cache L2 internal memory, each program segment and region is set to originate
Address, length range, access main body and read-write-execution authority.
Compared with prior art, the present invention at least has the advantages that：
Multi-core parallel concurrent system processing method of the invention based on hardware protection, using the multinuclear based on KeyStone frameworks
DSP Processor, multi-core DSP processor division is run into embedded real-time operating system, main core for main core and from core, each core
Upper operation master control core operating system, operation acceleration core operating system, master control core operating system are responsible for control from core, accelerate core behaviour
It is responsible for calculating as system, shares exclusive equipment in equipment and core outside master control core operating system initialization core, accelerate core operating system
Exclusive equipment in core is initialized, master control core operating system and the core operating system that accelerates complete the initialization of highly reliable function jointly.
Under KeyStone frameworks, internal memories at different levels have corresponding access control module to realize the protection to specific address space, profit
With the hardware protection mechanism, compared to traditional method for protecting software, the present invention carries for the multi-core parallel concurrent system based on multi-core DSP
A kind of design method of the reliability of soft or hard combination has been supplied, can effectively prevent the unauthorized access occurred during system operation.
Further, first log task is write in master control core operating system, the log task in master control core can be read
The log information of each core caching, and write Flash or transmitted by ICP/IP protocol, in order to user's analysis system shape
State；Then high priority background task is write in each core operating system, abnormal restoring function is provided for multi-core parallel concurrent system,
After occurring extremely system can be maintained to continue to run with without out of control；Then exception service journey is write in each core operating system
Sequence, the information of performing environment can be collected when occurring extremely, contributes to accident analysis afterwards；Then write in cycle timer
Disconnected service routine, refreshes in interrupt service routine to L2, enables the automatic refresh function of multinuclear shared drive, realization pair
The EDC error detection and correction of multinuclear shared drive bit；It is then determined that needing the anomalous event number caught, and event number is associated with
Not maskable interrupts, abnormal examination is enabled, completes the configuration of abnormal examination；Then write from the calculating application task on core, and
It will be deployed to from the run time stack for assessing calculation application task in multinuclear shared drive corresponding to each core；It is then determined that each program segment
Length and attribute；Then by the program segment with same alike result by linking script file continuous arrangement, and by different access
By internal memory protection granularity alignment between the program segment and region of main body and read-write-execution attribute, and by each program segment and
Region is loaded into L2 cache L2；Finally configured in operating system initialization by said procedure section and zone length scope
Corresponding access rights, the error correcting and detecting function of internal memories at different levels is configured, using L1 level core memory spaces as system cache, be used for
The operational efficiency of lifting system, any main equipment does not have any access rights to L1 address areas in system.
Further, in order to ensure the background task after abnormal occur being capable of adapter system, it is necessary to so that exception service journey
It is the background task that sort run, which terminates rear limit priority ready task, and otherwise operating system can dispatch other high priorities
Application task, application task is continued to run with system exception state, ultimately result in the collapse of system.
Further, multinuclear shared drive is averagely allocated to each core by DSP core number, and by the run time stack of calculating task
Space is deployed in divided shared drive burst, rather than (L1 has now been made into the L2 memory spaces being deployed in DSP core
System cache is called cache, can not direct addressin, the L2 spaces of each core, resource is nervous, and the present invention rises its space
Sky is used as the caching and the foregoing each program segment of storage that image, extensive matrix etc. calculate data as far as possible, and effect is calculated to improve
Rate), the calculating task on core is calculated in the event of stack overflow problem, is embodied in read-write behavior and is crossed the border, uses shared drive
Excess room, on the one hand can mitigate the pressure of L2 insufficient spaces, on the other hand larger run time stack space can also between
Connecing reduces the probability that calculating task run time stack is overflowed.
Further, it is each because L2 is with the configuration of internal memory protection granularity progress read-write-execution authority of fixed size
Program segment size can not possibly just be the multiple of internal memory protection granularity, therefore by the program segment with identical read-write-execution attribute
Continuous arrangement together, can farthest save L2 memory space, eliminate internal fragmentation.By the read-only code segment of program,
Program read-only data section is read-only by its read only attribute configuration access authority so that they can not illegally be rewritten, and program
Read-only data section can not be taken as instruction to be performed, while be also prevented from by other DSP core unauthorized access；Program reads and writes data
Section is readable writeable by its readable writeable attribute configuration access rights so that they can not be taken as instruction to be performed, also simultaneously
It can prevent by other DSP core unauthorized access；Its readable writeable attribute configuration access rights is pressed to be readable writeable by data interaction area,
Prevent they are from being taken as instruction to be performed, but can allow to be accessed by other DSP cores, in order to carry out the exchange of data；
Log buffer area is readable writeable by its readable writeable attribute configuration access rights so that they can not be taken as instruction to be held
OK, while only master control core is allowed to carry out read access to it.
Further, due to only having the read-only code segment of program to allow to perform, and the internuclear program segment that can not exchange visits, so as to
The instruction that mistake is performed after the race of PC pointers flies is effectively prevent, system crash caused by the race of PC pointers flies etc. can be substantially eliminated and asked
Topic.
Below by drawings and examples, technical scheme is described in further detail.
Brief description of the drawings
Fig. 1 is the method flow diagram of the highly reliable multi-core parallel concurrent system of structure provided in an embodiment of the present invention；
Fig. 2 is the layout in L2 spaces in DSP core provided in an embodiment of the present invention；
Fig. 3 is the reliability function Organization Chart of multi-core parallel concurrent system provided in an embodiment of the present invention；
Fig. 4 is reliability demonstration system provided in an embodiment of the present invention and daily record analysis result exemplary plot.
Embodiment
It is of the present invention to implement that a specific multi-core DSP Target Board with TI KeyStone frameworks is combined first
Method.The related mechanism of hardware protection is provided in the KeyStone frameworks that TI is released, can be real by the hardware protection mechanism
Now to the highly reliable function of multi-core parallel concurrent system constructing based on multi-core DSP.The present invention is using the production of TI companies
TMDSEVM6678L evaluation boards, this is onboard the core DSP Processor TMS320C6678 of the monolithic 8 (letters for employing KeyStone frameworks
Claim C6678), each DSP core running frequency reaches as high as 1.25GHz, there is provided up to 40GMAC fixed-point calculations and 20GFLOP per second
Floating-point operation ability, while the hardware platform possesses powerful cache structure and various peripheral hardware collection, is particularly suitable for building multinuclear
Parallel system.Each DSP core has 32KB one-level internal memory/program cache L1P and one-level internal memory/data buffer storage L1D, and
512KB secondary memory/caching L2.The DDR3 internal memories of multinuclear shared memory spaces and 512MB of the other C6678 also with 4MB.
C6678 has all hardware defencive function that foregoing KeyStone frameworks are provided simultaneously, in KeyStone frameworks
Under, internal memories at different levels have corresponding access control module to realize the protection to specific address space, specifically, in core
Memory space such as L1, L2, be divided into the page of fixed size, every page has a MPPA (Memory Page
Protection Attributes) register be used for configure this page read-write-execution authority and possess the authority accordingly
System master, so as to realize that internal memory is protected；Memory space such as space, multinuclear shared drive in the core of other cores outside for core
With DDR3 internal memories, then read-write-execution the authority in every sector address space is configured by way of application heap and possesses this accordingly
The system master of authority, each DSP core pair can be configured by the XMC (External Memory Controller) in core
Read-write-execution authority of the outer memory space different address section of core, the length of each section can be adjusted according to demand.More
2 sets of MPAX (Memory Protection and Address are integrated with core shared drive controller (MSMC)
Extension) it is used in configuration system non-DSP core main equipment to multinuclear shared drive and DDR3 read-write-execution authority, its
Middle SES/MPAX is used to configure access of the non-core main equipment to DDR3, and SMS/MPAX is used to configure non-core main equipment to shared drive
Access.Internal memories at different levels in other system are respectively provided with error-detection error-correction function, can be detected when bit bit flipping occurs
And error correction.
For L1D, L1P, 32KB space is divided into the internal memory guarantor of the page that 16 sizes are 2KB, i.e. L1D and L1P by C6678
Shield granularity is 2KB, and every page has a MPPA register to be used to configure its read-write-execution authority and corresponding addressable master
The ID of equipment, so as to realize that internal memory is protected；L2 internal memory protection philosophy is similar, and system divide into its 512KB space
The page that 32 sizes are 16KB, i.e. the internal memory protection granularity of L2 is 16KB.For XMC/MPAX, one, which shares 16 pairs of internal memory protections, uses
Register (XMPAXH and XMPAXL), every a pair of registers are used for continuous sheet of address addressing space (address space size
More than 4KB) carry out priority assignation, so as to prevent DSP core to core outside data space unauthorized access.Multinuclear shared drive controls
The SES/MPAX and SMS/MPAX of device internal memory protection philosophy are similar, there is 8 couples of internal memory protection register (XMPAXH respectively
And XMPAXL).Other L1P can detect 1bit EMS memory error, and L2 and multinuclear shared drive can detect 2bit mistakes and entangle
Positive 1bit mistakes.
The operating system run in multi-core parallel concurrent system is mainly by the distributed micro-kernel of bottom, intermediate layer parallel computation
Framework and upper strata complex dense calculate application composition.Multi-core DSP division is embedded in real time for main core and from core, each core operation
Operating system, master control core operating system is run on main core, from core operation accelerate core operating system, master control core operating system is responsible for
Control, core operating system is accelerated to be responsible for calculating.
Whole system is used as master control core by DSP core 0, and DSP core 1~7 is as acceleration core.Wherein master control core and accelerate core can
Performing image file will be stored in the L2 spaces of each DSP core after loaded, and L1P and L1D are used as Cache to accelerate to be
The execution speed of system.
Exclusive equipment in equipment and core is shared outside master control core operating system initialization core, accelerates core operating system initialization core
Interior exclusive equipment, master control core operating system and the core operating system that accelerates complete the initialization of highly reliable function jointly.
The operating system of each core will be loaded into L2 memory spaces in core after the completion of compiling link, in order to ensure each have
The program segment of identical read-write-execution attribute can be on address space close to, can be with and according to internal memory page alignment after loading
Each program segment is rearranged by writing link script .cmd files.System is segmented into program only in L2 after the completion of arrangement
Read code segment, program read-only data section, program read-write data segment, data interaction area, log buffer area, the read-only code of its Program
The attribute of section is reading-execution, is mainly made up of .text sections；The attribute of program read-only data section to be read-only, mainly by .const,
.rodata, the program segment such as .cinit is formed；The attribute of program read-write data segment is read-write, by remaining readable writeable program
Section is formed；Above three section can only allow this core to access, and other cores have no right to access；Data interaction area and the attribute in log buffer area
For read-write, wherein data interaction area allows other cores and main equipment to access, is mainly used in calculating number during multi-core parallel concurrent system operation
According to interaction；Log buffer area allows main core to read and the write-in of this core, and this core, which produces, writes the region after log information, on main core
Log task the log information of each core can be read from the region, and write Flash or transmitted by ICP/IP protocol.
Each attribute programs section and the hardware protection authority in region in L2 are configured during operating system initialization, specifically
Including：
1st, each program segment after operating system loaded and the address realm in region are determined；
2nd, by configuring L2 MPPA registers, each program segment and region start address, length range and access are set
Main body and read-write-execution authority.
Pass through above-mentioned configuration so that the internuclear program segment that can not exchange visits, and due to only having the read-only code segment of program to permit
Perhaps perform, once the read-only code segment of unauthorized access program must trigger abnormal and denied access, so as to effectively prevent PC pointers
Run fly after perform mistake instruction, can substantially eliminate PC pointers run fly caused by system crash the problems such as.
Using L1 level core memory spaces as system cache in the present invention, for the operational efficiency of lifting system, if right
The region has carried out direct memory access, then can trigger corresponding exception, so being also required to be configured L1 access rights.Configure L1
MPPA registers, the access rights of L1 whole address areas are arranged to 0, any main equipment is to L1 addresses in expression system
Region does not have any access rights.
Accelerate the calculating application that general operation user writes in core operating system, calculating is applied and will not sent out before end of run
Raw task switching, is write due to calculating application by user, and how internuclear interaction be present, therefore needs to prevent user should
With illegal address space is accessed so as to cause system crash, the calculating application for complexity in addition often has to run time stack space
Larger demand, therefore the risk for very likely causing run time stack to overflow.In order to prevent pair space adjacent with stack after stack overflow
Cause to override, the present invention averagely divides the multinuclear shared drive outside core, and each core has one section of exclusive multinuclear shared drive
Run time stack of the space as calculating task, the multinuclear shared memory space exclusive to its by configuring foregoing XMC DSP cores
With read-write authority, any access can not be carried out to this section of space by configuring SMS/MPAX other non-core main equipments, this
Sample will necessarily access adjacent illegal address so as to trigger hardware protection exception when stack overflows.
The error-detection error-correction function of internal memories at different levels is enabled, when bit bit flipping occurs in system, it is necessary to be carried out in time to it
EDC error detection and correction.But system can only carry out error correction to 1 bit-errors of generation, can only be detected for the mistake of 2 bits and the above,
So error correction must be completed after 1 bit-errors occur, before 2 bit-errors.The error detection function of internal memory must pass through reading
Mode could trigger, therefore in order to find in time mistake need periodically from internal memory read data detected.By in system
Middle setting timer interruption, timer interruption is triggered after each end cycle, and internal storage data is carried out in interrupt service routine
Reading and written-back operation, realize the purpose of timely error correction.
Because hardware protection mechanism must be triggered by event, so the anomalous event to be detected is must determine, and to this
A little anomalous events are registered.Specifically include shielding, enabling abnormality detection mark, make for the event that deactivation system captures to needs
Can not maskable interrupts corresponding to exception service program.In task run, after the hardware protection in system occurs extremely in meeting
Event corresponding to report, if event is not shielded and abnormal examination is enabled, event meeting trigger redirects, and enters
Enter to exception service routine vector entrance.The stack space in the entrance of exception service program, switchover operation, i.e., switch from task stack
To system stack, follow-up exception service program processing is then proceeded by.Need to record system in exception service program to work as
Preceding critical registers, specifically include status register, return address register, clock register, stack pointer register, parameter
Register, value register, abnormality mark bit register etc. are returned to, help the abnormal location of instruction of orientation triggering and investigation triggering different
The reason for normal.After exception service program completes the collection of performing environment when exception occurs, log buffer area is write, is finally waken up
Background task adapter system.
The background task of a high priority can be all created in each core operating system initialization, after system start-up, by
Applied in priority higher than calculating, therefore can be prior to calculating application operation.Background task is hung up afterwards, waits exception service program fortune
Simultaneously adapter system is waken up after row.Background task can select reconstruction task, or wait extraneous order.
The reliability of system is realized using above-mentioned C6678 hardware protections mechanism, as shown in figure 1, specific implementation step is as follows：
S1, log task is write in master control core operating system, reads the log buffer area of each core the duty cycle,
And can according to configuration by the log information in log buffer area by ICP/IP protocol be transferred to PC first day of the lunar year will resolution servers or
Store in the Flash on Target Board；
S2, high priority background task is write in each core operating system, its priority is higher than all application tasks with true
Its operation more early than all application tasks is protected, the background task is hung up after operation.Until being waken up and being connect in exception service program
Guard system, wait the instruction from the external world or the calculating application task of reconstruct triggering exception；
S3, exception service program is write in each core operating system, when collection triggering is abnormal in the service routine is
Unite performing environment, including status register, return address register, clock register, stack pointer register, parameter register,
Value register, abnormality mark bit register etc. are returned, the abnormal location of instruction of orientation triggering is helped and investigates the abnormal original of triggering
Cause.After exception service program completes the collection of performing environment when exception occurs, log buffer area is write, finally wakes up backstage times
Business adapter system；
S4, cycle timer interrupt service routine is write, L2 is refreshed in interrupt service routine, particular by
IDMA (DMA in core) writes data read-out again, so as to realize the EDC error detection and correction to bit in L2；In enabled multinuclear is shared
The automatic refresh function deposited, so as to realize the EDC error detection and correction to multinuclear shared drive bit；
S5, determine to need the anomalous event number caught, and event number is associated with not maskable interrupts, enable abnormal inspection
Look into, complete the configuration of abnormal examination；No. 120 representations of events DSP cores such as C6678 generate internal memory protection failure when accessing L1P,
No. 122 representations of events DSP cores generate internal memory protection failure when directly or indirectly accessing L1D；
S6, write from the calculating task on core, multinuclear shared drive is equally divided into 8 sections, every section of 512KB, and will be from core
The run time stack of task is deployed in multinuclear shared drive corresponding to each core；
S7, link is compiled to operating system and application, checks the .map files of generation, this document is to executable text
The parsing of part ELF header information, determine the length and attribute of each program segment；
S8, the program segment with same alike result linked into script file continuous arrangement by .cmd, and divided as shown in Figure 2
Into the read-only code segment of program, program read-only data section, program read-write data segment, remaining space in L2 is divided into data interaction
Area, log buffer area, and each section and region be according to 16KB byte-aligneds, then recompilate determine after link each section and
The length range in region；
S9, corresponding access rights are configured by said procedure section and zone length scope in operating system initialization,
The access rights of L1P and L1D cachings are configured, the access rights of run time stack in shared drive has been configured, has configured internal memories at different levels
Error correcting and detecting function.The reliability function framework of whole multi-core parallel concurrent system is as shown in Figure 3 after the completion of configuration.
Highly reliable multi-core parallel concurrent system is built using above-mentioned implementation steps, and writes the calculating application task of dependence test
Tested with PC first day of the lunar year will resolution servers, test content includes stack overflow detection and protection, the read-write protection of stack, code are run
Fly protection, the protection of program read, L1cache protections, L1P error detections, LL2 error detections and error correction, multinuclear shared drive
Error detection and error correction, the protection of other retaining spaces etc..Test result is as shown in the table：
Table 1
By above-mentioned item-dividing test, most Reliability Measures effective percentage is up to 100%, and code runs out-of-competition testing and surveyed
It is efficient relatively low, this is due to the read-only code segment of program that the random race enclave location provided is located at L2 in DSP core, therefore efficient
Not up to 100%.Fly in the event of the race in this code area, can be protected using other method (such as house dog electricity
Road).
The log information in log buffer area can be read and pass through ICP/IP protocol by the log task of master control core operating system
PC first day of the lunar year will resolution servers are transferred to, after the parsing of daily record resolver in result such as Fig. 4 shown in log recording window.By rear
Platform task, triggered in each above-mentioned test after exception without power-off restarting whole system, but by background task adapter system,
And PC ends are waited to send new test command.
In summary, should the invention provides a kind of highly reliable multi-core parallel concurrent system processing method based on hardware protection
Method can effectively lift the reliability of embedded multi-core parallel system, can effectively detect using stack overflow as the soft of representative
Part frequent fault simultaneously protects system to be not carried out wrong action；Log recording function is provided simultaneously, and can be in abnormal hair
The information of performing environment is collected when raw, contributes to ex-post analysis and investigation mistake；Abnormal restoring work(is provided by background task
Can, after occurring extremely system can be maintained to continue to run with without out of control.
Claims (10)
1. a kind of multi-core parallel concurrent system processing method based on hardware protection, it is characterised in that use and be based on KeyStone frameworks
Multi-core DSP processor, multi-core DSP processor division is run into for main core and from core, main core and from core embedded reality
When operating system, master control core operating system is run on main core, from core operation accelerate core operating system, master control core operating system is born
Duty control, accelerate core operating system to be responsible for calculating, share exclusive equipment in equipment and core outside master control core operating system initialization core,
Accelerate exclusive equipment in core operating system initialization core, master control core operating system and acceleration core operating system are completed highly reliable jointly
The initialization of function.
A kind of 2. multi-core parallel concurrent system processing method based on hardware protection according to claim 1, it is characterised in that bag
Include following steps：
S1, write log task in master control core operating system；
S2, write high priority background task in each core operating system；
S3, write exception service program in each core operating system；
S4, cycle timer interrupt service routine is write, L2 cache L2 is refreshed in interrupt service routine, enabled more
The automatic refresh function of core shared drive, realizes the EDC error detection and correction to multinuclear shared drive bit；
S5, determine to need the anomalous event number caught, and event number is associated with not maskable interrupts, enable abnormal examination, it is complete
Into the configuration of abnormal examination；
S6, write from the calculating application task on core, and should by each verification is deployed to from the run time stack for assessing calculation application task
Multinuclear shared drive in；
The length range of each program segment and region is determined after S7, compiling link, accesses main body and read-write-execution attribute；
S8, will continuously it be arranged with identical access main body and the program segment of read-write-execution attribute and region by linking script file
Row, it is each by internal memory protection granularity alignment between the program segment and region of different access main body and read-write-execution attribute
Program segment and region are loaded into L2 cache L2；
S9, corresponding access rights are configured by said procedure section and zone length scope in operating system initialization, configured
The error correcting and detecting function of internal memories at different levels.
A kind of 3. multi-core parallel concurrent system processing method based on hardware protection according to claim 2, it is characterised in that step
In rapid S1, the log task reads the log buffer area of each core periodically, and according to configuration by the day in log buffer area
Will message is transferred to PC first day of the lunar year will resolution servers or storage into the Flash on Target Board by ICP/IP protocol.
A kind of 4. multi-core parallel concurrent system processing method based on hardware protection according to claim 2, it is characterised in that step
In rapid S2, the priority of the high priority background task is higher than all application tasks to ensure its fortune more early than all application tasks
OK, the background task is hung up after operation, until being waken up simultaneously adapter system in exception service program, waits the finger from the external world
Order or the calculating application task of reconstruct triggering exception.
A kind of 5. multi-core parallel concurrent system processing method based on hardware protection according to claim 2, it is characterised in that step
In rapid S6, multinuclear shared memory space is distributed equally according to processor check figure, and configures main core and should be shared from verification
The access rights of internal memory.
A kind of 6. multi-core parallel concurrent system processing method based on hardware protection according to claim 2, it is characterised in that
Main core and the hardware protection authority that each core corresponding region in multinuclear shared drive is configured during core operating system initialization：
Determine the address realm of multinuclear shared drive corresponding to each core；
Register is protected by the internal memory for configuring multinuclear shared drive, main core is set and originated from multinuclear shared drive corresponding to core
Address, length range, access main body and read-write-execution authority.
A kind of 7. multi-core parallel concurrent system processing method based on hardware protection according to claim 2, it is characterised in that step
In rapid S7, link is compiled to operating system and application, by checking that it is each that the ELF header information of executable file of generation determines
The length range and read-write in individual program segment and region-execution attribute.
A kind of 8. multi-core parallel concurrent system processing method based on hardware protection according to claim 2, it is characterised in that step
In rapid S8, program segment and region on this core are included by read-write-execution attribute：The read-only code segment of program, program read-only data
Section, program read-write data segment, data interaction area and log buffer area, the read-only code segment of described program, program read-only data section and
The access main body of program read-write data segment is defined to only allow this core to access, and the access main body in the data interaction area is defined to permit
Perhaps other cores and main equipment are accessed, and the interaction of data, the visit in the log buffer area are calculated during for multi-core parallel concurrent system operation
Ask that main body is defined to allow main core reading and the write-in of this core, the log task on main core can read each core from the region
Log information, and write Flash or transmitted by ICP/IP protocol.
A kind of 9. multi-core parallel concurrent system processing method based on hardware protection according to claim 8, it is characterised in that institute
The attribute for stating the read-only code segment of program is reading-execution, is made up of .text sections；The attribute of described program read-only data section to be read-only,
It is made up of program segments such as .const .rodata .cinit；The attribute of described program read-write data segment is read-write, by remaining
Readable writeable program segment is formed, and the attribute in the data interaction area and log buffer area is read-write.
A kind of 10. multi-core parallel concurrent system processing method based on hardware protection according to claim 2, it is characterised in that
Configure in main core and during core operating system initialization the hardware package in each attribute programs section and region in L2 cache L2
Authority is protected, is specially：
Determine main core and each program segment and the address realm in region from core L2 cache L2 after operating system loaded；
By configuring main core and protecting register from core L2 cache L2 internal memory, each program segment and region starting point are set
Location, length range, access main body and read-write-execution authority.
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