CN107357596B - Chip program updating system - Google Patents
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- CN107357596B CN107357596B CN201610301804.4A CN201610301804A CN107357596B CN 107357596 B CN107357596 B CN 107357596B CN 201610301804 A CN201610301804 A CN 201610301804A CN 107357596 B CN107357596 B CN 107357596B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44568—Immediately runnable code
- G06F9/44578—Preparing or optimising for loading
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Abstract
The invention provides a chip program updating system, comprising: the system comprises an upper computer, a first control circuit board and at least one second control circuit board; the first control circuit board comprises a first communication chip and a first control chip which are connected with each other, and the second control circuit board comprises a second communication chip and a second control chip which are connected with each other; the upper computer is connected with the first communication chip through a communication interface, and the first communication chip is respectively connected with each second communication chip. The chip program updating system provided by the invention can realize remote program updating of all control circuit boards in the control circuit through one communication interface, and improves the updating efficiency of the chip program and the communication efficiency of the communication interface.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a chip program updating system.
Background
The urban rail transit is used as a main artery for supporting the normal running of the city, so that the development is rapid, meanwhile, the rail transit traction control technology also enters a rapid development period, and the development of the control technology is realized, so that the control circuit is developed from single simple sequential logic operation to a plurality of complex logic operation control circuit boards. The maintenance of the control circuit board program codes is also started to develop from a simple programming mode to an on-line and long-distance programming mode so as to adapt to the requirements of developing more and more complex traction control modes.
At present, most of control chips on a control circuit board support on-line remote programming updating of program codes, the control circuit board is connected with an external program updating device through a serial interface of the control circuit, and the control chips on the control circuit board receive an updating program through the serial interface, so that the program updating is finished on-line remotely.
However, the control circuit generally includes only one serial interface, and one serial interface can be connected to only one control circuit board, so that only one program update of the control circuit board can be remotely performed on line through one serial interface. When a plurality of control circuit boards exist in the control circuit, program update of all the control circuit boards cannot be realized through one serial interface, and meanwhile, the communication efficiency of the serial interface is reduced.
Disclosure of Invention
The invention provides a chip program updating system, which can realize the online remote program updating of control chips on a plurality of control circuit boards in a control system through one communication interface, thereby improving the updating efficiency of chip programs and the communication efficiency of the communication interface.
The chip program updating system provided by the invention comprises: the system comprises an upper computer, a first control circuit board and at least one second control circuit board; the first control circuit board comprises a first communication chip and a first control chip which are connected with each other, and the second control circuit board comprises a second communication chip and a second control chip which are connected with each other; the upper computer is connected with the first communication chip through a communication interface, and the first communication chip is respectively connected with each second communication chip;
the upper computer is used for sending update data to the first communication chip through the communication interface;
the first communication chip is used for forwarding the update data to the first control chip;
the first control chip is used for analyzing the update data to obtain a chip identifier; if the chip identification corresponds to the first control chip, completing program updating of the first control chip according to the updating data; if the chip identifier corresponds to the second control chip, controlling the first communication chip to establish a communication channel between the upper computer and the second communication chip corresponding to the chip identifier; the chip identification corresponds to the first communication chip and the first control chip or corresponds to the second communication chip and the second control chip which are positioned on the same second control circuit board;
the second communication chip is used for forwarding the update data to the second control chip connected with the second communication chip;
and the second control chip is used for completing program updating of the second control chip according to the updating data.
The invention provides a chip program updating system, comprising: the upper computer is connected with the first communication chip through a communication interface, and the first communication chip is connected with each second communication chip respectively. The chip program updating system provided by the invention can realize remote program updating of all control circuit boards in the control circuit through one communication interface, and improves the updating efficiency of the chip program and the communication efficiency of the communication interface.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it will be obvious that the drawings in the following description are some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of a chip program update system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a chip program update system according to a second embodiment of the present invention;
fig. 3 is a schematic diagram of a chip program update system according to a fourth embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a schematic diagram of a chip program update system according to an embodiment of the invention. As shown in fig. 1, the chip program update system provided in this embodiment may include:
the upper computer 1, a first control circuit board 2 and at least one second control circuit board 3. The first control circuit board 2 includes a first communication chip 21 and a first control chip 23 connected to each other, and the second control circuit board 3 includes a second communication chip 31 and a second control chip 33 connected to each other. The host computer 1 is connected to the first communication chip 21 via a communication interface, and the first communication chip 21 is connected to each of the second communication chips 31.
The host computer 1 is configured to send update data to the first communication chip 21 through the communication interface.
The first communication chip 21 is used for forwarding the update data to the first control chip 23.
The first control chip 23 is configured to parse the update data to obtain a chip identifier. If the chip identifier corresponds to the first control chip 23, the program update of the first control chip 23 is completed according to the update data, and if the chip identifier corresponds to the second control chip 33, the first communication chip 21 is controlled to establish a communication channel between the upper computer 1 and the second communication chip 31 corresponding to the chip identifier. Wherein the chip identification corresponds to the first communication chip 21 and the first control chip 23 or to the second communication chip 31 and the second control chip 33 located on the same second control circuit board 3.
The second communication chip 31 is used for forwarding the update data to a second control chip 33 connected with the second communication chip 31.
And the second control chip 33 is used for completing the program update of the second control chip 33 according to the update data.
In this embodiment, the chip identifier may uniquely distinguish the first control chip 23 or any one of the second control chips 33, and the chip identifier has a correspondence relationship with the communication chip and the control chip on the same control circuit board, for example: the chip identifier B corresponds to one of the second control chips 33, and at the same time corresponds to the second communication chip 31 connected to the second control chip 33. The chip identification may have various implementations, for example: the chip identifier may be a combination of numbers and letters, or a combination of chip types and numbers, which is not limited in this embodiment.
In this embodiment, the chip program updating system includes a plurality of control circuit boards, specifically, a first control circuit board 2 and at least one second control circuit board 3, and from the physical connection point of view, the upper computer 1 and the first control circuit board 2 are physically connected through a communication interface and a first communication chip 21, and the upper computer 1 and each second control circuit board 3 are physically connected through a communication interface, the first communication chip 21 and a second communication chip 31 on each second control circuit board 3.
In the present embodiment, the first communication chip 21 and each second communication chip 31 implement a data forwarding function, the first communication chip 21 may forward update data to the first control chip 23 or each second communication chip 31, and the second communication chip 31 may forward update data to the second control chip 33 connected to the second communication chip 31.
In this embodiment, the first control chip 23 may analyze the update data sent by the host computer 1 to obtain a chip identifier, and according to the chip identifier, the first control chip 23 or each second control chip 33 may implement updating of a chip program. Specifically, when the chip identifier corresponds to the first control chip 23, since the communication channel between the upper computer 1 and the first control chip 23 is communicated, data can be sent to each other, and then the first control chip 23 directly completes the program update of the first control chip 23 according to the update data. When the chip identifier corresponds to a certain second control chip 33, since the upper computer 1 is only in physical communication with the second control chip 33, and communication channel communication is not realized, the first control chip 23 controls the first communication chip 21 to establish a duplex communication channel between the upper computer 1 and the second communication chip 31, and then the second control chip 33 completes program update of the second control chip 33 according to update data.
In summary, in the chip program updating system provided in this embodiment, the first communication chip 21 on the first control circuit board 2 is used to realize the physical connection between the multiple control circuit boards and the upper computer 1, and the first control chip 23 on the first control circuit board 2 is used to analyze the update data, so that the chip identifier that needs to be updated can be obtained, and further the first control chip 23 or any one of the second control chips 33 is used to complete the program update, so that the chip program update is remotely performed on line through one communication interface, and the update efficiency of the chip program and the communication efficiency of the communication interface are improved.
It should be noted that the communication interface may be any communication interface on the first control circuit board 2, for example: the serial port may also be a communication interface customized by the host computer 1 and the first control circuit board 2, which is not limited in this embodiment. The host computer 1 and the first communication chip 21 perform data transmission according to a communication protocol followed by the communication interface.
It should be noted that, the communication channel established between the upper computer 1 and the second communication chip 31 corresponding to the chip identifier is a duplex channel.
The first communication chip 21 and the second communication chip 31 may be identical in model number or different in model number, and the first control chip 23 and the second control chip 33 may be identical in model number or different in model number.
Optionally, updating the data may include: chip update instructions and chip update programs. The chip update instruction refers to various instructions in the process of updating the chip program, for example: program update start instructions, program update interrupt instructions, program update suspend instructions, chip restart instructions, etc., each of which includes a chip identification.
Optionally, the first control circuit board 2 and the at least one second control circuit board 3 are directly connected by an electrical interface.
The present embodiment provides a chip program updating system, including: the upper computer is connected with the first communication chip through a communication interface, and the first communication chip is connected with each second communication chip respectively. According to the chip program updating system provided by the embodiment, remote program updating of all control circuit boards in the control circuit can be realized through one communication interface, so that the updating efficiency of the chip program and the communication efficiency of the communication interface are improved.
Fig. 2 is a schematic diagram of a chip program update system according to a second embodiment of the present invention, and the present embodiment provides another implementation manner of the chip program update system based on the first embodiment, which specifically implements remote update of a chip program when a control circuit board includes a plurality of chips of different types. As shown in fig. 2, the chip program update system provided in this embodiment may include:
the upper computer 1, a first control circuit board 2 and at least one second control circuit board 3. The first control circuit board 2 includes a first communication chip 21 and a first control chip 23 connected to each other, and the second control circuit board 3 includes a second communication chip 31 and a second control chip 33 connected to each other. The host computer 1 is connected to the first communication chip 21 via a communication interface, and the first communication chip 21 is connected to each of the second communication chips 31.
The first control chip 23 includes a first type chip 231 and a second type chip 233, and the first type chip 231 and the second type chip 233 are connected to the first communication chip 21.
The first type of chip 231 is used for resolving the update data to obtain a chip identifier. If the chip identifier corresponds to the first type chip 231, the program update of the first type chip 231 is completed according to the update data. If the chip identifier corresponds to the second type chip 233, the first communication chip 21 is controlled to establish a communication channel between the host computer 1 and the second type chip 233.
The second type chip 233 is used for completing program update of the second type chip 233 according to the update data.
In the above-described structure, the first control circuit board 2 includes two different types of control chips, namely, the first type chip 231 and the second type chip 233. Wherein the chip identifier may uniquely distinguish between the first type of chip 231 or the second type of chip 233. From the physical connection point of view, the first type chip 231 and the second type chip 233 are both connected to the first communication chip 21, and therefore, the host computer 1 is physically connected to both the first type chip 231 and the second type chip 233 through the communication interface and the first communication chip 21.
In the above structure, the first type chip 231 may analyze the update data sent by the host computer 1 to obtain a chip identifier, and according to the chip identifier, the first type chip 231 or the second type chip 233 may implement updating of the chip program. Specifically, when the chip identifier corresponds to the first type chip 231, since the communication channel between the host computer 1 and the first type chip 231 is communicated, data can be sent to each other, and the first type chip 231 directly completes the program update of the first type chip 231 according to the update data. When the chip identifier corresponds to the second type chip 233, since only physical communication is performed between the upper computer 1 and the second type chip 233, and communication channel communication is not implemented, the first type chip 231 first controls the first communication chip 21 to establish a communication channel between the upper computer 1 and the second type chip 233, and then the second type chip 233 directly completes program update of the second type chip 233 according to update data sent by the upper computer.
Therefore, the chip program updating system provided by the embodiment can realize remote program updating when two different types of control chips exist on one control circuit board through one communication interface, so that the updating efficiency of the chip program and the communication efficiency of the communication interface are improved.
Further, the second control chip 33 may include a third type chip 331 and a fourth type chip 333, and the third type chip 331 and the fourth type chip 333 are connected to the second communication chip 31.
The first type chip 231 is further configured to control the first communication chip 21 to establish a communication channel between the host computer 1 and the second communication chip 31 corresponding to the chip identifier if the chip identifier corresponds to the third type chip 331 or the fourth type chip 333.
The third type chip 331 is configured to complete program update of the third type chip 331 according to the update data if the chip identifier corresponds to the third type chip 331. If the chip identifier corresponds to the fourth type chip 333, the second communication chip 31 connected to the third type chip 331 is controlled to establish a communication channel between the host computer 1 and the fourth type chip 333 corresponding to the chip identifier.
The fourth type chip 333 is used for completing program update of the fourth type chip 333 according to the update data.
In the above-described structure, the second control circuit board 3 includes two different types of control chips, namely, a third type chip 331 and a fourth type chip 333. Wherein the chip identification can uniquely distinguish the third type chip 331 or the fourth type chip 333. From the physical connection point of view, the third type chip 331 and the fourth type chip 333 are connected to the second communication chip 31, and therefore, the host computer 1 is physically connected to the third type chip 331 and the fourth type chip 333 through the communication interface, the first communication chip 21, and the respective second communication chips 31.
In the above structure, the first type chip 231 may analyze the update data transmitted from the host computer 1 to obtain a chip identifier, and the third type chip 331 or the fourth type chip 333 may implement updating of the chip program according to the chip identifier. Specifically, when the chip identifier corresponds to a certain third type chip 331, since only physical communication is performed between the upper computer 1 and the third type chip 331, and communication channel communication is not implemented, the first type chip 231 first controls the first communication chip 21 to establish a communication channel between the upper computer 1 and the second communication chip 31 corresponding to the chip identifier, and then the third type chip 331 completes program update of the third type chip 331 according to update data. When the chip identifier corresponds to the fourth type chip 333, since only physical communication is performed between the upper computer 1 and the fourth type chip 333, and communication channel communication is not implemented, the first type chip 231 first controls the first communication chip 21 to establish a communication channel between the upper computer 1 and the second communication chip 31 corresponding to the chip identifier, then the third type chip 331 controls the second communication chip 31 connected to the third type chip 331 to establish a communication channel between the upper computer 1 and the fourth type chip 333, and then the fourth type chip 333 directly completes program update of the fourth type chip 333 according to update data sent by the upper computer.
Therefore, through the chip program updating system, remote program updating can be realized through one communication interface when a plurality of control circuit boards exist in the control circuit and two different types of control chips exist on each control circuit board, so that the updating efficiency of the chip program and the communication efficiency of the communication interface are improved.
It should be noted that the first type of chip 231 and the third type of chip 331 may have the same model, and the second type of chip 233 and the fourth type of chip 333 may have the same model.
Alternatively, the first type of chip 231 and the third type of chip 331 may be Field programmable gate arrays (Field-Programmable Gate Array, FPGA for short). The second type chip 233 and the fourth type chip 333 may be digital signal processors (Digital Signal Processor, abbreviated as DSPs). The first communication chip 21 and the second communication chip 31 may be complex programmable logic devices (Complex Programmable Logic Device, abbreviated as CPLDs).
The embodiment provides a chip program updating system, which can realize remote program updating of all control chips through one communication interface when a control circuit comprises a plurality of control circuit boards and the control circuit boards comprise a plurality of different types of control chips, and improves the updating efficiency of chip programs and the communication efficiency of the communication interface.
As the chip program updating system provided in the third embodiment of the present invention, on the basis of the second embodiment, another implementation manner of the chip program updating system is provided, and specifically, the restart function of the control chip after the chip updating is successful is realized. The chip program updating system provided in this embodiment specifically includes:
the first type chip 231 or the third type chip 331 is further configured to feed back a success flag to the host computer 1 after the chip program update is completed.
The upper computer 1 is further configured to send a first restart instruction to the first communication chip 21 through the communication interface after receiving the success identification. The first restart instruction is used to instruct to restart the first type chip 231 or restart the third type chip 331.
The first communication chip 21 is configured to forward the first restart instruction to the first type chip 231.
The first type of chip 231 is used for resolving the first restart instruction to obtain a chip identifier. If the chip identifier corresponds to the first type chip 231, the first communication chip 21 is controlled to trigger the first type chip 231 to reset. If the chip identifier corresponds to the third type chip 331, the first communication chip 21 is controlled to forward the first restart instruction to the second communication chip 31 corresponding to the chip identifier.
The second communication chip 31 is configured to forward the first restart instruction to the third type chip 331 connected to the second communication chip 31.
The third type chip 331 is used for controlling the second communication chip 31 connected with the third type chip 331 to trigger the third type chip 331 to reset.
Therefore, through the process, after the chip program is updated, only the control chip with the updated program is reset and restarted, other components in the control system and the whole control system are not affected, and the reset and restart of the whole control system caused by the program update are avoided.
Further, the upper computer 1 is further configured to send a second restart instruction to the first communication chip 21 through the communication interface after detecting that the second type chip 233 or the fourth type chip 333 completes the chip program update. The second restart instruction is used to instruct to restart the second type chip 233 or the fourth type chip 333.
The first communication chip 21 is configured to forward the second restart instruction to the first type chip 231.
The first type of chip 231 is used for resolving the second restart instruction to obtain a chip identifier. If the chip identifier corresponds to the second type chip 233, the first communication chip 21 is controlled to close a communication channel between the upper computer 1 and the second type chip 233, and the first communication chip 21 is controlled to trigger the second type chip 233 to reset. If the chip identifier corresponds to the fourth type chip 333, the first communication chip 21 is controlled to close the communication channel between the upper computer 1 and the second communication chip 31 corresponding to the chip identifier, and the first communication chip 21 is controlled to forward the second restart instruction to the second communication chip 31 corresponding to the chip identifier.
The second communication chip 31 is configured to forward the second restart instruction to the third type chip 331 connected to the second communication chip 31.
The third type chip 331 is used for controlling the second communication chip 31 connected with the third type chip 331 to close a communication channel between the upper computer 1 and the fourth type chip 333 corresponding to the chip identifier, and controlling the second communication chip 31 connected with the third type chip 331 to trigger the fourth type chip 333 to reset.
The embodiment provides a chip program updating system, which only realizes the independent reset and restart of a control chip after a certain control chip remotely completes program updating, avoids the reset and restart problem of the whole control system after a certain control chip is updated once, and ensures the normal operation of the whole control system after program updating.
Fig. 3 is a schematic structural diagram of a chip program update system according to a fourth embodiment of the present invention, and the present embodiment uses a specific chip type as an example based on the above embodiment, to explain in detail the working principle of the chip program update system according to the present invention. As shown in fig. 3, the chip program update system provided in this embodiment includes: the upper computer 1, a first control circuit board and four second control circuit boards.
Wherein, first control circuit board includes: CPLD1, FPGA1, DSP1 and Flash Memory (Flash for short) 1, the first second control circuit board includes: CPLD2, FPGA2, DSP2 and Flash2, the second control circuit board includes: CPLD3, FPGA3, DSP3 and Flash3, and the third second control circuit board includes: CPLD4, FPGA4, DSP4 and Flash4.
The upper computer 1 is connected with the CPLD1 through a serial port.
The working principle of the chip program update system provided in this embodiment will be described in detail below by taking remote update of FPGA1 as an example.
The upper computer 1 sends update data through the serial port, wherein the update data comprises a chip identifier fpga1. After receiving the update data, the CPLD1 forwards the update data to the FPGA1, the FPGA1 analyzes the update data to obtain a chip identifier of FPGA1, and the FPGA1 directly guides the update data into the Flash1. After the Flash1 code is imported, the FPGA1 feeds back a successful identification to the upper computer 1 through the CPLD1, and the upper computer 1 confirms that the program code of the FPGA1 is updated successfully, and then a reset instruction is sent through the CPLD1, and the FPGA1 controls the CPLD1 to trigger a reset interface of the FPGA1 according to the reset instruction, so that reset restarting of the FPGA1 is completed.
The working principle of the chip program update system provided in this embodiment will be described in detail below by taking the remote update DSP1 as an example.
The upper computer 1 sends update data through the serial port, wherein the update data comprises a chip identifier dsp1. After receiving the update data, the CPLD1 forwards the update data to the FPGA1, the FPGA1 analyzes the update data to obtain a chip identifier of DSP1, the FPGA1 controls the CPLD1 to establish a serial duplex channel between the DSP1 and the upper computer 1, and the upper computer 1 directly calls the TI plug-in C2prog to finish the update of the DSP1 program. After the upper computer 1 detects that the program code of the DSP1 is updated successfully, the upper computer 1 sends a reset instruction through the CPLD1, the FPGA1 controls the CPLD1 to close the serial channel and controls the CPLD1 to trigger a reset interface of the DSP1, so that reset restarting of the DSP1 is completed.
The working principle of the chip program update system provided in this embodiment will be described in detail below by taking the remote update FPGA3 as an example.
The upper computer 1 sends update data through the serial port, and the update data comprises a chip identifier fpga3. After receiving the update data, the CPLD1 forwards the update data to the FPGA1, the FPGA1 analyzes the update data to obtain a chip identifier of FPGA3, the FPGA1 controls the CPLD1 to establish a serial full duplex channel between the upper computer 1 and the DPLD3, and the FPGA3 directly guides the update data into the Flash3. After the Flash3 code is imported, the FPGA3 feeds back a successful identifier to the upper computer 1 through the CPLD3 and the CPLD1, the upper computer 1 confirms that the program code of the FPGA3 is updated successfully, then a reset instruction is sent through the CPLD1, the FPGA1 analyzes the reset instruction to obtain a chip identifier of FPGA3, the CPLD1 forwards the reset instruction to the CPLD3, and the FPGA3 controls the CPLD3 to trigger a reset interface of the FPGA3 according to the reset instruction, so that reset restarting of the FPGA3 is completed.
The working principle of the chip program update system provided in this embodiment will be described in detail below by taking the remote update DSP3 as an example.
The upper computer 1 sends update data through the serial port, and the update data comprises a chip identifier dsp3. After receiving the update data, the CPLD1 forwards the update data to the FPGA1, the FPGA1 analyzes the update data to obtain a chip mark DSP3, the FPGA1 controls the CPLD1 to establish a serial full duplex channel between the upper computer 1 and the DPLD3, the FPGA3 controls the CPLD3 to establish a serial duplex channel between the DSP3 and the upper computer 1, and the upper computer 1 directly calls the TI plug-in C2prog to finish the update of the DSP3 program. After the upper computer 1 detects that the program code of the DSP3 is successfully updated, the upper computer 1 sends a reset instruction through the CPLD1, the FPGA1 analyzes the reset instruction to obtain a chip mark DSP3, the FPGA1 controls the CPLD1 to close a serial full duplex channel between the upper computer 1 and the DPLD3, the FPGA3 controls the CPLD3 to close the serial full duplex channel between the DSP3 and the upper computer 1, and the FPGA3 controls the CPLD3 to trigger a reset interface of the DSP3, so that reset restarting of the DSP3 is completed.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (6)
1. A chip program update system, comprising: the system comprises an upper computer, a first control circuit board and at least one second control circuit board; the first control circuit board comprises a first communication chip and a first control chip which are connected with each other, and the second control circuit board comprises a second communication chip and a second control chip which are connected with each other; the upper computer is connected with the first communication chip through a communication interface, and the first communication chip is respectively connected with each second communication chip;
the upper computer is used for sending update data to the first communication chip through the communication interface;
the first communication chip is used for forwarding the update data to the first control chip;
the first control chip is used for analyzing the update data to obtain a chip identifier; if the chip identification corresponds to the first control chip, completing program updating of the first control chip according to the updating data; if the chip identifier corresponds to the second control chip, controlling the first communication chip to establish a communication channel between the upper computer and the second communication chip corresponding to the chip identifier; the chip identification corresponds to the first communication chip and the first control chip or corresponds to the second communication chip and the second control chip which are positioned on the same second control circuit board;
the second communication chip is used for forwarding the update data to the second control chip connected with the second communication chip;
the second control chip is used for completing program updating of the second control chip according to the updating data; the first control circuit board and the at least one second control circuit board are directly connected through an electrical interface; the update data includes: chip update instructions and chip update programs.
2. The system of claim 1, wherein the first control chip comprises a first type chip and a second type chip, each of the first type chip and the second type chip being connected to the first communication chip;
the first type chip is used for analyzing the update data to obtain the chip identification; if the chip identifier corresponds to the first type chip, completing program updating of the first type chip according to the updating data; if the chip identification corresponds to the second type chip, controlling the first communication chip to establish a communication channel between the upper computer and the second type chip;
and the second type chip is used for completing program updating of the second type chip according to the updating data.
3. The system of claim 2, wherein the second control chip comprises a third type chip and a fourth type chip, each of the third type chip and the fourth type chip being connected to the second communication chip;
the first type chip is further used for controlling the first communication chip to establish a communication channel between the upper computer and the second communication chip corresponding to the chip identifier if the chip identifier corresponds to the third type chip or the fourth type chip;
the third type chip is used for completing program updating of the third type chip according to the updating data if the chip identifier corresponds to the third type chip; if the chip identifier corresponds to the fourth type chip, controlling the second communication chip connected with the third type chip to establish a communication channel between the upper computer and the fourth type chip corresponding to the chip identifier;
and the fourth type chip is used for completing program updating of the fourth type chip according to the updating data.
4. The system of claim 3, wherein the first type of chip or the third type of chip is further configured to feed back a success flag to the host computer after the chip program update is completed;
the upper computer is further used for sending a first restarting instruction to the first communication chip through the communication interface after receiving the successful identification; the first restarting instruction is used for indicating to restart the first type chip or restart the third type chip;
the first communication chip is used for forwarding the first restarting instruction to the first type chip;
the first type chip is used for analyzing the first restarting instruction to obtain the chip identifier; if the chip identifier corresponds to the first type chip, controlling the first communication chip to trigger the first type chip to reset; if the chip identifier corresponds to the third type chip, the first communication chip is controlled to forward the first restarting instruction to the second communication chip corresponding to the chip identifier;
the second communication chip is used for forwarding the first restarting instruction to the third type chip connected with the second communication chip;
the third type chip is used for controlling a second communication chip connected with the third type chip to trigger the third type chip to reset.
5. The system of claim 3, wherein the host computer is further configured to send a second restart instruction to the first communication chip through the communication interface after detecting that the second type of chip or the fourth type of chip completes a chip program update; the second restarting instruction is used for indicating to restart the second type chip or restart the fourth type chip;
the first communication chip is used for forwarding the second restarting instruction to the first type chip;
the first type chip is used for analyzing the second restarting instruction to obtain the chip identifier; if the chip identification corresponds to the second type chip, controlling the first communication chip to close a communication channel between the upper computer and the second type chip, and controlling the first communication chip to trigger the second type chip to reset; if the chip identifier corresponds to the fourth type chip, controlling the first communication chip to close a communication channel between the upper computer and a second communication chip corresponding to the chip identifier, and controlling the first communication chip to forward the second restarting instruction to the second communication chip corresponding to the chip identifier;
the second communication chip is used for forwarding the second restarting instruction to the third type chip connected with the second communication chip;
the third type chip is used for controlling the second communication chip connected with the third type chip to close a communication channel between the upper computer and the fourth type chip corresponding to the chip identifier, and controlling the second communication chip connected with the third type chip to trigger the fourth type chip to reset.
6. The system of any one of claims 3 to 5, wherein the first type of chip and the third type of chip are field programmable gate arrays FPGAs; the second type chip and the fourth type chip are Digital Signal Processors (DSPs); the first communication chip and the second communication chip are complex programmable logic devices CPLDs.
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| CN113360163A (en) * | 2021-04-19 | 2021-09-07 | 深圳市创成微电子有限公司 | Multi-chip device and chip upgrading method |
| CN113407222B (en) * | 2021-06-17 | 2022-11-11 | 南方电网数字电网研究院有限公司 | Service updating method and device, computer equipment and storage medium |
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