CN107340665B

CN107340665B - Electrophoretic display panel and method of manufacture

Info

Publication number: CN107340665B
Application number: CN201710774794.0A
Authority: CN
Inventors: 许祖钊; 林柏全; 许文钦; 毛琼琴
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2017-08-31
Filing date: 2017-08-31
Publication date: 2020-06-05
Anticipated expiration: 2037-08-31
Also published as: CN107340665A

Abstract

The embodiment of the application discloses an electrophoretic display panel and a manufacturing method. The electrophoretic display panel includes: a substrate including a display region and a non-display region; the first metal layer is positioned on the substrate, and a first capacitor polar plate is formed on the first metal layer; the second metal layer is positioned on the first metal layer, and a plurality of shading areas are formed on the second metal layer; the third metal layer is positioned between the first metal layer and the second metal layer, and a second capacitor plate is formed on the third metal layer; and a plurality of metal exchange lines extending along the second direction and arranged along the first direction for transmitting data signals to the data lines, wherein at least one metal exchange line in each metal exchange line is positioned in the display area, and at least one metal exchange line formed in the second metal layer exists in the at least one metal exchange line. The embodiment can reduce the occupation of the metal exchange wire on the first metal layer and/or the third metal layer, thereby increasing the capacitance between the first capacitor plate and the second capacitor plate to meet the display requirement.

Description

Electrophoretic display panel and method of manufacture

Technical Field

The present application relates to the field of display technologies, and in particular, to an electrophoretic display panel and a method of manufacturing the same.

Background

At present, the basic principle of electrophoretic display is that the position of electrophoretic particles is controlled by an electric field, and the reflection of light is controlled by the moved position, so as to achieve the required brightness. The conventional electrophoretic display panel is generally configured such that an electrophoretic film is formed between a pixel electrode and a common electrode. Thus, the pixel electrode and the common electrode are respectively provided with the direct current voltage signals, and an electric field can be formed between the pixel electrode and the common electrode, thereby realizing image display. Specific structure of the electrophoretic display panel, reference may be made to fig. 1, which shows a schematic structural diagram of a conventional electrophoretic display panel.

As shown in fig. 1, a conventional electrophoretic display panel generally includes a pixel electrode 011 and a data line 012 supplying a data signal to the pixel electrode 011. The data lines 012 extend in a first direction and are arranged in a second direction. The data line 012 is electrically connected to the pixel electrode 011 through two thin film transistors connected in series. And the gates of the two thin film transistors are electrically connected to a scan line 013 for supplying a gate driving signal. The scan lines 013 extend along the second direction and are arranged along the first direction. In this case, in order to reduce the space occupied by the traces in the non-display area and to facilitate the design of a narrow bezel, as shown in fig. 1, a metal line 014 for transmitting data signals to the data lines 012 may be provided in the display area of the electrophoretic display panel. In order to simplify the manufacturing process, the metal line 014 may be disposed in the same layer as the scan line 013 and extend along the second direction. This also contributes to a slim design of the panel.

In addition, in the conventional electrophoretic display panel, two capacitor plates are usually formed on the film layers of the data lines 012 and the scan lines 013, respectively, as shown by the areas formed by the thick solid lines in the figure. During the charging phase, the two capacitor plates are charged to store electrical energy. In the holding stage, the two capacitor plates respectively charge the pixel electrode and the common electrode to supplement the gradually-reduced potential of the pixel electrode under the influence of the self characteristics of the thin film transistor, so that the electric field required by the movement of the electrophoretic particles is ensured, and the picture display is realized.

However, since the scan line 013, the metal line 014 and the capacitor plate are disposed on the same film, the area of the capacitor plate in the film is affected, and thus the capacitance between the two capacitor plates in the charging phase is reduced, and the design requirement in the holding phase cannot be satisfied.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present application provides an improved electrophoretic display panel and method of manufacturing to solve the technical problems mentioned in the background section above.

In a first aspect, embodiments of the present application provide an electrophoretic display panel. The electrophoretic display panel includes: a substrate including a display region and a non-display region; the first metal layer is positioned on the substrate, and a first capacitor polar plate is formed on the first metal layer; the second metal layer is positioned on the first metal layer, and a plurality of shading areas are formed on the second metal layer; the third metal layer is positioned between the first metal layer and the second metal layer, and a second capacitor plate is formed on the third metal layer; and a plurality of metal exchange lines extending along the second direction and arranged along the first direction for transmitting data signals to the data lines, wherein at least one metal exchange line in each metal exchange line is positioned in the display area, and at least one metal exchange line formed in the second metal layer exists in the at least one metal exchange line.

In some embodiments, the electrophoretic display panel includes a thin film transistor, a plurality of scan lines, and a plurality of data lines for supplying data signals to the respective pixel electrodes; the thin film transistor comprises a grid electrode, a source electrode, a drain electrode and a channel, wherein the orthographic projection of the channel to the second metal layer is positioned in one shading area; the grid is formed on the first metal layer, the source and the drain are formed on the third metal layer, and the channel is formed on the semiconductor layer, wherein the semiconductor layer is positioned between the first metal layer and the third metal layer; the plurality of scanning lines are formed on the first metal layer, extend along the second direction, are arranged along the first direction and are used for providing a grid driving signal for the grid; the data lines are formed on the third metal layer, extend along the first direction and are arranged along the second direction, and the data lines are electrically connected with the at least one metal exchange line.

In some embodiments, an electrophoretic display panel includes a pixel electrode layer and a common electrode layer; the pixel electrode layer is positioned between the second metal layer and the common electrode layer, and an electrophoretic film is arranged between the pixel electrode layer and the common electrode layer; the pixel electrode of the pixel electrode layer receives a data signal, and the common electrode of the common electrode layer receives a common voltage signal.

In some embodiments, the first capacitor plate is electrically connected to the pixel electrode and the second capacitor plate is electrically connected to the common electrode.

In some embodiments, the electrophoretic display panel includes a common signal line for transmitting a common voltage signal to the common electrode; the common signal line is formed on the third metal layer, and the second capacitor polar plate is electrically connected with the common electrode through the common signal line; the first capacitor plate is electrically connected with the pixel electrode through a through hole, wherein the through hole is formed in an at least partially overlapping region of the orthographic projection of the first capacitor plate to the pixel electrode layer and one of the pixel electrodes.

In some embodiments, the orthographic projection of the pixel electrode to the second metal layer partially overlaps the at least one metal bar.

In some embodiments, the electrophoretic display panel further includes a first insulating layer between the pixel electrode layer and the second metal layer.

In some embodiments, the electrophoretic display panel further includes a second insulating layer between the first metal layer and the semiconductor layer, wherein the second insulating layer has the same thickness as the first insulating layer.

In some embodiments, the thickness L of the first insulating layer satisfies: l is less than or equal to 350 nanometers.

In some embodiments, the thickness L of the first insulating layer satisfies: l is more than or equal to 250 nanometers and less than or equal to 350 nanometers.

In a second aspect, embodiments of the present application provide a manufacturing method for manufacturing an electrophoretic display panel as described in any one of the embodiments of the first aspect. The manufacturing method comprises the following steps: preparing a substrate, wherein the substrate comprises a display area and a non-display area; forming a first metal layer in a display area of a substrate, and processing the first metal layer to form a first capacitor plate; forming a third metal layer on the first metal layer, and processing the third metal layer to form a second capacitor plate; forming a second metal layer on the third metal layer, and processing the second metal layer to form a plurality of shading areas and at least one metal line change; the electrophoresis display panel comprises a plurality of metal exchange lines for transmitting data signals to the data lines.

In some embodiments, the electrophoretic display panel includes a pixel electrode layer and a first insulating layer, and the manufacturing method further includes: forming a first insulating layer on the second metal layer so that the first insulating layer covers the second metal layer; a pixel electrode layer is formed over the first insulating layer, and the pixel electrode layer is processed to form each pixel electrode.

According to the electrophoretic display panel and the manufacturing method thereof, at least one metal wire in the display area is arranged on the second metal layer, so that the thin design of the panel is facilitated, and the space occupied by the first metal layer and/or the third metal layer can be reduced. Therefore, the area of the first capacitor plate and/or the second capacitor plate can be increased, so that the overlapping area between the first capacitor plate and the second capacitor plate is increased, and the capacitance between the first capacitor plate and the second capacitor plate in the charging stage is increased, so that the display requirement is met. In addition, the second metal layer is used for arranging the routing of partial metal line replacement, and the line replacement requirement of any number of data lines can be met, so that the design of the electrophoretic display panel is more flexible and is not influenced by the proportional relation between the data lines and the scanning lines.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a top view of a conventional electrophoretic display panel;

FIG. 2 is a schematic structural diagram of an embodiment of an electrophoretic display panel provided in the present application;

FIG. 3 is a cross-sectional structural view at A-A' of the electrophoretic display panel shown in FIG. 2;

fig. 4 is a schematic structural diagram of another embodiment of an electrophoretic display panel provided in the present application;

fig. 5 is a sectional structural view at B-B' of the electrophoretic display panel shown in fig. 4;

fig. 6 is a sectional structural view at C-C' of the electrophoretic display panel shown in fig. 4;

fig. 7 is a schematic structural diagram of another embodiment of an electrophoretic display panel provided in the present application;

fig. 8 is a schematic diagram of a trace of an electrophoretic display panel provided in the present application;

FIG. 9 is a flow chart of one embodiment of a method of manufacturing provided herein.

Detailed Description

The principles and features of the present application are described in further detail below with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Referring to fig. 2 and fig. 3, fig. 2 is a schematic structural diagram of an embodiment of an electrophoretic display panel provided in the present application; fig. 3 is a sectional structural view at a-a' of the electrophoretic display panel shown in fig. 2. As shown in fig. 3, the electrophoretic display panel may include: a substrate 10, a first metal layer 11, a second metal layer 12 and a third metal layer 13.

In the present embodiment, the substrate 10 may include a display region (e.g., a region formed by a dotted line in fig. 2) and a non-display region (e.g., a region between the dotted line and a solid line in fig. 2). The first metal layer 11 is located on the substrate 10, and the first metal layer 11 is formed with a first capacitor plate 21. The second metal layer 12 is located on the first metal layer 11, and the second metal layer 12 is formed with a plurality of light-shielding regions 23. And the third metal layer 13 may be located between the first metal layer 11 and the second metal layer 12, and the third metal layer 13 is formed with a second capacitor plate 22. That is, the first metal layer 11, the third metal layer 13, and the second metal layer 12 are sequentially stacked in a direction away from the substrate 10.

Note that, in fig. 3, the reference numerals (e.g., 21) outside the parentheses represent the reference numerals of the electronic components in the electrophoretic display panel. The reference numbers (e.g., 11) in brackets in fig. 3 represent the numbers of the layers where the electronic components are located. This numbering is also used in the drawings of the following embodiments.

In this embodiment, the electrophoretic display panel may further include a plurality of metal lines extending in the second direction and arranged in the first direction. The metal lines may be used to transmit data signals to the data lines. At least one metal replacement line in each metal replacement line can be located in the display area, so that the space occupied by the metal replacement lines in the non-display area can be reduced, and the narrow frame design is facilitated. Here, the metal lines in the display region may be disposed on any film layer of the electrophoretic display panel. For example, a metal film layer for forming a metal line is added on the electrophoretic display panel. For another example, in order to simplify the manufacturing process, a metal line may be formed on any existing metal film layer of the electrophoretic display panel.

In this embodiment, there is at least one metal line formed in the second metal layer in the at least one metal line in the display area. As shown in fig. 3, metal line 241 and metal line 242 may be formed in first metal layer 11, and metal line 243 and metal line 244 may be formed in second metal layer 12. This reduces the space occupied by the metal strap in the first metal layer 11 and/or the third metal layer 13, and thus increases the area of the first capacitor plate 21 and/or the second capacitor plate 22. As shown in fig. 2, the metal line 241 and the metal line 242 are disposed on the same layer as the first capacitor plate 21 and are electrically connected to one data line 27 through a via hole. The metal line 243 and the metal line 244 are disposed on the same layer as the light shielding region 23 and electrically connected to one data line 27 through a via hole. Since the capacitance between the two capacitor plates is related to the overlapping area between the two capacitor plates, i.e. under the same condition, the larger the overlapping area is, the larger the capacitance is. At this time, compared with the first capacitor plate 21 and the second capacitor plate 22 located between the metal line change 241 and the metal line change 242, the first capacitor plate 21 and the second capacitor plate 22 located between the metal line change 242 and the metal line change 244 may extend in the first direction toward the direction close to the metal line change 244 to increase the area of the first capacitor plate 21 and the second capacitor plate 22, so that the overlapping area between the two may be increased, and the capacitance between the two in the charging stage may be increased. Therefore, in the holding stage, if other conditions are the same (for example, the areas of the pixel electrodes are the same), the first capacitor plate and the second capacitor plate can respectively supplement electric energy to the pixel electrode and the common electrode better, so that the electrophoretic particles move to corresponding positions to meet the display requirements, and the picture display is realized.

It is understood that the electrophoretic display panel in this embodiment only describes the film layer structure related to the invention. Other film structures, such as insulating layers, thin film transistors, etc., may also be included between the films. In addition, the number of the electronic elements shown in fig. 2 is only schematic, and the display area of the electrophoretic display panel is usually provided with a plurality of data lines, a plurality of metal exchange lines, a plurality of groups of capacitor plates, a plurality of pixel electrodes, and the like. And after at least part of the metal exchange lines are formed on the second metal layer, the number of the metal exchange lines electrically connected with each data line can be set at will so as to reduce the influence of resistance and increase the transmission intensity of data signals.

With continued reference to fig. 4-6, fig. 4 is a schematic structural diagram of another embodiment of an electrophoretic display panel provided in the present application; fig. 5 is a sectional structural view at B-B' of the electrophoretic display panel shown in fig. 4; fig. 6 is a sectional structural view at C-C' of the electrophoretic display panel shown in fig. 4. As shown in fig. 5, the electrophoretic display panel in this embodiment also includes a substrate 10, a first metal layer 11, a second metal layer 12, a third metal layer 13, a first capacitor plate 21, a second capacitor plate 22, a light shielding region 23, and a metal line 24, as in fig. 2. The positional relationship between the film layers can be referred to in the related description in fig. 3, and is not described herein again.

Unlike fig. 2, the electrophoretic display panel in the present embodiment may further include a thin film transistor, a plurality of scan lines 26, and a plurality of data lines 27. Data signals can be supplied to the respective pixel electrodes through these electronic elements. As shown in fig. 6, the thin film transistor includes a gate electrode 251, a source electrode 252, a drain electrode 253, and a channel 254. The scan line is generally electrically connected to the gate electrode 251 of the thin film transistor; the data line is electrically connected to one of the source electrode 252 and the drain electrode 253 of the thin film transistor; meanwhile, the other end of the source electrode 252 and the drain electrode 253 of the thin film transistor is electrically connected to the pixel electrode 28.

The thin film transistor may be an amorphous silicon (α -Si) thin film transistor, in a process for forming a channel of the thin film transistor, a plurality of vapor deposition techniques (such as glow discharge, vacuum evaporation, chemical vapor deposition, etc.) may be used to process a monosilane or disilane raw material to form an amorphous silicon film, and then the amorphous silicon film may be patterned into a channel.

It should be noted that the electrophoretic display panel generally uses a total reflection technology to display a picture, that is, the electrophoretic display panel depends on the illumination of a light source in the external environment or a light source disposed on the surface of the electrophoretic display panel, as shown by the arrow in fig. 6. In order to avoid the light source affecting the carriers in the channel 254, the tft is typically located on the lower side of the second metal layer 12 (i.e., the side facing away from the light source). And the orthographic projection of the channel 254 to the second metal layer 12 is located within one of the light-blocking regions 23.

In the present embodiment, in order to simplify the manufacturing process and facilitate the thin design of the panel, the gate electrode 251, the source electrode 252, the drain electrode 253, the scan line 26 and the data line 27 may be formed on each metal film layer of the electrophoretic display panel. As an example, as shown in fig. 6, the gate electrode 251 may be formed on the first metal layer 11. The source 252 and the drain 253 may be formed at the third metal layer 13. Channel 254 is formed in semiconductor layer 14. The semiconductor layer 14 may be (but is not limited to) located between the first metal layer 11 and the third metal layer 13 as shown in fig. 6. In some application scenarios, the semiconductor layer may also be located between the substrate and the first metal layer. In addition, as can be seen from fig. 4 and 5, a plurality of scan lines 26 may also be formed on the first metal layer 11 so as to provide gate driving signals to the gates. And the scan lines 26 extend in a second direction and are arranged in a first direction. A plurality of data lines 27 may be formed on the third metal layer 13 to supply data signals to the source or drain electrodes. The data lines 27 extend in a first direction, are arranged in a second direction, and are electrically connected to at least one metal line 24.

As shown in fig. 4, the data line 27 may be electrically connected to the two metal wirings 24 through a via. One of the metal lines 24 may be in the same layer as the scan lines 26, and the other metal line 24 may be in the same layer as the light-shielding region 23. This can reduce attenuation of the data signal due to the resistance of the data line 27, thereby increasing the intensity of the data signal transmitted on the data line 27.

As can be seen from fig. 5, the electrophoretic display panel in this embodiment may further include a pixel electrode layer 15 and a common electrode layer 16. The pixel electrode layer 15 is located between the second metal layer 12 and the common electrode layer 16. And an electrophoretic film 17 is disposed between the pixel electrode layer 15 and the common electrode layer 16. The pixel electrode 28 of the pixel electrode layer 15 receives a data signal, and the common electrode of the common electrode layer 16 receives a common voltage signal. In the charging phase, after the pixel electrode 28 receives the data signal and the common electrode receives the common voltage signal, an electric field may be formed between the pixel electrode 28 and the common electrode. Thus, under the action of the electric field, the electrophoretic particles in the electrophoretic film 17 move, thereby realizing the picture display.

In addition, in order that the first and

second capacitor plates

21 and 22 may store electric energy during the charging phase and may transmit electric energy to the pixel electrode 28 and the common electrode during the holding phase, the first capacitor plate 21 may receive a data signal and be electrically connected to the pixel electrode 28; and the second capacitor plate 22 may receive a common voltage signal and is electrically connected to the common electrode.

As shown in fig. 4, the electrophoretic display panel may further include a common signal line 29. The common signal line 29 may be used to transmit a common voltage signal to the common electrode. To further simplify the manufacturing process, the common signal line 29 may be formed in the third metal layer so as to be electrically connected to the second capacitor plate 22. And the second capacitor plate 22 and the common electrode may be electrically connected by a common signal line 29. For example, the common signal line 29 is in contact with the second capacitor plate 22 in the display region, while the common signal line 29 is electrically connected to the common electrode in the non-display region through a via hole. It can be understood that the common signal lines 29 can also extend along the first direction and be arranged along the second direction, so as to avoid interference with the routing of the data lines 27, and make the overall routing of the panel more regular and beautiful, and improve the display effect.

Further, the first capacitor plate 21 and the pixel electrode 28 may be electrically connected through a via hole. The via hole is disposed in an at least partially overlapping region of an orthographic projection of the first capacitor plate 21 to the pixel electrode layer and one of the pixel electrodes 28. As shown in fig. 4, the source of the thin film transistor of the dual gate structure is connected to the data line 27, and the drain of the thin film transistor is electrically connected to the first capacitor plate 21 and the pixel electrode 28 through the via hole 20. As can be seen from fig. 6, the drain electrode 252, the first capacitor plate 21 and the pixel electrode 28 of the thin film transistor have an overlapping region in the orthographic projection of the substrate 10. And the via 20 is disposed in an overlapping region therebetween.

It will be appreciated that to reduce the via depth, reduce the manufacturing process difficulty and the manufacturing reject ratio, the second capacitor plate may be electrically connected to the pixel electrode, as an example. And the first capacitor plate may be electrically connected to the common electrode. At this time, the common signal line may be formed at the first metal layer. And in order to avoid interference with the trace of the scan line, the common signal lines may extend along the second direction and be arranged along the first direction.

As can be seen from the above, the electrophoretic display panel is usually of a total reflection type, and the second metal layer is only provided with the light-shielding region 23. The metal exchange line 24 can be arbitrarily disposed on the second metal layer without affecting the function of the light-shielding region. And the orthographic projection of the pixel electrode 28 onto the second metal layer may partially overlap the at least one metal bar 24. As shown in fig. 4, by patterning the second metal layer, a partial metal bar 24 can be formed, which increases the capacitance between the first capacitor plate 21 and the second capacitor plate 22, and also allows for more flexibility in the design of the panel. To further increase the capacitance between the first capacitor plate 21 and the second capacitor plate 22, each metal exchange line 24 may be formed in the second metal layer, as shown in fig. 7. In addition, in some application scenarios, in addition to increasing the areas of the first capacitor plate and the second capacitor plate, the area of the pixel electrode may also be increased, so that the overlapping area between the pixel electrode and the common electrode may be increased. Thus, more capacitance can be formed and stored between the pixel electrode and the common electrode in the charging stage.

It should be noted that, as shown in fig. 5, when the metal line 24 for transmitting the data signal is disposed on the second metal layer 12, considering that the second metal layer 12 is adjacent to the pixel electrode layer 15, in order to avoid the data signal being directly provided to the pixel electrode through the metal line 24, the electrophoretic display panel may further include the first insulating layer 18 between the pixel electrode layer 15 and the second metal layer 12. In this way, the first insulating layer 18 can function as a mutual barrier insulation between the two. And the thickness of the first insulating layer 18 may be set according to practical circumstances.

Meanwhile, in order to allow the thin film transistor to perform a switching control function, as shown in fig. 6, the electrophoretic display panel may further include a second insulating layer 19 between the first metal layer 11 and the semiconductor layer 14. In this way, the second insulating layer 19 can serve as an insulator between the gate and the channel. It should be noted that, in order to ensure that the thin film transistor can be turned on after the gate electrode receives the gate driving signal, the thickness of the second insulating layer 19 is not usually set to be very thick. That is, the thickness of the second insulating layer 19 can perform an insulating function without affecting the performance of the thin film transistor.

Alternatively, the first insulating layer 18 may have the same thickness as the second insulating layer 19 in order to simplify the manufacturing process. And the first insulating layer 18 and the second insulating layer 19 can be made of the same material, thereby reducing the variety of production raw materials, adjustment of production process parameters and the like. In addition, when the second capacitor plate 22 is electrically connected to the common electrode, a capacitance is also generated between the second capacitor plate 22 and the pixel electrode 28. Since capacitance is related to the distance between the capacitor plates, the smaller the thickness of the first insulating layer 18, the smaller the distance between the second capacitor plate 22 and the pixel electrode 28 can be made. This can help to increase the capacitance between the two, and thus increase the electrical energy stored by the pixel electrode.

It is understood that as the manufacturing technology is continuously developed, the thickness of each film layer in the electrophoretic display panel is also continuously changed. As an example, in order to realize a slim design of the electrophoretic display panel, the thickness L of the first insulating layer may satisfy: l is less than or equal to 350 nanometers. That is, as the production technology advances, the thinner the electrophoretic display panel can be made. Accordingly, the thickness L of the first insulating layer may be smaller. For the current production technology, the thickness L of the first insulating layer can be made to satisfy: l is more than or equal to 250 nanometers and less than or equal to 350 nanometers.

In addition, as can be seen from fig. 1, when the number of rows of the pixel electrodes in the second direction is greater than the number of columns of the pixel electrodes in the first direction, even if one data line is electrically connected to one metal line, some data lines cannot be replaced. In the electrophoretic display panel in each of the embodiments of the present application, by disposing at least one metal line in the second metal layer, the number of the metal lines is not limited by the ratio of the number of rows to the number of columns of the pixel electrode, so that each data line can be electrically connected to at least one metal line to transmit a data signal. Reference may be made to fig. 8, which shows a schematic diagram of a trace of an electrophoretic display panel provided in the present application.

The electrophoretic display panel in this embodiment comprises an array of 8 rows by 5 columns of pixel electrodes (not shown in the figure). At this time, in order to implement the screen display, as shown in fig. 8, the electrophoretic display panel may include at least 5 scan lines 26 extending in the second direction, at least 8 data lines 27 extending in the first direction, and at least 8 metal exchange lines 24 extending in the second direction. The metal line 241-245 electrically connected to the first 5 data lines 27 may be formed in a first metal layer, i.e., disposed on the same layer as the scan line 26. And metal bar 246-metal bar 248 electrically connected to the remaining 3 data lines 27 may be formed on a second metal layer, i.e., disposed on the same layer as the light-shielding region. Therefore, no matter the electrophoresis display panel is of a transverse screen structure or a vertical screen structure, the line changing requirement of the data lines can be met. Moreover, the metal exchange line 246-the metal exchange line 248 is disposed on the second metal layer, which does not affect the area of the capacitor plate corresponding to the 5 th row of pixel electrodes.

Optionally, an orthogonal projection of the metal line disposed on the second metal layer to the first metal layer may at least partially overlap the scan line. That is, the metal bar 246-metal bar 248 in fig. 8 may respectively overlap one of the scan lines 26 in the display area. Therefore, the wiring is more regular and attractive, and the display effect is improved.

The embodiments of the present application also provide a manufacturing method, which can be used to manufacture the electrophoretic display panel described in the above embodiments. Referring to fig. 9, a flow chart of one embodiment of a method of manufacturing provided herein is shown. The manufacturing method comprises the following steps:

step 901, prepare a substrate. Wherein the substrate may include a display region and a non-display region. The substrate herein may be purchased (purchased); or may be self-made, for example, by a series of processes from raw materials.

Step 902, forming a first metal layer in a display region of a substrate, and processing the first metal layer to form a first capacitor plate.

Step 903, forming a third metal layer on the first metal layer, and processing the third metal layer to form a second capacitor plate. The orthographic projection of the second capacitor plate onto the first metal layer should here largely coincide with the first capacitor plate.

Step 904, forming a second metal layer on the third metal layer, and processing the second metal layer to form a plurality of light-shielding regions and at least one metal line replacement. The electrophoretic display panel may include a plurality of metal lines for transmitting data signals to the data lines.

In some optional implementations of this embodiment, the electrophoretic display panel may further include a pixel electrode layer and a first insulating layer. At this time, the manufacturing method may further include: forming a first insulating layer on the second metal layer so that the first insulating layer covers the second metal layer; a pixel electrode layer is formed over the first insulating layer, and the pixel electrode layer is processed to form each pixel electrode.

As an example, the main processes for manufacturing the electrophoretic display panel in the embodiment of fig. 7 by using the manufacturing method of the present embodiment may be as follows:

1) and forming a first metal layer on the prepared substrate at a position corresponding to the display area. The first metal layer is patterned to form a first capacitor plate, a scanning line and a grid electrode of the thin film transistor.

2) An insulating layer is formed overlying the first metal layer. The insulating layer is the second insulating layer. The thickness of the insulating layer should not be too thick, otherwise the movement of carriers in the channel under the action of the gate driving signal is affected, and the performance of the thin film transistor is affected.

3) A semiconductor layer is formed on the insulating layer. The semiconductor layer is processed to form a channel of the thin film transistor.

4) An insulating layer is formed covering the semiconductor layer. And via holes are respectively formed at the positions of the insulating layer corresponding to the first capacitor plate and the channel.

5) Forming a third metal layer on the insulating layer of step 4). And patterning the third metal layer to form a second capacitor plate, a data line, a common signal line, and a source and a drain of the thin film transistor. And the source electrode and the drain electrode of the thin film transistor are respectively connected with the channel through the through hole. And the drain electrode is connected with the first capacitor plate through the via hole.

6) And forming an insulating layer covering the third metal layer. And forming a via hole at a position of the insulating layer corresponding to the data line.

7) Forming a second metal layer on the insulating layer of step 6). And patterning the second metal layer to form a light shielding area and a metal exchange line. The metal replacement wire is connected with the data wire through the through hole.

8) And forming an insulating layer covering the second metal layer. And forming a via hole in the insulating layer at a position corresponding to the drain electrode of the thin film transistor. The insulating layer is the first insulating layer. The thickness of the insulating layer is also not likely to be too thick in order to reduce the effect on the capacitance between the pixel electrode and the second capacitor plate. For example, the thickness of the insulating layer may be the same as that of the insulating layer in step 2). As production technology continues to improve, for example, the thickness of the insulating layer may be no greater than 350 nm. In some production processes, the thickness L of the insulating layer may also satisfy: l is more than or equal to 250 nanometers and less than or equal to 350 nanometers.

9) Forming a pixel electrode layer on the insulating layer of step 8). And processing the pixel electrode layer to form a pixel electrode array. And each pixel electrode is connected with the drain electrode of the thin film transistor through a through hole.

It should be noted that the process of manufacturing the electrophoretic display panel in the embodiment of fig. 7 further includes forming a common electrode, forming an electrophoretic film between the common electrode and the pixel electrode, and the like. These processes are the same as the conventional processes and are not described herein.

The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. An electrophoretic display panel, comprising:

a substrate including a display region and a non-display region;

the first metal layer is positioned on the substrate, and a first capacitor plate is formed on the first metal layer;

the second metal layer is positioned on the first metal layer, and a plurality of shading areas are formed on the second metal layer;

a third metal layer located between the first metal layer and the second metal layer, the third metal layer forming a second capacitor plate;

and a plurality of metal exchange lines extending along the second direction and arranged along the first direction for transmitting data signals to the data lines, wherein at least one metal exchange line in each metal exchange line is positioned in the display area, and at least one metal exchange line formed in the second metal layer exists in the at least one metal exchange line.

2. The electrophoretic display panel according to claim 1, wherein the electrophoretic display panel comprises a thin film transistor, a plurality of scan lines, and a plurality of data lines for supplying data signals to the respective pixel electrodes;

the thin film transistor comprises a grid electrode, a source electrode, a drain electrode and a channel, wherein the orthographic projection of the channel to the second metal layer is positioned in one shading area;

the grid electrode is formed on the first metal layer, the source electrode and the drain electrode are formed on the third metal layer, and the channel is formed on a semiconductor layer, wherein the semiconductor layer is positioned between the first metal layer and the third metal layer;

the plurality of scanning lines are formed on the first metal layer, extend along a second direction, are arranged along a first direction, and are used for providing gate driving signals for the gate;

the data lines are formed on the third metal layer, extend along a first direction and are arranged along a second direction, and the data lines are electrically connected with at least one metal exchange line.

3. The electrophoretic display panel according to claim 2, wherein the electrophoretic display panel comprises a pixel electrode layer and a common electrode layer;

the pixel electrode layer is positioned between the second metal layer and the common electrode layer, and an electrophoretic film is arranged between the pixel electrode layer and the common electrode layer;

the pixel electrode of the pixel electrode layer receives a data signal, and the common electrode of the common electrode layer receives a common voltage signal.

4. The electrophoretic display panel of claim 3, wherein the first capacitor plate is electrically connected to the pixel electrode and the second capacitor plate is electrically connected to the common electrode.

5. The electrophoretic display panel according to claim 4, wherein the electrophoretic display panel comprises a common signal line for transmitting a common voltage signal to the common electrode;

the common signal line is formed on the third metal layer, and the second capacitor polar plate is electrically connected with the common electrode through the common signal line;

the first capacitor plate is electrically connected with the pixel electrode through a via hole, wherein the via hole is formed in an at least partial overlapping area of the orthographic projection of the first capacitor plate to the pixel electrode layer and one of the pixel electrodes.

6. The electrophoretic display panel according to claim 3, wherein a forward projection of the pixel electrode to the second metal layer partially overlaps at least one metal bar.

7. The electrophoretic display panel according to one of claims 3 to 6, further comprising a first insulating layer between the pixel electrode layer and the second metal layer.

8. The electrophoretic display panel according to claim 7, further comprising a second insulating layer between the first metal layer and the semiconductor layer, wherein the second insulating layer has the same thickness as the first insulating layer.

9. An electrophoretic display panel as claimed in claim 7, wherein the thickness L of the first insulating layer satisfies: l is less than or equal to 350 nanometers.

10. An electrophoretic display panel as claimed in claim 9, wherein the thickness L of the first insulating layer satisfies: l is more than or equal to 250 nanometers and less than or equal to 350 nanometers.

11. A manufacturing method for manufacturing an electrophoretic display panel according to any one of claims 1 to 10, the manufacturing method comprising:

preparing a substrate, wherein the substrate comprises a display area and a non-display area;

forming a first metal layer in a display area of the substrate, and processing the first metal layer to form a first capacitor plate;

forming a third metal layer on the first metal layer, and processing the third metal layer to form a second capacitor plate;

forming a second metal layer on the third metal layer, and processing the second metal layer to form a plurality of shading areas and at least one metal line change;

the electrophoresis display panel comprises a plurality of metal exchange lines used for transmitting data signals to the data lines.

12. The manufacturing method according to claim 11, wherein the electrophoretic display panel includes a pixel electrode layer and a first insulating layer, the manufacturing method further comprising:

forming the first insulating layer on the second metal layer so that the first insulating layer covers the second metal layer;

and forming the pixel electrode layer on the first insulating layer, and processing the pixel electrode layer to form each pixel electrode.