CN107291626B - Data storage method and device - Google Patents
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- CN107291626B CN107291626B CN201710465774.5A CN201710465774A CN107291626B CN 107291626 B CN107291626 B CN 107291626B CN 201710465774 A CN201710465774 A CN 201710465774A CN 107291626 B CN107291626 B CN 107291626B
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Abstract
The present disclosure relates to data storage, and belongs to the field of electronic technology. The method comprises the following steps: receiving a storage mode setting instruction of a target storage area, wherein the storage mode setting instruction carries a target storage mode, and the target storage mode is a single-layer cell SLC mode, a multi-layer cell MLC mode or a three-layer cell TLC mode; in the Nand chip, setting the storage mode of a target storage area as a target storage mode; and performing data storage operation in the target storage area through the target storage mode. By adopting the method and the device, the storage modes of the target storage area can be optionally converted into each other according to requirements through the storage mode setting instruction. The setting or conversion operation of the storage mode can be well controlled through the operation of the storage mode setting instruction, so that the flexibility of the storage mode setting operation is improved, and the actual requirements of users are better met.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a data storage method and apparatus.
Background
At present, the storage capacity of Nand chips (a computer flash memory chip) is getting larger and larger, and users generally cannot use all the storage space of Nand chips at the initial stage of using Nand chips, so that the unused storage space causes resource idle and waste.
In order to solve the above problem, when the usage amount of the Nand chip does not exceed a predetermined capacity, the memory mode of the Nand chip may be set to an SLC (Single-Level Multi-Level Cell) mode; when the usage amount of the Nand chip exceeds a predetermined capacity, the memory mode of the Nand chip may be set to an MLC (Multi-Level Cell) mode or a TLC (Triple-Level Cell) mode. The SLC mode is more stable and faster to write than both the MLC mode and the TLC mode. However, the storage space obtained by storing in the SLC mode is small, and the storage space obtained by storing in the MLC mode or TLC mode is large, for example, the storage space of a Nand chip in the SLC mode is 5G, and the storage space of a Nand chip in the MLC mode is 10G.
In the prior art, the storage mode of the Nand chip can be automatically switched, and the switching mode is to automatically trigger the chip to switch the storage mode through the storage data volume, so that the mode has poor operation flexibility and cannot well meet the actual requirements of users.
Disclosure of Invention
To overcome the problems in the related art, the present disclosure provides a data storage method. The technical scheme is as follows:
according to a first aspect of the embodiments of the present disclosure, there is provided a data storage method, the method including:
receiving a storage mode setting instruction of a target storage area, wherein the storage mode setting instruction carries a target storage mode, and the target storage mode is a single-layer cell SLC mode, a multi-layer cell MLC mode or a three-layer cell TLC mode;
in a Nand chip, setting the storage mode of the target storage area as the target storage mode;
and performing data storage operation in the target storage area through the target storage mode.
Optionally, the original storage mode of the target storage area is MLC mode or TLC mode, and the target storage mode is SLC mode, and the method further includes:
acquiring the data quantity of the stored data of the target storage area as a first data quantity,
acquiring the maximum data volume which can be stored in the whole target storage area in the target storage mode, and taking the maximum data volume as a second data volume;
and if the second data amount is larger than or equal to the first data amount, setting the storage mode of the target storage area to the target storage mode is executed.
Optionally, the method further comprises:
and when detecting that data read-write abnormality occurs in the storage area of the MLC mode or the TLC mode in the Nand chip, switching the storage mode of the storage area of the MLC mode or the TLC mode to be the SLC mode.
Optionally, the initial storage mode of the Nand chip is an SLC mode.
Optionally, the storage mode setting instruction further includes a start address and an end address carrying the target storage area;
in the Nand chip, setting the storage mode of the target storage area to the target storage mode includes:
and in the Nand chip, setting the storage mode of the storage area between the starting address and the ending address as a target storage mode.
Optionally, the storage mode setting instruction further carries an identifier of a logical storage unit included in the target storage area;
in the Nand chip, setting the storage mode of the target storage area to the target storage mode includes:
and in the Nand chip, setting the storage mode of the logic storage unit corresponding to the identifier as a target storage mode.
According to a second aspect of embodiments of the present disclosure, there is provided a data storage apparatus, the apparatus comprising:
the device comprises a receiving module, a storage mode setting module and a processing module, wherein the receiving module is used for receiving a storage mode setting instruction of a target storage area, and the storage mode setting instruction carries a target storage mode, and the target storage mode is a single-layer cell SLC mode, a multi-layer cell MLC mode or a three-layer cell TLC mode;
the setting module is used for setting the storage mode of the target storage area to the target storage mode in a Nand chip;
and the first storage module is used for carrying out data storage operation in the target storage area through the target storage mode.
Optionally, the original storage mode of the target storage area is an MLC mode or a TLC mode, and the target storage mode is an SLC mode, and the apparatus further includes:
the first acquisition module is used for acquiring the data volume of the stored data of the target storage area, and taking the data volume as a first data volume;
the second acquisition module is used for acquiring the maximum data volume which can be stored in the whole target storage area in the target storage mode and taking the maximum data volume as a second data volume;
and the second storage module is used for setting the storage mode of the target storage area to the target storage mode if the second data volume is larger than or equal to the first data volume.
Optionally, the apparatus further comprises:
and the switching module is used for switching the storage mode of the storage area in the MLC mode or the TLC mode into the SLC mode when detecting that data read-write abnormality occurs in the storage area in the MLC mode or the TLC mode in the Nand chip.
Optionally, the initial storage mode of the Nand chip is an SLC mode.
Optionally, the storage mode setting instruction further includes a start address and an end address carrying the target storage area;
the setting module is used for setting the storage mode of the storage area between the starting address and the ending address to be a target storage mode in a Nand chip.
Optionally, the storage mode setting instruction further carries an identifier of a logical storage unit included in the target storage area;
the setting module is used for setting the storage mode of the logic storage unit corresponding to the identification into a target storage mode in the Nand chip.
According to a third aspect of the embodiments of the present disclosure, there is provided a terminal, which includes a processor and a memory, where at least one instruction, at least one program, a code set, or a set of instructions is stored in the memory, and the at least one instruction, the at least one program, the code set, or the set of instructions is loaded and executed by the processor to implement the above data storage method.
According to a fourth aspect of the embodiments of the present disclosure, there is provided a computer-readable storage medium having stored therein at least one instruction, at least one program, a set of codes, or a set of instructions, which is loaded and executed by a processor to implement the above-mentioned data storage method.
The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects:
in the embodiment of the disclosure, a storage mode setting instruction of a target storage area is received, where the storage mode setting instruction carries a target storage mode, and the target storage mode is not limited to an SLC mode, an MLC mode, or a TLC mode. In addition, in this embodiment, the setting or conversion of the storage mode completely follows the received storage mode setting instruction of the target area, so that the setting or conversion operation of the storage mode can be well controlled through the operation of the storage mode setting instruction, the flexibility of the storage mode setting operation is improved, and the actual requirements of users are better met.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. In the drawings:
FIG. 1 is a flow chart illustrating a method of data storage according to an exemplary embodiment;
FIG. 2 is a schematic diagram illustrating a software interface for configuring a Nand chip in accordance with one illustrative embodiment;
FIG. 3 is a schematic diagram illustrating another software interface for configuring a Nand chip in accordance with an exemplary embodiment;
FIG. 4 is a flow chart illustrating a method of data storage according to another exemplary embodiment;
FIG. 5 is a schematic diagram illustrating a data storage device in accordance with an exemplary embodiment;
FIG. 6 is a schematic diagram illustrating a data storage device in accordance with another exemplary embodiment;
FIG. 7 is a schematic diagram illustrating a data storage device in accordance with yet another exemplary embodiment;
fig. 8 is a block diagram of a terminal according to an example embodiment.
With the foregoing drawings in mind, certain embodiments of the disclosure have been shown and described in more detail below. These drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the concepts of the disclosure to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
An exemplary embodiment of the present disclosure provides a data storage method, which may be used in a terminal or a server equipped with a Nand chip. The embodiment of the present disclosure takes a terminal as an example to perform detailed description of the scheme, and other situations are similar to the above, and the present disclosure is not repeated. The terminal can be a mobile phone, a tablet computer, a desktop computer, a notebook computer and the like. The terminal may include a processor, memory, etc. The processor, which may be a CPU (Central Processing Unit), may be used to control the memory to perform a storage operation, control the memory to perform a mode conversion, and the like. The memory, which may be Flash (Flash memory) or the like, may be used to store data. In the scheme, a data storage method is provided for Nand Flash.
The process flow shown in fig. 1 will be described in detail below with reference to the embodiments, and the contents may be as follows:
step S110, receiving a storage mode setting instruction of the target storage area, where the storage mode setting instruction carries a target storage mode.
Wherein the target storage mode is SLC mode, MLC mode or TLC mode.
The memory mode of the Nand chip includes, but is not limited to, SLC mode, MLC mode and TLC mode, and all of the three memory modes have their own disadvantages and advantages. Among them, the SLC mode has advantages of longer lifetime, faster access speed, higher stability, etc. compared to the MLC mode and TLC mode. However, the SLC mode has a small memory amount compared to the MLC mode and the TLC mode. Generally, the memory capacity of SLC mode is one-half of MLC, which is one-half of TLC. For example, the data size of a Nand chip operating in MLC mode is 256G, and if the Nand chip operates in SLC mode, the data size is reduced from 256G to 128G.
In implementation, the scheme can be applied to the process of configuring the terminal by a technician. For example, when a technician debugs a mobile phone, the Android system and some necessary default system software need to be installed in the mobile phone. After the storage space occupied by the Android system and the default system software is preliminarily estimated, technicians can select a storage mode of a target storage area according to actual requirements so as to ensure that the Android system and the default system software can stably run in a mobile phone.
The user can select the target storage area according to the self requirement and set the target storage mode aiming at the target storage area. For example, a user may open a software interface for configuring a Nand chip on one computer device, provide a window set for a target storage area and a target storage mode setting window in the software interface, and select a desired target storage area from candidate storage areas in a pull-down menu of the target storage area setting window, and select a target storage mode corresponding to the target storage area from candidate target storage modes in the pull-down menu of the target storage mode setting window. As shown in fig. 2, a schematic diagram of a software interface for configuring a Nand chip is shown in accordance with an exemplary embodiment. After the target storage area and the target storage mode are selected, the 'confirm' button in the setting window can be clicked, and the terminal can receive a storage mode setting instruction. Of course, the terminal may also automatically trigger generation of the storage mode setting instruction when detecting that the remaining storage space of the target storage area is insufficient, which is not limited in the embodiment of the present invention.
Step S120, in the Nand chip, the storage mode of the target storage area is set as the target storage mode.
Optionally, the target storage area may be specified by an identifier of the logical storage unit, and correspondingly, the storage mode setting instruction further carries the identifier of the logical storage unit included in the target storage area, and the processing in step S120 may be as follows: and in the Nand chip, setting the storage mode of the logic storage unit corresponding to the identification as a target storage mode.
In implementation, during initialization of the Nand chip, the memory area of the Nand chip is generally divided into N logical memory units, and each logical memory unit has its own identifier. For example, a piece of Nand chip is divided into 32 logical memory units, and the identifications of the logical memory units are 1, 2 and 3 … … 32 in sequence. In this embodiment, any logical storage unit may be used as the target storage area, and further, the target storage area also includes the identifier of the corresponding logical storage unit. In order to accurately locate the target storage area in which the storage mode needs to be set, an identifier of a logical storage unit included in the target storage area, such as "area 1, area 2, and area 3" in the pull-down menu in fig. 2, may be set, and the terminal may generate the storage mode setting instruction according to the identifier. Furthermore, the Nand chip may be controlled to set the storage mode of the logic storage unit corresponding to the identifier to the target storage mode according to the storage mode setting instruction, for example, the target storage mode may be set for the selected target storage area in the column of "target storage mode" in fig. 2. For example, it is necessary to set the storage mode of the logical memory cell C to the SLC mode, in which the flag of the logical memory cell C is "3". First, the terminal may generate a storage mode setting instruction containing the flag "3" and the target storage mode "SLC". Then, the terminal can control the Nand chip to set the storage mode of the logic storage unit corresponding to the identifier "3" to be the SLC mode according to the instruction.
Based on the mode, the target storage area is designated through the identification of the logic storage unit, and the flexibility of setting the target storage area is increased.
It should be noted that, in the method provided in this embodiment, the conversion of the storage mode of the target storage area is flexible, and not only the storage mode may be set from SLC mode to MLC mode, but also the storage mode may be set from MLC mode to SLC mode. When the storage mode is set from the MLC mode to the SLC mode, a reverse transition process occurs inside the target storage area.
Alternatively, the target storage area may be specified by an identifier of the logical storage unit, and correspondingly, the storage mode setting instruction further includes a start address and an end address carrying the target storage area, and the processing of step S120 may be as follows: in the Nand chip, the memory mode of the memory region between the start address and the end address is set as the target memory mode.
In implementation, it is also specified in this embodiment that the storage mode of the storage area between the start address and the end address of the target storage area is set as the target storage mode in the Nand chip, unlike the way of setting the storage mode of the entire logical storage unit. The storage mode of the storage area between the start address and the end address in any logical storage unit included in the target storage area may be set as the target storage mode. For example, a window for setting the start address and the end address of the target memory area is provided in a software interface for configuring the Nand chip, and the user can set the target memory area by inputting the start address and the end address in the window. In addition, a setting window of a target storage mode for the target storage region set by the user, such as a pull-down menu including "SLC mode", "MLC mode", and "TLC mode", may also be provided in the software interface. FIG. 3 is a schematic diagram of another software interface for configuring a Nand chip, according to an exemplary embodiment. In a possible case, the addresses of a logical memory unit are from 00000000 to 00001000, and if a memory region from the start address 00000000 to the end address 00000100 needs to be selected as a target memory region in the logical unit, a corresponding operation can be performed in the software interface to achieve the setting of the target memory region. Finally, the storage mode of the set target storage area may be set as the target storage mode.
Based on the mode, the target storage area can be selected according to the starting address and the ending address of the target storage area, so that the target storage area is more flexibly selected.
And step S130, performing data storage operation in the target storage area through the target storage mode.
In implementation, after the target storage mode of the target storage area is set, the data storage operation may be performed in the target storage area through the target storage mode. For example, the target storage area is set to SLC mode in the original storage mode and to MLC mode in the target storage mode, and the target storage area includes 4GB of storage area where data is stored and 6GB of storage area where data is not stored. The 10GB target storage area operating in SLC mode may be expanded to the target storage area operating in MLC mode, where the expanded target storage area in MLC mode contains original 4GB stored data, and when new data is stored into the target storage area, the data storage operation is still performed in MLC mode.
Optionally, in order to prevent data overflow, when switching from the large-capacity storage mode to the small-capacity storage mode, it is further detected whether the data amount would exceed the capacity of the storage area, and accordingly, as shown in fig. 4, if the original storage mode of the target storage area is the MLC mode or the TLC mode, and the target storage mode is the SLC mode, the method provided in this embodiment may further include: step S210, acquiring the data volume of the stored data in the target storage area, taking the data volume as a first data volume, acquiring the maximum data volume which can be stored in the whole target storage area in the target storage mode, and taking the maximum data volume as a second data volume; in step S220, if the second data amount is greater than or equal to the first data amount, setting the storage mode of the target storage area to the target storage mode is performed.
It should be noted that, if the storage mode of the target storage area is changed from the MLC mode or the TLC mode to the SLC mode, the storage space of the target storage area is changed from large to small. If the data amount of the stored data in the target storage area is too large in the MLC mode or TLC mode, the target storage area converted to the SLC mode for storage may not contain the stored data, which may result in data loss. Therefore, in this embodiment, before the storage mode of the target storage area is switched from the MLC mode or the TLC mode to the SLC mode, whether to perform such switching may be determined according to the related data amount of the target storage area, so as to avoid the problem of data loss caused by insufficient storage space, and ensure the integrity of data.
For example, in a target storage area including 10GB of storage space when operating in MLC mode, first, the data amount of stored data in the original storage mode of the target storage area in MLC mode is acquired to be 4 GB. Then, the maximum data amount that the whole target storage area can store in the target storage mode SLC mode is acquired to be half of that in the MLC mode, namely 5 GB. And then, judging that the maximum data amount which can be stored in the target storage area in the target storage mode SLC mode is larger than the data amount of the stored data in the original storage mode MLC mode of the target storage area, and executing to set the storage mode of the target storage area to be the SLC mode.
For another example, in a target storage area containing 20GB of storage space when operating in TLC mode, first, the data amount of stored data in the original storage mode TLC mode of the target storage area is acquired to be 10 GB. Next, the maximum data amount that can be stored in the target storage mode SLC mode of the entire target storage region is acquired to be one fourth of that in the TLC mode, that is, 5 GB. And then, judging that the maximum data amount which can be stored in the target storage mode SLC mode of the whole target storage area is smaller than the data amount of the stored data in the original storage mode TLC mode of the target storage area, and not executing the setting of the storage mode of the target storage area to be the SLC mode.
In addition to the above, when the original storage mode of the target storage area is TLC and the target storage mode is MLC, the large storage space is also converted into the small storage space, so the above operation can be performed to avoid the problem of data loss due to insufficient storage space.
Optionally, in order to enable the Nand chip to operate normally, and when an abnormality occurs in the storage region in the MLC mode or the TLC mode, the storage mode may be switched to the stable SLC mode, and accordingly, the method provided by this embodiment may further include: and when detecting that data read-write abnormality occurs in the storage area of the MLC mode or the TLC mode in the Nand chip, switching the storage mode of the storage area of the MLC mode or the TLC mode to the SLC mode.
It should be noted that, since the MLC mode or TLC mode is more unstable than the target storage area operating in SLC mode, and thus is prone to data read/write abnormality in the MLC mode or TLC mode, if data read/write abnormality in the storage area of MLC mode or TLC mode in the Nand chip is detected, the storage mode of the storage area of MLC mode or TLC mode may be switched to SLC mode.
By the method, the target storage area can be ensured to work normally no matter what storage mode the target storage area works in.
Alternatively, the initial storage mode of the Nand chip may be SLC mode.
It should be noted that, because the Nand chip has a large storage space during initial use, which may not be used, and thus a large amount of idle storage space remains, the initial storage mode of the Nand chip can be set to the SLC mode, so as to ensure that the Nand chip has the characteristics of high access speed and high stability.
In the implementation, generally, the storage mode of the Nand chip can be firstly converted from the SLC mode to the MLC mode in the case of insufficient capacity, and then converted from the MLC mode to the TLC mode in the case of insufficient capacity, and of course, the storage mode of the Nand chip can also be directly converted from the SLC mode to the TLC mode.
In the embodiment of the disclosure, a storage mode setting instruction of a target storage area is received, where the storage mode setting instruction carries a target storage mode, and the target storage mode is not limited to an SLC mode, an MLC mode, or a TLC mode. In addition, in this embodiment, the setting or conversion of the storage mode completely follows the received storage mode setting instruction of the target area, so that the setting or conversion operation of the storage mode can be well controlled through the operation of the storage mode setting instruction, the flexibility of the storage mode setting operation is improved, and the actual requirements of users are better met.
Yet another exemplary embodiment of the present disclosure provides a data storage device, as shown in fig. 5, including:
the receiving module 510 is configured to receive a storage mode setting instruction of a target storage area, where the storage mode setting instruction carries a target storage mode, and the target storage mode is a single-layer cell SLC mode, a multi-layer cell MLC mode, or a three-layer cell TLC mode.
A setting module 520, configured to set the storage mode of the target storage area to the target storage mode in the Nand chip.
A first storage module 530, configured to perform a data storage operation in the target storage area through the target storage mode.
Optionally, as shown in fig. 6, an original storage mode of the target storage area is an MLC mode or a TLC mode, and a target storage mode is an SLC mode, where the apparatus provided in this embodiment further includes:
a first obtaining module 610, configured to obtain a data size of stored data in a target storage area, as a first data size;
a second obtaining module 620, configured to obtain a maximum data size that can be stored in the entire target storage area in the target storage mode, and use the maximum data size as a second data size;
and a second storing module 630, configured to perform setting the storage mode of the target storage area to the target storage mode if the second data amount is greater than or equal to the first data amount.
Optionally, as shown in fig. 7, the apparatus provided in the embodiment of the present invention further includes:
the switching module 710 is configured to switch the storage mode of the storage area in the MLC mode or the TLC mode to the SLC mode when detecting that data read/write abnormality occurs in the storage area in the MLC mode or the TLC mode in the Nand chip.
Optionally, the initial storage mode of the Nand chip is SLC mode.
Optionally, the storage mode setting instruction further includes a start address and an end address carrying the target storage area.
The setting module 520 is configured to set a storage mode of a storage area between a start address and an end address to a target storage mode in the Nand chip.
Optionally, the storage mode setting instruction further carries an identifier of a logical storage unit included in the target storage area.
The setting module 520 is configured to set, in the Nand chip, the storage mode of the logic storage unit corresponding to the identifier as the target storage mode.
In the embodiment of the disclosure, a storage mode setting instruction of a target storage area is received, where the storage mode setting instruction carries a target storage mode, and the target storage mode is not limited to an SLC mode, an MLC mode, or a TLC mode. In addition, in this embodiment, the setting or conversion of the storage mode completely follows the received storage mode setting instruction of the target area, so that the setting or conversion operation of the storage mode can be well controlled through the operation of the storage mode setting instruction, the flexibility of the storage mode setting operation is improved, and the actual requirements of users are better met.
With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.
It should be noted that: in the data storage device provided in the above embodiment, when storing data, only the division of the above functional modules is taken as an example, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above described functions. In addition, the data storage device provided by the above embodiment and the data storage method embodiment belong to the same concept, and specific implementation processes thereof are detailed in the method embodiment and are not described herein again.
Yet another exemplary embodiment of the present disclosure shows a structural diagram of a terminal. The terminal can be a mobile phone, a tablet computer, a desktop computer, a notebook computer, etc.
Referring to fig. 8, terminal 800 may include one or more of the following components: processing component 802, memory 804, power component 806, multimedia component 808, audio component 810, input/output (I/O) interface 812, sensor component 814, and communication component 816.
The processing component 802 generally controls overall operation of the terminal 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing elements 802 may include one or more processors 820 to execute instructions to perform all or a portion of the steps of the methods described above. Further, the processing component 802 can include one or more modules that facilitate interaction between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.
The memory 804 is configured to store various types of data to support operation at the terminal 800. Examples of such data include instructions for any application or method operating on terminal 800, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 804 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
The multimedia component 808 includes a screen providing an output interface between the terminal 800 and the user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the terminal 800 is in an operation mode, such as a photographing mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.
The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a Microphone (MIC) configured to receive external audio signals when the audio output device 800 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may further be stored in the memory 804 or transmitted via the communication component 816.
The I/O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.
In an exemplary embodiment, the terminal 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described methods.
In an exemplary embodiment, a computer-readable storage medium, such as the memory 804 including instructions executable by the processor 820 of the terminal 800 to perform the above-described method, is also provided. For example, the computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
Yet another embodiment of the present disclosure provides a computer-readable storage medium, in which instructions, when executed by a processor of a terminal, enable the terminal to perform:
receiving a storage mode setting instruction of a target storage area, wherein the storage mode setting instruction carries a target storage mode, and the target storage mode is a single-layer cell SLC mode, a multi-layer cell MLC mode or a three-layer cell TLC mode;
in the Nand chip, setting the storage mode of a target storage area as a target storage mode;
and performing data storage operation in the target storage area through the target storage mode.
Optionally, the original storage mode of the target storage area is an MLC mode or a TLC mode, and the target storage mode is an SLC mode, and the method further includes:
acquiring the data volume of the stored data of the target storage area, taking the data volume as a first data volume, acquiring the maximum data volume which can be stored in the whole target storage area in a target storage mode, and taking the maximum data volume as a second data volume;
setting the storage mode of the target storage area to the target storage mode is performed if the second data amount is greater than or equal to the first data amount.
Optionally, the method further comprises:
and when detecting that data read-write abnormality occurs in the storage area of the MLC mode or the TLC mode in the Nand chip, switching the storage mode of the storage area of the MLC mode or the TLC mode to the SLC mode.
Optionally, the initial storage mode of the Nand chip is SLC mode.
Optionally, the storage mode setting instruction further includes a start address and an end address carrying the target storage area;
in the Nand chip, setting the storage mode of the target storage area as the target storage mode comprises the following steps:
in the Nand chip, the memory mode of the memory region between the start address and the end address is set as the target memory mode.
Optionally, the storage mode setting instruction further carries an identifier of a logical storage unit included in the target storage area;
in the Nand chip, setting the storage mode of the target storage area as the target storage mode comprises the following steps:
and in the Nand chip, setting the storage mode of the logic storage unit corresponding to the identification as a target storage mode.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. A method of data storage, the method comprising:
receiving a storage mode setting instruction of a target storage area, wherein the storage mode setting instruction carries a target storage mode, and the target storage mode is a single-layer cell SLC mode, a multi-layer cell MLC mode or a three-layer cell TLC mode; the storage mode setting instruction is generated after the setting in the target storage area setting window and the target storage mode setting window is completed by a user, or is automatically generated under the condition that the residual storage space of the target storage area is detected to be insufficient;
in a Nand chip, setting a storage mode of the target storage area to the target storage mode, where the storage mode setting instruction further carries a start address and an end address of the target storage area, and then in the Nand chip, setting the storage mode of the target storage area to the target storage mode includes: in a Nand chip, setting the storage mode of a storage area between the starting address and the ending address as a target storage mode; or, if the storage mode setting instruction further carries an identifier of a logical storage unit included in a target storage area, the setting, in the Nand chip, the storage mode of the target storage area to the target storage mode includes: in the Nand chip, setting the storage mode of the logic storage unit corresponding to the identifier as a target storage mode;
and performing data storage operation in the target storage area through the target storage mode.
2. The method of claim 1, wherein the original storage mode of the target storage area is MLC mode or TLC mode, and wherein the target storage mode is SLC mode, the method further comprising:
acquiring the data volume of the stored data of the target storage area, taking the data volume as a first data volume, acquiring the maximum data volume which can be stored in the whole target storage area in the target storage mode, and taking the maximum data volume as a second data volume;
and if the second data amount is larger than or equal to the first data amount, setting the storage mode of the target storage area to the target storage mode is executed.
3. The method according to any one of claims 1-2, further comprising:
and when detecting that data read-write abnormality occurs in the storage area of the MLC mode or the TLC mode in the Nand chip, switching the storage mode of the storage area of the MLC mode or the TLC mode to be the SLC mode.
4. The method of any of claims 1-2, wherein the initial storage mode of the Nand chip is SLC mode.
5. A data storage device, characterized in that the device comprises:
the device comprises a receiving module, a storage mode setting module and a processing module, wherein the receiving module is used for receiving a storage mode setting instruction of a target storage area, and the storage mode setting instruction carries a target storage mode, and the target storage mode is a single-layer cell SLC mode, a multi-layer cell MLC mode or a three-layer cell TLC mode; the storage mode setting instruction is generated after the setting in the target storage area setting window and the target storage mode setting window is completed by a user, or is automatically generated under the condition that the residual storage space of the target storage area is detected to be insufficient;
a setting module, configured to set, in a Nand chip, a storage mode of the target storage area to the target storage mode, where the storage mode setting instruction further carries a start address and an end address of the target storage area, and then, in the Nand chip, the setting module sets the storage mode of the target storage area to the target storage mode, where the setting module includes: in a Nand chip, setting the storage mode of a storage area between the starting address and the ending address as a target storage mode; or, if the storage mode setting instruction further carries an identifier of a logical storage unit included in a target storage area, the setting, in the Nand chip, the storage mode of the target storage area to the target storage mode includes: in the Nand chip, setting the storage mode of the logic storage unit corresponding to the identifier as a target storage mode;
and the first storage module is used for carrying out data storage operation in the target storage area through the target storage mode.
6. The apparatus of claim 5, wherein the original storage mode of the target storage region is MLC mode or TLC mode, and wherein the target storage mode is SLC mode, the apparatus further comprising:
the first acquisition module is used for acquiring the data volume of the stored data of the target storage area, and taking the data volume as a first data volume;
the second acquisition module is used for acquiring the maximum data volume which can be stored in the whole target storage area in the target storage mode and taking the maximum data volume as a second data volume;
and the second storage module is used for setting the storage mode of the target storage area to the target storage mode if the second data volume is larger than or equal to the first data volume.
7. The apparatus of any of claims 5-6, further comprising:
and the switching module is used for switching the storage mode of the storage area in the MLC mode or the TLC mode into the SLC mode when detecting that data read-write abnormality occurs in the storage area in the MLC mode or the TLC mode in the Nand chip.
8. The apparatus of any of claims 5-6, wherein the initial storage mode of the Nand chip is SLC mode.
9. A terminal, characterized in that it comprises a processor and a memory in which at least one instruction, at least one program, set of codes or set of instructions is stored, which is loaded and executed by the processor to implement the data storage method according to any one of claims 1 to 4.
10. A computer readable storage medium having stored therein at least one instruction, at least one program, set of codes, or set of instructions, which is loaded and executed by a processor to implement the data storage method of any one of claims 1 to 4.
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| CN108572924B (en) * | 2018-04-20 | 2021-10-08 | 华中科技大学 | Request processing method of 3D MLC flash memory device |
| CN110910936A (en) * | 2018-09-17 | 2020-03-24 | 北京兆易创新科技股份有限公司 | Mode switching method and device, storage equipment and storage medium |
| CN109491925A (en) * | 2018-09-20 | 2019-03-19 | 中山市江波龙电子有限公司 | Store equipment and its method for writing data, storage device |
| CN109491592B (en) * | 2018-09-20 | 2022-11-15 | 中山市江波龙电子有限公司 | Storage device, data writing method thereof and storage device |
| CN111240578B (en) * | 2018-11-28 | 2023-10-10 | 深圳市江波龙电子股份有限公司 | Multi-bit storage device and electronic equipment |
| CN110413224A (en) * | 2019-06-26 | 2019-11-05 | 深圳佰维存储科技股份有限公司 | Data storage method and device and memory |
| CN112346664B (en) * | 2020-11-30 | 2023-06-09 | 湖南国科微电子股份有限公司 | Data storage method, device, equipment and medium |
| CN112799594A (en) * | 2021-02-02 | 2021-05-14 | 深圳市德明利技术股份有限公司 | Method and device for improving reliability of memory and computer equipment |
| CN117369735B (en) * | 2023-12-08 | 2024-05-10 | 荣耀终端有限公司 | Data storage method, electronic device and storage medium |
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| CN103116550A (en) * | 2013-01-11 | 2013-05-22 | 深圳市硅格半导体有限公司 | Method and device for switching physical block work mode in flash memory |
| CN106170773A (en) * | 2014-01-09 | 2016-11-30 | 桑迪士克科技有限责任公司 | On naked core, the selectivity of buffer-type nonvolatile memory returns and copies |
| US9319073B2 (en) * | 2014-02-11 | 2016-04-19 | Seagate Technology Llc | Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding |
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| CN105551522A (en) * | 2016-01-14 | 2016-05-04 | 深圳市硅格半导体股份有限公司 | Management method and management apparatus of flash memory storage device |
| CN106843762B (en) * | 2017-01-17 | 2019-11-12 | 深圳忆联信息系统有限公司 | The method and solid state hard disk of managing storage area |
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