CN107275334A - Display device - Google Patents
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- CN107275334A CN107275334A CN201610878503.8A CN201610878503A CN107275334A CN 107275334 A CN107275334 A CN 107275334A CN 201610878503 A CN201610878503 A CN 201610878503A CN 107275334 A CN107275334 A CN 107275334A
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- insulating barrier
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- 230000004888 barrier function Effects 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 239000013078 crystal Substances 0.000 claims abstract description 27
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 18
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 280
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 51
- 229920005591 polysilicon Polymers 0.000 claims description 51
- 239000010408 film Substances 0.000 claims description 50
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 239000010409 thin film Substances 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 2
- 230000003139 buffering effect Effects 0.000 claims 1
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 239000011229 interlayer Substances 0.000 claims 1
- 101100489584 Solanum lycopersicum TFT1 gene Proteins 0.000 description 15
- 238000000034 method Methods 0.000 description 13
- 101100214488 Solanum lycopersicum TFT2 gene Proteins 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
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- 239000007769 metal material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- RZVXOCDCIIFGGH-UHFFFAOYSA-N chromium gold Chemical compound [Cr].[Au] RZVXOCDCIIFGGH-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
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- 150000001875 compounds Chemical class 0.000 description 1
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- 238000013461 design Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The present invention on a kind of display device, including：One substrate；One first film transistor unit, be arranged on the substrate and including：One first active layer, wherein first active layer include a silicon layer；First active layer includes a channel region, source region and a drain region, and the wherein channel region is located between the source area and the drain region, and the silicon layer is less than the silicon layer in the thickness of the source area or the drain region in the thickness of the channel region；One second film crystal pipe unit, be arranged on the substrate and including：One second active layer, second active layer includes a metal oxide layer；One first insulating barrier, on first active layer and second active layer；And a display medium, on the substrate.
Description
Technical field
The main object of the present invention is to provide a kind of display device, espespecially a kind of to include low-temperature polysilicon film simultaneously
The display device of transistor unit and metal oxide thin-film transistor unit.
Background technology
As display technology constantly improves, all display panels are sent out towards the trend such as small volume, thickness of thin, lightweight
Exhibition, therefore the display equipment of main flow develops into thin display, such as liquid crystal by conventional cathode-ray tube on the market at present
Show panel, organic LED display panel or inorganic light-emitting diode display panel etc..Wherein, thin display can be applied
Field it is quite a lot of, the mobile phone that is used such as in daily life, notebook computer, video camera, camera, music player, shifting
The display panels such as dynamic guider, TV, it is most of to use those display panels.
Although liquid crystal display or organic light-emitting diode (OLED) display apparatus are display device common on the market, especially
The technology for being liquid crystal display is even more quite ripe, but as display device is continued to develop and consumer shows to display device
Show that quality requirement is improved increasingly, Ge Jia manufacturers strongly develop the display device with more high display quality invariably.
Thin-film transistor structure on viewing area, can be the polysilicon membrane crystal with high carrier mobility characteristic
Pipe, or the metal oxide thin-film transistor with low drain electrical characteristics, current display can not still combine two kinds of crystalline substances
Body pipe, it is, because both technique can influence each other, to cause the overall process complications of display device (for example：Need more times
Chemical vapor deposition method).In view of this, the thin film transistor (TFT) group for viewing area and gate driving circuit region is still needed at present
Part structure is improved, under with good thin-film transistor component characteristic, to simplify both technique and structure.In addition it is current
The low-temperature polysilicon film transistor used has the shortcomings that leakage current, therefore still must be to the knot of low-temperature polysilicon film transistor
Structure makes improvement, to improve the situation of leakage current so that the efficiency of obtained low-temperature polysilicon film transistor is improved.
The content of the invention
The main object of the present invention is to provide a kind of display device, and it includes low-temperature polysilicon film transistor simultaneously
Unit and metal oxide thin-film transistor unit.
In one embodiment of the invention, display device may include：One substrate；One first film transistor unit, is set
In on the substrate and including：One first active layer, wherein first active layer include a silicon layer, and first active layer includes a ditch
Road area, source region and a drain region, the wherein channel region are located between the source area and the drain region, and the silicon layer is in the raceway groove
The thickness in area is less than the silicon layer in the thickness of the source area or the drain region；One second film crystal pipe unit, is arranged at the base
On plate and including：One second active layer, second active layer includes a metal oxide layer；One first insulating barrier, positioned at this
On one active layer and second active layer；And a display medium, on the substrate.
From the foregoing it will be appreciated that the display device of the present invention includes the first film of polysilicon layer including the first active layer simultaneously
Transistor unit and the second film crystal pipe unit that the second active layer is metal oxide layer.Particularly first film transistor
First active layer of unit includes polysilicon layer and the amorphous silicon layer with doped region and undoped region, the undoped region
It is provided between the polysilicon layer and the doped region, is arranged so that the first obtained active layer includes polysilicon layer
First film transistor unit there is tracking-resistant.
Brief description of the drawings
Figure 1A to Fig. 1 E is the Making programme diagrammatic cross-section of component on the substrate of the display device of the embodiment of the present invention 1.
Fig. 1 F are the diagrammatic cross-sections of the display device of the embodiment of the present invention 1.
Fig. 2A to Fig. 2 D is the Making programme diagrammatic cross-section of component on the substrate of the display device of the embodiment of the present invention 2.
Fig. 3 A to Fig. 3 F are the Making programme diagrammatic cross-sections of component on the substrate of the display device of the embodiment of the present invention 3.
Fig. 4 is the diagrammatic cross-section of component on the substrate of the display device of the embodiment of the present invention 4.
Fig. 5 is the diagrammatic cross-section of component on the substrate of the display device of the embodiment of the present invention 5.
Fig. 6 is the diagrammatic cross-section of component on the substrate of the display device of the embodiment of the present invention 6.
Fig. 7 A to Fig. 7 C are the diagrammatic cross-sections of component on the substrate of the display device of other embodiments of the invention 1.
Fig. 8 is the diagrammatic cross-section of component on the substrate of the display device of other embodiments of the invention 2.
【Symbol description】
AA viewing areas B external zones
The display dielectric layer of 2 second substrate 3
The cushion of 11 substrate 12
The polysilicon layer of 14 amorphous silicon layer 141
The undoped region of 16 amorphous silicon layer 161
The first grid insulating barrier of 162 doped region 131
The active layer of 132 second grid insulating barrier 142 second
The second grid of 121 first grid 122
The insulating barrier of 151 first insulating barrier 152 second
The insulating barrier of 153 the 3rd insulating barrier 154 the 4th
171 first source electrodes 172 first drain
173 second source electrodes 174 second drain
The secondary shielding layer of 181 first screen layer 182
15 bottom insulating barrier 171a, 172a, 173a, 174a contact holes
15 ' top insulating barrier 15a, 131a, 153a openings
D drain regions S source areas
AA viewing areas C channel regions
TFT1 first film transistor unit TFT2 the second film crystal pipe units
Embodiment
Illustrate embodiments of the present invention the following is by particular specific embodiment, those skilled in the art can be by this theory
Bright book disclosure of that understands other advantages and effect of the present invention easily.The present invention also can be different specific by other
Embodiment is implemented or applied, and the various details in this specification can not depart from this wound for different viewpoints and application yet
Various modifications and change are carried out under the spirit of work.
Furthermore, ordinal number used in specification and claim such as " the first ", " word the second ", with the power of modifying
Profit require component, itself and unexpectedly contain and represent the request component have it is any before ordinal number, a certain request is not represented yet
Component and the order in the order or manufacture method of another request component, the use of those ordinal numbers are only used for making have certain life
One request component of name is able to that with another request component with identical name clear differentiation can be made.
Embodiment 1
Figure 1A to Fig. 1 E is the Making programme diagrammatic cross-section of component on the substrate of the display device of the present embodiment.First,
As shown in Figure 1A there is provided a substrate 11, here, substrate 11 is made using the baseplate material such as glass, plastics, flexible materials
Into；And a first screen layer 181 and a secondary shielding layer 182, wherein first screen layer 181 and second are set on the substrate 11
The material of screen layer 182 can be any screening optical activity material, such as metal, black matrix".Then in the first screen layer 181 and
One cushion 12 is set in the secondary shielding layer 182, and the material of cushion 12 can be silica or silicon nitride and silica
Laminated construction, the silicon nitride of latter of which is located between silica and substrate, then in setting a pattern on the cushion 12
Change polysilicon layer 141, and the polysilicon layer 141 and the first screen layer 181 are to be correspondingly arranged, in the top of polysilicon layer 141
Setting amorphous silicon layer 16, it includes doped region 162 and undoped region 161, the polysilicon layer 141 and the shape of amorphous silicon layer 16
Into one first active layer, first active layer includes a channel region C, source region S and a drain region D, wherein channel region C
Between source area S and drain region D, channel region C includes undoped region 161 but does not include doped region 162, and
Source area S and the drain region then include doped region 162 and undoped region 161.
As shown in Figure 1B, one second active layer 142 is formed in the first buffer layer 12, second active layer 142 is with being somebody's turn to do
Secondary shielding layer 182 is to be correspondingly arranged, and second active layer 142 is metal oxide in the present embodiment, such as IGZO.As schemed
Shown in 1C, a first grid insulating barrier 131 is formed on first active layer and second active layer 142, the first grid is exhausted
Edge layer 131 is silicon oxide layer.As shown in figure iD, a first grid 121 and one the are formed simultaneously on first grid insulating barrier 131
Two grids 122, the wherein first grid 121 and the second grid 122 be respectively with first active layer and second active layer
142 are correspondingly arranged, and the first grid 121 and the second grid 122 can be used as made by the metal materials such as Cu or Al in addition.
As referring to figure 1E, one first insulating barrier 151, first insulating barrier are formed on the first grid 121 and the second grid 122
151 materials are to use silica in the present embodiment, and one first source electrode 171 and one of formation on first insulating barrier 151
First drain electrode 172, and first source electrode 171 and first drain electrode 172 passes through multiple contact hole 171a, 172a and the source area respectively
The doped region 162 of S and the drain region D amorphous silicon layer 16 is electrically connected with, and is also formed simultaneously on the first insulating barrier 151
One second source electrode 173 and one second drain electrode 174, and second source electrode 173 and second drain electrode 174 pass through multiple contact holes
173a, 174a and second active layer 142 are electrically connected with.
Via previous process, in the display device of the present embodiment, first active layer (including polysilicon layer 141 and non-
Crystal silicon layer 16) it is located at second active layer 142 on the substrate 11, the first grid insulating barrier 131 is located at first active layer
With on second active layer 142, the first grid 121 and the second grid 122 are on the first grid insulating barrier 131, one
First insulating barrier 151 is on the first grid 121 and the second grid 122, and first source electrode 171, first drain electrode
172nd, second source electrode 173 and second drain electrode 174 are provided at 151 on first insulating barrier；Wherein first source electrode 171 and should
First drain electrode 172 by multiple contact hole 171a, 172a with source area S and the drain region D amorphous silicon layer 16 should
Doped region 162 is electrically connected with, and second source electrode 173 and this second drain electrode 174 by multiple contact hole 173a, 174a with this
Second active layer 142 is electrically connected with.In addition, display device also includes a first screen layer 181, a secondary shielding layer 182 and one
Cushion 12, the wherein first screen layer 181, the secondary shielding layer 182 are provided between the substrate 11 and the cushion 12, and this
One active layer is provided on the cushion 12 with second active layer 142, and first active layer and second active layer 142 are
Overlapped respectively with the first screen layer 181 and secondary shielding layer 182.In addition in the present embodiment, the undoped region 161 is also located at
In channel region C, and the undoped region 161 is less than or equal to the undoped region 161 in the source electrode in channel region C thickness
Area S and the drain region D thickness.
In the present embodiment, display device is while including the first film of polysilicon layer 141 including the first active layer
Transistor unit TFT1 and the second film crystal pipe unit TFT2 that the second active layer 142 is metal oxide layer, the metal oxygen
The material of compound can be Zinc oxide-base metal oxide, for example：IGZO ITZO etc., wherein the first film transistor list
First TFT1 is a top grid structure, and it includes a first grid 121, and the first grid 121 is disposed on first active layer.
Particularly, in the present embodiment, the first active layer and the second active layer are to be arranged on same layer, therefore first grid, second
Grid can be formed simultaneously, and the first source electrode, the second source electrode, the first drain electrode and the second drain electrode can also be formed simultaneously, thus be subtracted
Few processing step so that the modular construction on substrate more simplifies, and the present embodiment first makes polysilicon layer and makes metal again in addition
Oxide skin(coating), can avoid the high temperature crystallization technique of polysilicon layer from damaging metal oxide layer, or institute in the present embodiment
The first film transistor unit that obtained first active layer includes polysilicon layer has effects that preferably tracking-resistant.
As shown in fig. 1F, a second substrate 2 can be included simultaneously in the display device of the present embodiment, it is relative with substrate 11 to set
Put；And a display medium 3, it is arranged between substrate 11 and second substrate 2, wherein substrate 11 and substrate 2 use such as glass, modeling
Made by the baseplate materials such as material, flexible materials, film；In addition, display medium 3 can be liquid crystal layer, organic luminous layer, two poles
Die array etc., but not limited to this.
Embodiment 2
Fig. 2A to Fig. 2 D is the Making programme diagrammatic cross-section of component on the substrate of the display device of the present embodiment.First,
As shown in Figure 2 A there is provided a substrate 11, on the substrate 11 side set one patterning first grid 121, and the substrate 11 with
One first grid insulating barrier 131 is set on the first grid 121, and 131 settings one first are active on the first grid insulating barrier
Layer, first active layer is correspondingly arranged with the first grid 121, and first active layer is non-comprising a polysilicon layer 141 and one
Crystal silicon layer 16, the polysilicon layer 141 is located between the substrate 11 and the amorphous silicon layer 16；First active layer include source region S,
An one drain region D and channel region C, channel region C are located between source area S and drain region D；The amorphous silicon layer 16 includes one
The undoped region 161 of doped region 162 and one, the undoped region 161 and the doped region 162 are sequentially stacked on the polysilicon layer 141
And in source area S and drain region D, wherein not including amorphous silicon layer 16 in channel region C.In first grid insulation
The top of layer 131 is provided with one second active layer 142, and second active layer is a metal oxide, such as：IGZO.As shown in Figure 2 B,
It is exhausted that a second grid is formed on first active layer (including polysilicon layer 141 and amorphous silicon layer 16) and the second active layer 142
Edge layer 132, then forms a bottom insulating barrier 15 on the second grid insulating barrier 132, and wherein the bottom insulating barrier 15 is in this implementation
It is silicon nitride layer in example, and an opening 15a is formed with the exposure second grid insulating barrier 132 on the bottom insulating barrier 15, should
The 15a that is open is correspondingly arranged with second active layer 142.As shown in Figure 2 C in forming a second grid on the bottom insulating barrier 15
122, the second grid 122 is provided in the opening 15a on the bottom insulating barrier 15, and the second grid 122 is and this
Second active layer 142 is correspondingly arranged, and wherein the second grid 122 can be used as made by the metal materials such as Cu or Al.Such as Fig. 2 D
It is shown, a top insulating barrier 15 ' is formed on the second grid 122 and bottom insulating barrier 15, the top insulating barrier 15 ' is silicon monoxide
Layer, the bottom insulating barrier 15 and the top insulating barrier 15 ' one first insulating barrier 151 of formation, are then formed on first insulating barrier 151
One first source electrode 171 and one first drain electrode 172, and first source electrode 171 and first drain electrode 172 passes through multiple contact holes respectively
The doped region 162 of 171a, 172a and source area S and the drain region D amorphous silicon layer 16 is electrically connected with, and exhausted first
Also the second source electrode 173 and one second drain electrode 174, and second source electrode 173 and second drain electrode 174 are formed in edge layer 151 simultaneously
It is electrically connected with by multiple contact hole 173a, 174a and second active layer 142.
Via previous process, the display device obtained by the present embodiment is provided at the substrate 11 comprising a first grid 121
On, the first grid insulating barrier 131 is provided on the first grid 121, first active layer (including the polysilicon layer 141 and
The amorphous silicon layer 16) and second active layer 142 be provided on the first grid insulating barrier 131, the second grid insulating barrier 132
It is provided on first active layer and second active layer 142, the second grid 122 is provided at the second grid insulating barrier 132
On, one first insulating barrier 151 is provided on the second grid insulating barrier 132, and first source electrode 171, this first drain electrode 172,
Second source electrode 173 and second drain electrode 174 are on first insulating barrier 151；Wherein first source electrode 171 and this first leakage
Pole 172 is by multiple contact hole 171a, 172a with the doped region with source area S and the drain region D amorphous silicon layer 16
162 are electrically connected with, and second source electrode 173 and second drain electrode 174 by multiple contact hole 173a, 174a second to have with this
Active layer 142 is electrically connected with.Specifically in the present embodiment, first insulating barrier 151 is exhausted comprising a bottom insulating barrier 15 and a top
Edge layer 15 ', the bottom insulating barrier 15 is located between the second grid insulating barrier 132 and the top insulating barrier 15 ', and the second grid 122
The opening 15a of bottom insulating barrier 15 is provided at, and is contacted with second grid insulating barrier 132, opening 15a is the second active layer of correspondence
142, the bottom insulating barrier 15 is a silicon nitride layer in the present embodiment in addition and the top insulating barrier is one silica layer, bottom insulation
15 silicon nitride layer of layer relatively push up the silica floor height of insulating barrier 15 ' because of hydrogen content, remove the bottom insulating barrier above correspondence metal oxide
15 can prevent the hydrogen in bottom insulating barrier 15 to be diffused into metal oxide layer, and then it is thin to avoid the rise of metal conductive oxide rate from causing
The shortcoming that film transistor efficiency declines.
Embodiment 3
Fig. 3 A to Fig. 3 F are the Making programme diagrammatic cross-sections of component on the substrate of the display device of the present embodiment.First,
As shown in Figure 3A there is provided a substrate 11, here, substrate 11 is made using the baseplate material such as glass, plastics, flexible materials
Into；And patterning forms a first screen layer 181 on substrate, then forms a cushion in the first screen layer 181
12, the laminated construction of silica or silicon nitride and silica can be used in the material of cushion 12, and the silicon nitride of latter of which is set
Between silica and substrate, a patterned polysilicon layer 141, the polysilicon layer are then set in the first buffer layer 12
141 be to be correspondingly arranged with the first screen layer 181, then sequentially forms an amorphous silicon layer 16 in the top of polysilicon layer 141, its
Include doped region 162 and undoped region 161, the wherein doping is for one n-type amorphous silicon layer of formation.The polysilicon layer 141
And the amorphous silicon layer 161 forms one first active layer, first active layer includes source region S, a drain region D and a raceway groove
Area C, source area S and drain region D include amorphous silicon layer 16, and channel region C does not include amorphous silicon layer 16.And at this
A second grid 122 is formed on cushion 12, material used in the second grid 122 is polysilicon in the present embodiment.
First active layer and the top of second grid 122 form a first grid insulating barrier 131, and the first grid insulating barrier 131 is one
Silicon oxide layer.As shown in Figure 3 B, a first grid 121 and one second active layer are set on the first grid insulating barrier 131
142, and the first grid 121 and second active layer 142 are metal oxides in the present embodiment, such as IGZO.Such as Fig. 3 C
It is shown, opening 131a is formed on the first grid insulating barrier 131 with exposed to source area S and drain region D amorphous silicon layer 16
Doped region 162.As shown in Figure 3 D, one first source electrode 171 and one first drain electrode are formed on the first grid insulating barrier 131
172, and first source electrode 171 and first drain electrode 172 respectively by opening 131a and source area S and drain region D should
The doped region 162 of amorphous silicon layer 16 is electrically connected with, and also forms one second source electrode simultaneously on the first grid insulating barrier 131
173 and one second drain electrode 174, and second source electrode 173 and second drain electrode 174 be electrically connected with second active layer 142.
As shown in FIGURE 3 E, in first source electrode 171, first drain electrode 172, first grid 121, the leakage of the second source electrode 173, second
One the 3rd insulating barrier 153 is formed on the active layer 142 of pole 174 and second, and one is formed on the 3rd insulating barrier 153 and is open
153a is with the exposure first grid 121, and wherein the 3rd insulating barrier 153 is one silica layer in the present embodiment.Such as Fig. 3 F institutes
Show, one the 4th insulating barrier 154, the 4th are formed in the opening 153a of the top of the 3rd insulating barrier 153 and the 3rd insulating barrier
Insulating barrier 154 and the first grid 121 joint at the opening 153a of the 3rd insulating barrier, the 4th is exhausted in the present embodiment
Edge layer 154 is a silicon nitride layer.
Via previous process, the display device obtained by the present embodiment includes one first active layer (including polysilicon layer 141
And amorphous silicon layer 16) and the second grid 122 be provided on the substrate 11, the first grid insulating barrier 131 first has located at this
In active layer and the second grid 122, the first grid 121 is provided at the first grid insulating barrier 131 with second active layer 142
On, first source electrode 171 is provided on the first grid insulating barrier 131 and exhausted by the first grid with first drain electrode 172
The opening 131a formed in edge layer 131 as contact hole with source area S and the drain region D amorphous silicon layer 141
The doped region 162 is electrically connected with, and second source electrode 173 and this second drain electrode 174 be provided on second active layer 142 and with
Second active layer 142 is electrically connected with.Wherein the first grid 121 includes a metal oxide layer, such as：IGZO, and this second
Grid 122 includes a silicon layer, such as polysilicon layer.In addition one the 3rd insulating barrier 153 is provided at the first grid insulating barrier 131,
One grid 121, first source electrode 171, first drain electrode 172, second active layer 142, second source electrode 173 and second leakage
On pole 174, the 3rd insulating barrier 153 includes an opening 153a to appear the first grid 121, and one the 4th insulating barrier 154 is
On the 3rd insulating barrier 153 and in opening 153a, wherein the material of the 4th insulating barrier 154 is silicon nitride.In addition, also
Including a first screen layer 181 and a cushion 12, wherein the first screen layer 181 is located at the substrate 11 and the cushion 12
Between, first active layer is provided on the cushion 12 with the second grid 122, and first active layer is and first shielding
Layer 181 overlaps.
In the present embodiment, display device is while brilliant including the first film that the first active layer includes polysilicon layer 141
Body pipe unit TFT1 and the second film crystal pipe unit TFT2 that the second active layer 142 is metal oxide layer.And first is thin
The first grid 121 that film transistor unit TFT1 is included is provided in above the first active layer, is setting for a top grid structure
Meter, and the second grid 122 that the second film crystal pipe unit TFT2 is included is provided in the lower section of the second active layer 142, is one
The setting of bottom-gate knot.Particularly, in the present embodiment, polysilicon layer 142 and second grid 122 can be formed simultaneously, and can be same
When form the active layer 142 of first grid 121 and second, processing step can be reduced so that modular construction on substrate can also plus letter
Change.In addition in the present embodiment, the 4th insulating barrier 154 is a silicon nitride layer, and the 4th insulating barrier 154 is via the 3rd insulation
Opening 153a on layer 153 is contacted with first grid 121, and the material of the first grid 121 used in the present embodiment is gold
Belong to oxide, such as IGZO, due to containing hydrogen in silicon nitride layer, when the silicon nitride layer is contacted with first grid, in silicon nitride layer
Hydrogen can be diffused in IGZO so that IGZO activity lifting, and then causes the rise of its electrical conductivity, so that obtained first
Film crystal pipe unit TFT1 effect is more preferably.
Embodiment 4
The technique of the present embodiment is similar with previous embodiment, therefore is not repeating, as shown in figure 4, obtained by the present embodiment
Display device include a first grid 121 and the second grid 122 and be provided on the substrate 11, the first grid insulating barrier
131 are provided on the first grid 121 and the substrate 11, first active layer (including polysilicon layer 141 and amorphous silicon layer 16)
It is provided on the first grid insulating barrier 131, the second grid insulating barrier 132 is provided at first active layer and the second grid
On 122, first source electrode 171 is provided on the second grid insulating barrier 132 and by multiple contact holes with first drain electrode 172
171a, 172a are electrically connected with the doped region 162 with source area S and the drain region D amorphous silicon layer 16, and this second has
Active layer 142 is provided on the second grid insulating barrier 132, and second source electrode 173 and this second drain electrode 174 be provided at this second
It is electrically connected with active layer 142 and with second active layer 142, wherein the second grid 122 is provided at first grid insulation
Between layer 131 and the substrate 11.In the present embodiment, the first grid 121 that first film transistor unit TFT1 is included is to set
Put below the first active layer, and the second grid 122 that the second film crystal pipe unit TFT2 is included is provided in second and had
The lower section of active layer 142, is the design of bottom gate configuration.In addition the second grid that the second film crystal pipe unit TFT2 is included
122 are simultaneously formed with the first film transistor unit TFT1 first grids 121 included, therefore can simplify technique and component
Structure, material used in the first grid 121 and the second grid 122 is molybdenum, chromium gold in the present embodiment in addition
Category, titanium or other refractory metals.
Embodiment 5
The technique of the present embodiment is similar with previous embodiment, therefore is not repeating, as shown in figure 5, the display of the present embodiment
Equipment, including：One first grid 121 and the second grid 122 are provided on the substrate 11, and the first grid insulating barrier 131 is
On the first grid 121, the second grid 122 and the substrate 11, first active layer (including polysilicon layer 141 and non-
Crystal silicon layer 16) and second active layer 142 on the first grid insulating barrier 131, second source electrode 173 and second drain electrode
174 are provided on second active layer 142 and are electrically connected with second active layer 142, and one the 3rd insulating barrier 153 is provided at this
In first grid insulating barrier 131, second active layer 142, second source electrode 173 and second drain electrode 174, first source electrode
171 and this first drain electrode 172 be provided on the 3rd insulating barrier 153 and by multiple contact hole 171a, 172a with the source electrode
The doped region 162 of area S and the drain region D amorphous silicon layer 16 is electrically connected with.
Embodiment 6
The technique of the present embodiment is similar with previous embodiment, therefore is not repeating, the display device of the present embodiment, including：
One first grid 121 and the second grid 122 are provided on the substrate 11, the first grid insulating barrier 131 be provided at this first
On grid 121, the second grid 122 and the substrate 11, first active layer (including polysilicon layer 141 and amorphous silicon layer 16) and
Second active layer 142 is provided on the first grid insulating barrier 131, and second source electrode 173 and second drain electrode 174 are provided at
It is electrically connected with second active layer 142 and with second active layer 142, first source electrode 171 and first drain electrode 172 are to set
It is connected on the doped region 162 of source area S and the drain region D amorphous silicon layer 16 and with the doped region 162, and one
Three insulating barriers 153 are provided on first active layer and second active layer 142.
Other embodiment 1
1 display device into embodiment 6 is to include the first active layer to include many as set forth above
The first film transistor unit TFT1 of crystal silicon layer and amorphous silicon layer.In the other embodiment 1 of the present invention, the first film crystal
Pipe unit TFT1 the first active layer structure can be varied from, and be not limited to shown in the schema of previous embodiment.For example, should
The structure of first film transistor unit can be as shown in Fig. 7 A to Fig. 7 C, and wherein first active layer includes a polysilicon layer
141 and an amorphous silicon layer 16, the amorphous silicon layer 16 includes a doped region 162 and a undoped region 161, and wherein this first has
Active layer includes source region S, a drain region D and a channel region C, and channel region C is located between source area S and drain region D,
The amorphous silicon layer 16 is formed in source area S and drain region D, and channel region C do not include have mixing for amorphous silicon layer 16
Miscellaneous area 162, but optionally include the undoped region 161 of amorphous silicon layer 16.In Fig. 7 A, in channel region C undoped
The thickness in area 161 is less than or equal to the thickness in source S and drain region D undoped region 161；In Fig. 7 B, in channel region C
The thickness of undoped region 161 be less than thickness in source S and drain region D undoped region 161；And in Fig. 7 C, in ditch
Road area C is simultaneously not provided with amorphous silicon layer 16.Specifically, the undoped region 161 is less than or equal in the thickness of the channel region
The undoped region 161 is in the thickness of the source area and the drain region.In the present invention, the aspect shown in Fig. 7 A to Fig. 7 C can be applied mechanically
In embodiments of the invention 1 into embodiment 6.
Other embodiment 2
1 display device into embodiment 6 is to include the first active layer to include many as set forth above
The first film transistor unit TFT1 of crystal silicon layer 141 and amorphous silicon layer 16.In the other embodiment 2 of the present invention, first is thin
Film transistor unit TFT1 the first active layer structure can be varied from, and be not limited to shown in previous embodiment schema.Citing and
Speech, first film transistor unit TFT1 structure can be as shown in figure 8, wherein first active layer includes a polysilicon layer
141 and an amorphous silicon layer 16, the amorphous silicon layer 16 includes a doped region 162 and a undoped region 161, and wherein this first has
Active layer includes source region S, a drain region D and a channel region C, and channel region C is located between source area S and drain region D,
The polysilicon layer 141 is different in the projected area on substrate 11 from drain region D in source area S, the polysilicon as shown in Figure 8
Layer 141 is greater than area of the polysilicon layer 141 in drain region D in source area S area, and polysilicon layer 141 exists in addition
Source area S area can also be less than area (not shown) of the polysilicon layer 141 in drain region D.More specifically,
The polysilicon layer 141 with the polysilicon layer 141 is to differ in drain region D area in source area S area, and its face
Product ratio can be any proportion, be not limited in as shown in Figure 8.
Display device in the present invention obtained by previous embodiment also includes a viewing area and an external zones, the external zones
It is disposed adjacent outside the viewing area and with the viewing area, wherein first film transistor unit TFT1 is located at the external zones
In, and the second film crystal pipe unit TFT2 is located in the viewing area.
The viewing area of display device in the present invention obtained by previous embodiment also include multiple pixels, wherein this first
Film crystal pipe unit TFT1 and the second film crystal pipe unit TFT2 is provided in same pixel, or in adjacent pixel.
In the present invention, the display device obtained by previous embodiment can merge with contact panel and use, and be touched as one
Control display device.Meanwhile, display device or touch control display device obtained by present invention can be applied to this technology
Known to field on the electronic installation of any required display screen, such as display, mobile phone, notebook computer, video camera, photograph
Machine, music player, action navigation device, TV etc. need to show on the electronic installation of image.
Above-described embodiment explanation merely for convenience and illustrate, the interest field advocated of the present invention is from should be to apply
It is defined described in the scope of the claims, rather than is only limitted to above-described embodiment.
Claims (16)
1. a kind of display device, it is characterised in that including：
One substrate；
One first film transistor unit, being arranged on the substrate includes：
One first active layer, wherein first active layer include a silicon layer；First active layer includes a channel region, source region
With a drain region, the wherein channel region is located between the source area and the drain region, and the silicon layer is less than in the thickness of the channel region
The silicon layer is in the thickness of the source area or the drain region；
One second film crystal pipe unit, be arranged on the substrate and including：
One second active layer, second active layer includes a metal oxide layer；
One first insulating barrier, on first active layer and second active layer；And
One display medium, on the substrate.
2. display device as claimed in claim 1, it is characterised in that wherein the silicon layer includes a polysilicon layer and a non-crystalline silicon
Layer, and the polysilicon layer is located between the substrate and the amorphous silicon layer.
3. display device as claimed in claim 2, it is characterised in that wherein the amorphous silicon layer includes a doped region and one non-mixed
Miscellaneous area, the undoped region and the doped region are sequentially stacked on the polysilicon layer and in the source area and the drain region.
4. display device as claimed in claim 3, it is characterised in that wherein the undoped region is also located in the channel region, and
The undoped region is less than or equal to the undoped region in the thickness of the source area and the drain region in the thickness of the channel region.
5. display device as claimed in claim 2, it is characterised in that the first film transistor unit also comprising a source electrode and
One drain electrode, the wherein source area and the source contact, the drain region and the drain contact, wherein the polysilicon layer is in the source area
It is different in the projected area on substrate in the drain region from the polysilicon layer.
6. display device as claimed in claim 1, it is characterised in that including a viewing area and an external zones, the peripheral position
It is disposed adjacent in outside the viewing area and with the viewing area, wherein the first film transistor unit is located in the external zones, and is somebody's turn to do
Second film crystal pipe unit is located in the viewing area.
7. display device as claimed in claim 1, it is characterised in that including a viewing area and an external zones, the peripheral position
It is disposed adjacent in outside the viewing area and with the viewing area, wherein the first film electricity crystalline substance is located at the second film crystal pipe unit
In the viewing area.
8. display device as claimed in claim 7, it is characterised in that wherein the viewing area includes multiple pixels, this is first thin
Film transistor unit is located in same pixel with the second film crystal pipe unit.
9. display device as claimed in claim 7, it is characterised in that wherein the viewing area includes multiple pixels, this is first thin
Film transistor unit is located in adjacent pixel with the second film crystal pipe unit.
10. display device as claimed in claim 1, it is characterised in that the first film transistor unit also includes one first
Grid is corresponding with first active layer, and wherein the first grid includes a metal oxide.
11. display device as claimed in claim 1, it is characterised in that the material of first insulating barrier is silicon nitride and should
First insulating barrier has opening second active layer of correspondence.
12. display device as claimed in claim 1, it is characterised in that also including a first screen layer, a secondary shielding layer and
One cushion, the wherein cushion are arranged between first active layer and substrate, and the first screen layer, the secondary shielding layer are set
In the substrate and the buffering interlayer, and first active layer and second active layer respectively with the first screen layer and secondary shielding
Layer overlaps.
13. display device as claimed in claim 1, it is characterised in that the second film crystal pipe unit also includes one second
Grid is corresponding with second active layer, and wherein the second grid includes a silicon layer.
14. display device as claimed in claim 1, it is characterised in that the first film transistor unit also includes one first
Grid, the first grid is arranged on first active layer.
15. display device as claimed in claim 13, it is characterised in that be also arranged at this including one second insulating barrier first exhausted
In edge layer, the material of first insulating barrier is silica, and second insulating barrier is silicon nitride, wherein, first insulating barrier has
One opening to should first grid, and the first grid contacts with the second insulating barrier.
16. display device as claimed in claim 1, it is characterised in that the second film crystal pipe unit also includes one second
Grid, the second grid is arranged under second active layer.
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| US15/452,754 US20170294459A1 (en) | 2016-04-08 | 2017-03-08 | Display device |
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| US201662319965P | 2016-04-08 | 2016-04-08 | |
| US62/319,965 | 2016-04-08 |
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| CN202011093173.4A Pending CN112133710A (en) | 2016-04-08 | 2016-06-15 | Display device |
| CN201610878503.8A Pending CN107275334A (en) | 2016-04-08 | 2016-10-09 | Display device |
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| CN109920855A (en) * | 2019-02-13 | 2019-06-21 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor and its manufacturing method |
| WO2020114485A1 (en) * | 2018-12-07 | 2020-06-11 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor, and display device |
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| CN108493198B (en) * | 2018-04-11 | 2020-11-24 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and organic light emitting diode display device |
| TWI699892B (en) * | 2018-09-21 | 2020-07-21 | 友達光電股份有限公司 | Electronic device and manufacturing method thereof |
| CN110534531A (en) * | 2019-08-30 | 2019-12-03 | 京东方科技集团股份有限公司 | A kind of driving backboard and preparation method thereof, display panel |
| CN110620120B (en) * | 2019-09-25 | 2022-07-29 | 福州京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN111668236A (en) | 2020-06-08 | 2020-09-15 | Tcl华星光电技术有限公司 | Array substrate and preparation method thereof |
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Also Published As
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| CN107302030B (en) | 2020-11-03 |
| CN107302030A (en) | 2017-10-27 |
| TWI606283B (en) | 2017-11-21 |
| CN112133710A (en) | 2020-12-25 |
| TW201809818A (en) | 2018-03-16 |
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