CN107256850B - Adapter plate embedded with metal micro-channel and preparation method thereof - Google Patents
Adapter plate embedded with metal micro-channel and preparation method thereof Download PDFInfo
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- CN107256850B CN107256850B CN201710611140.6A CN201710611140A CN107256850B CN 107256850 B CN107256850 B CN 107256850B CN 201710611140 A CN201710611140 A CN 201710611140A CN 107256850 B CN107256850 B CN 107256850B
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- 239000002184 metal Substances 0.000 title claims abstract description 262
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 190
- 238000000034 method Methods 0.000 claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 claims description 32
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- 230000004888 barrier function Effects 0.000 claims description 22
- 239000011521 glass Substances 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 238000009713 electroplating Methods 0.000 claims description 13
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052721 tungsten Inorganic materials 0.000 claims description 11
- 239000010937 tungsten Substances 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 238000005240 physical vapour deposition Methods 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 9
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- 239000004743 Polypropylene Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- 229920000052 poly(p-xylylene) Polymers 0.000 claims description 5
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- -1 polypropylene Polymers 0.000 claims description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
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Abstract
The invention discloses an adapter plate with embedded metal microchannels and a preparation method thereof, wherein the adapter plate comprises a first substrate and a second substrate which are mutually bonded, and the metal microchannels are arranged in the first substrate; the metal microchannel consists of a through hole on the first substrate and a metal fin on the second substrate; in the process of integrating the high-density chip, a first substrate and a second substrate of the adapter plate are firstly bonded to form an adapter plate structure, metal fins are arranged in through holes of the first substrate to form a metal micro-channel structure, then the high-density chip is integrated on the surface of the first substrate, signal redistribution of the high-density chip is realized through a metal rewiring layer and metal interconnection through holes on the surface of the first substrate, and heat is conducted through the metal micro-channel. The adapter plate has the advantages of good heat conduction effect, small packaging size, simple process and controllable cost.
Description
Technical Field
The invention relates to an adapter plate embedded with a metal microchannel and a preparation method thereof.
Background
The TSV/TGV interposer technology (TSV/Through-Glass-Via, TGV) is an important development direction derived from the TSV interconnection technology, can provide line width/pitch and thermal expansion coefficient matched with a three-dimensional packaged integrated circuit IC, has the characteristics of small size, high density and high integration, can effectively reduce the package size, reduce transmission delay, reduce noise, improve electrical performance, reduce power consumption and the like, and has become the most competitive interposer technology for chip-level three-dimensional integration of integrated circuits IC, MEMS, micro-nano sensors and the like.
When a high-density chip and a high-power chip are integrated in a three-dimensional system-in-package, the performance of the chip is reduced, the service life is shortened, and even the function is failed due to the heat dissipation problem of the chip body.
In consideration of the heat dissipation problem of the adapter plate when a high-density chip is integrated, the published patent application (publication number: CN 104900611A) relates to a method for embedding an ultrathin graphene heat sink into a package body in a three-dimensional packaging process based on a flexible substrate, so that a heat dissipation channel directly leading to the outside is added in the package body to solve the heat dissipation problem, but the method can solve the heat dissipation problem, but the bonding strength of graphene and the chip is poor, and the heat dissipation capability is reduced; in the published patent application (publication No. CN 104716112A) heat is progressively dissipated using a multi-stage heat spreader thermally coupled to a first die package and a die package heat spreader. The die package heat spreader is thermally coupled to the second die package and provides a thermal path for conducting heat from the second die package to the package heat spreader. The mode has complex heat dissipation structure and high process requirement.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides the adapter plate embedded with the metal microchannel and the preparation method thereof, and solves the problems in the background technology.
The technical scheme adopted by the invention for solving the technical problems is as follows: an adapter plate with embedded metal microchannels is used for integrating a high-density chip and comprises a first substrate and a second substrate which are mutually bonded, wherein the metal microchannels are arranged in the first substrate;
the first substrate is provided with a plurality of through holes, an insulating layer, a metal interconnection layer and a metal rewiring layer; the through holes and the through holes are distributed on the first substrate at intervals; the insulating layer is continuously arranged on the side wall of the through hole, the side wall of the through hole and the upper surface and the lower surface of the first substrate; the metal interconnection layer is continuously arranged on the surfaces of the insulating layers of the side walls of the through holes and the side walls of the through holes; the metal rewiring layer is arranged on a part, in contact with the high-density chip, of the first substrate upper surface insulating layer and a part, in contact with the second substrate, of the first substrate lower surface insulating layer; the metal rewiring layer is in contact with the metal interconnection layer to form an electric signal path;
the upper surface of the second substrate is provided with a plurality of metal fins, the metal fins are positioned in the through holes, the lower ends of the metal fins are fixedly connected with the second substrate, and the upper ends of the metal fins extend to the plane of the metal rewiring layer on the upper surface of the first substrate;
the metal microchannel comprises a through hole and a metal fin; when the high-density chip is integrated on the adapter plate, the high-density chip is arranged above the first substrate, the electric signal is redistributed through the metal rewiring layer and the metal interconnection layer on the upper surface of the first substrate, and heat generated by the high-density chip is conducted through the metal microchannel.
In a preferred embodiment of the present invention, the first substrate and the second substrate are bonded to each other, and the bonding method includes gold bonding, silicon glass anodic bonding, silicon bonding, and BCB bonding.
In a preferred embodiment of the present invention, the material of the first substrate includes silicon, glass, silicon nitride, gallium arsenide, and metal.
In a preferred embodiment of the present invention, the second substrate material includes silicon, glass, silicon nitride, gallium arsenide; the metal fin is made of copper, aluminum, gold and tungsten and is formed on the surface of the second substrate through a LIGA electroforming process.
In a preferred embodiment of the present invention, the material of the second substrate includes a metal and/or a metal alloy thereof, and the metal is at least one of tungsten, titanium, molybdenum, titanium tungsten, nickel, and germanium; the material of the metal fin is the same as that of the second substrate, and the metal fin is formed on the surface of the second substrate through a metal DRIE etching process.
In a preferred embodiment of the present invention, the height of the metal fin is adapted to the distance between the metal redistribution layers on the upper and lower surfaces of the first substrate.
In a preferred embodiment of the present invention, a barrier layer is further disposed between the metal interconnection layer and the insulating layer, and between the metal redistribution layer and the insulating layer, wherein the barrier layer material includes at least one of Ta, taN, and TiW, and the cross section of the insulating layer, the metal interconnection layer, and the barrier layer disposed on the sidewall of the via hole is annular.
The invention provides a preparation method of an adapter plate embedded with a metal microchannel, which comprises the following steps:
(1) Manufacturing a first substrate and an insulating layer: taking a plate-shaped material as a first substrate, and forming a plurality of through holes and a plurality of through holes on the first substrate through DRIE (direct ion etching), laser, sand blasting or wet etching processes, wherein the hole diameter of each through hole is larger than that of each through hole; forming compact insulating layers on the side walls of the through holes, the side walls of the through holes and the upper and lower surfaces of the first substrate by a vapor deposition method, wherein the insulating layers are made of silicon oxide, silicon nitride, aluminum oxide, BCB (barium-boron), polyimide, glass, polypropylene and parylene; the material of the first substrate comprises silicon, glass, silicon nitride and gallium arsenide;
(2) Manufacturing electric signal path and metal fin
(1) Manufacturing an electric signal path: forming a continuous metal layer on the surface of the insulating layer through PVD (physical vapor deposition) sputtering, etching a pattern on the metal layer on the upper surface and the lower surface of the first substrate by utilizing a graphical electroplating process to form a metal rewiring layer, and enabling the metal rewiring layer to be arranged on a part of the upper surface of the first substrate, which is contacted with the high-density chip, and a part of the lower surface of the first substrate, which is contacted with the second substrate; the continuous metal layers distributed on the side walls of the through holes and the surface of the side wall insulating layer of the through holes are metal interconnection layers and are in contact with the metal rewiring layer to form an electric signal path;
(2) manufacturing a metal fin: taking a semiconductor plate as a second substrate, and forming a plurality of metal fins which are distributed in a parallel array by LIGA electroforming, wherein the length of each metal fin is equal to the distance between metal rewiring layers on the upper surface and the lower surface of the first substrate; the second substrate material comprises silicon, glass, silicon nitride and gallium arsenide; the metal fin is made of copper, aluminum, gold and tungsten;
(3) And bonding the first substrate and the second substrate through a bonding process, wherein the metal fins are arranged in the through holes, and the through holes and the metal fins form metal microchannels, so that the adapter plate embedded with the metal microchannels is formed.
The invention also provides a preparation method of the adapter plate with the embedded metal microchannel, which comprises the following steps:
(1) Manufacturing a first substrate and an insulating layer: taking a plate-shaped material as a first substrate, forming through holes on the first substrate through DRIE (direct ion etching), laser, sand blasting or wet etching processes, and forming a plurality of through holes and a plurality of through holes, wherein the aperture of each through hole is larger than that of each through hole; forming compact insulating layers on the side walls of the through holes, the side walls of the through holes and the upper and lower surfaces of the first substrate by a vapor deposition method, wherein the insulating layers are made of silicon oxide, silicon nitride, aluminum oxide, BCB, polyimide, glass, polypropylene and parylene; the plate-shaped material comprises silicon, glass, silicon nitride and gallium arsenide;
(2) Manufacturing electric signal path and metal fin
(1) Manufacturing an electric signal path: forming a continuous metal layer on the surface of the insulating layer through PVD (physical vapor deposition) sputtering, etching a pattern on the metal layer on the upper surface and the lower surface of the first substrate by utilizing a graphical electroplating process to form a metal rewiring layer, and enabling the metal rewiring layer to be arranged on a part of the upper surface of the first substrate, which is contacted with the high-density chip, and a part of the lower surface of the first substrate, which is contacted with the second substrate; the continuous metal layers distributed on the side walls of the through holes and the surface of the side wall insulating layer of the through holes are metal interconnection layers and are in contact with the metal rewiring layer to form an electric signal path;
(2) manufacturing a metal fin: taking a metal plate or an alloy plate as a second substrate, and forming a plurality of metal fins which are distributed in parallel in an array mode by utilizing a DRIE etching process, wherein the length of each metal fin is equal to the distance between metal rewiring layers on the upper surface and the lower surface of the first substrate; the second substrate and the metal fin are made of the same material and comprise at least one of tungsten, titanium, molybdenum, titanium tungsten, nickel, germanium and metal alloy thereof;
(3) And bonding the first substrate and the second substrate through a bonding process, wherein the metal fins are arranged in the through holes, and the through holes and the metal fins form metal microchannels, so that the adapter plate embedded with the metal microchannels is formed.
In a preferred embodiment of the present invention, step (2) (1) is to make the electrical signal path: forming a continuous barrier layer and a continuous metal layer on the surface of the insulating layer, wherein the barrier layer is arranged between the metal layer and the insulating layer, and etching patterns on the barrier layer and the metal layer on the upper surface and the lower surface of the first substrate by utilizing a graphical electroplating process to form a metal rewiring layer so that the metal rewiring layer is arranged on the part of the upper surface of the first substrate, which is contacted with the high-density chip, and the part of the lower surface of the first substrate, which is contacted with the second substrate; the continuous metal layers distributed on the side walls of the through holes and the surface of the side wall insulating layer of the through holes are metal interconnection layers and are in contact with the metal rewiring layer to form an electric signal passage; the barrier layer material comprises at least one of Ta, taN and TiW, and the insulating layer, the metal interconnection layer and the barrier layer arranged on the side wall of the through hole are annular in cross section.
Compared with the background technology, the technical scheme has the following advantages:
1. the through holes are arranged among the through holes, metal fins are arranged in the through holes in an array mode, the upper ends of the metal fins abut against the high-density chip, and the lower ends of the metal fins are fixedly connected with the second substrate; the size of the through holes and the number of the metal fins can be set according to the high-density chip, so that a good heat conduction effect is achieved.
2. The embedded metal fins effectively improve the chip assembling density on the adapter plate and reduce the size of the three-dimensional chip packaging.
3. The preparation method has simple process and controllable cost.
Drawings
FIG. 1 is a schematic view of a first substrate, a through hole, and a through hole structure according to the present invention;
FIG. 2 is a schematic view of an insulating layer structure according to the present invention;
FIG. 3 is a schematic view of the structure of a metal interconnect layer and a metal redistribution layer according to the present invention;
FIG. 4 is a schematic view of a second substrate and metal fin structure of the present invention;
FIG. 5 is a schematic view of an interposer with embedded metal microchannels according to the present invention;
FIG. 6 is a schematic cross-sectional view of an interposer with embedded metal microchannels according to the present invention;
FIG. 7 is a top view of an interposer with embedded metal microchannels according to the present invention;
FIG. 8 is a schematic diagram of a structure of the present invention used with a high density chip.
Detailed Description
The invention is explained in detail below with reference to the drawings and examples:
example 1
Referring to fig. 1-7, the method for manufacturing an interposer with embedded metal micro-channels of the present embodiment includes the following steps:
(1) Manufacturing the first substrate 1 and the insulating layer 11: taking a silicon material plate as a first substrate 1, and forming a plurality of through holes 13 and a plurality of through holes 14 on the silicon material plate by a DRIE (direct DRIE etching) process, wherein the aperture of each through hole 14 is larger than the diameter of each through hole 13; forming dense insulating layers 11 on the side walls of the through holes 13, the side walls of the through holes 14 and the upper and lower surfaces of the first substrate 1 by a vapor deposition method;
(2) Manufacturing an electric signal path and a metal fin:
(1) manufacturing an electric signal path: forming a continuous metal layer on the surface of the insulating layer 11 by PVD sputtering, etching a pattern on the metal layer on the upper surface and the lower surface of the first substrate 1 by using a patterned electroplating process to form a metal rewiring layer 15, and arranging the metal rewiring layer 15 on a part of the upper surface of the first substrate 1, which is contacted with the high-density chip, and a part of the lower surface of the first substrate 1, which is contacted with the second substrate 2; the continuous metal layer distributed on the side wall of the through hole 13 and the surface of the side wall insulating layer of the through hole 14 is a metal interconnection layer 12, and is contacted with the metal rewiring layer 15 to form an interconnection area, and a stable and continuous electric signal passage is formed between the metal interconnection layer 12 and the metal rewiring layer 15 through the thickening effect of the graphical electroplating process, so that the redistribution of signals of the high-density chip 3 is realized;
(2) manufacturing the metal fins 22: taking one glass plate as a second substrate 2, manufacturing an SU-8 photoresist mask on the second substrate 2, and forming a plurality of metal fins 22 which are parallel to each other and distributed in an array by a LIGA (laser induced manufacturing) copper electroforming process, wherein the length of each metal fin 22 is equal to the distance between the patterned metal layers on the upper surface and the lower surface of the first substrate 1;
the through hole 14 and the metal fin 22 form a metal micro-channel; the upper ends of the metal fins 22 are abutted against the high-density chip 3, and the lower ends of the metal fins are connected with the second substrate 2, so that good heat conduction and heat dissipation effects can be achieved;
(3) And thinning the back surface of the second substrate 2, bonding the first substrate 1 and the second substrate 2 by a silicon glass anodic bonding process, and arranging the metal fins 22 in the through holes 14 to form metal microchannels, thereby forming the adapter plate embedded with the metal microchannels.
The interposer with the embedded metal microchannel, which is prepared in this embodiment, is used for integrating a high-density chip, and includes a first substrate 1 and a second substrate 2 which are bonded to each other, where the thickness of the first substrate 1 is 300 μm to 500 μm, and a metal microchannel is arranged inside the first substrate;
the first substrate 1 is provided with a plurality of through holes 13, a plurality of through holes 14, an insulating layer 11, a metal interconnection layer 12 and a metal rewiring layer 15; the through holes 13 and the through holes 14 are distributed at intervals on the first substrate 1; the insulating layer 11 is continuously arranged on the side wall of the through hole 13, the side wall of the through hole 14 and the upper and lower surfaces of the first substrate 1; the metal interconnection layer 12 is continuously arranged on the surface of the insulating layer on the side wall of the through hole 13 and the side wall of the through hole 14, a barrier layer is further arranged between the insulating layer 11 and the metal interconnection layer 12, the insulating layer 11, the metal interconnection layer 12 and the barrier layer arranged on the side wall of the through hole are annular in cross section, and the annular metal interconnection layer is grown on the side wall of the through hole through shape-preserving electroplating to effectively avoid stress concentration of the substrate; the metal rewiring layer 15 is arranged on a part, contacting the high-density chip 3, of the upper surface insulating layer 11 of the first substrate 1 and a part, contacting the second substrate 2, of the lower surface insulating layer of the first substrate 1; the metal rewiring layer 15 is in contact with the metal interconnection layer 12 to form an electric signal path;
the first substrate 1 and the second substrate 2 are provided with bonding structures which are nested with each other, the lower surface of the first substrate is bonded with the upper surface of the second substrate, a plurality of metal fins 22 are arranged at the positions of the bonding surfaces of the second substrate 2 and the first substrate 1, the metal fins 22 are positioned in the through holes 14, the lower ends of the metal fins are fixedly connected with the second substrate 2, and the upper ends of the metal fins extend to the plane of the metal rewiring layer 15 on the upper surface of the first substrate 1;
the metal microchannel comprises a through hole 14 and a metal fin 22; when the high-density chip 3 is integrated on the adapter plate, the high-density chip 3 is arranged above the first substrate 1, the electric signal is redistributed through the metal rewiring layer 15 and the metal interconnection layer on the upper surface of the first substrate 1, and heat generated by the high-density chip 3 is led out through the metal microchannel.
Referring to fig. 8, in the present embodiment, the metal redistribution layer 15 further includes a portion that is disposed on the upper surface of the first substrate 1 and is not in contact with the high-density chip 3, and the metal redistribution layer 15 is electrically connected to the high-density chip 3 through a gold wire, so as to ensure diversity of signal distribution.
Example 2
Example 2 differs from example 1 in that: step (2) manufacturing an electric signal path and a metal fin:
(1) manufacturing an electric signal path: forming a continuous metal layer on the surface of the insulating layer 11 by PVD sputtering, wherein the metal layer comprises a barrier layer TiW and a seed layer Cu, etching a pattern on the metal layer on the upper surface and the lower surface of the first substrate 1 to form a metal rewiring layer 15 after a copper electroplating process is used for masking by photoresist, thickening by electroplating copper, and removing the photoresist and the seed layer/barrier layer, so that the metal rewiring layer 15 is arranged on the part of the upper surface of the first substrate 1, which is contacted with a high-density chip, and the part of the lower surface of the first substrate 1, which is contacted with the second substrate 2; the continuous metal layer distributed on the side wall of the through hole 13 and the surface of the side wall insulating layer of the through hole 14 is a metal interconnection layer 12, and is contacted with the metal rewiring layer 15 to form an interconnection area, and a stable and continuous electric signal passage is formed between the metal interconnection layer 12 and the metal rewiring layer 15 through the thickening effect of the graphical electroplating process to form an electric signal passage and realize the redistribution of signals of the high-density chip 3;
(2) manufacturing the metal fin 22: taking a metal tungsten plate as a second substrate, manufacturing an SU-8 photoresist mask on the second substrate 2, and forming a plurality of metal fins 22 which are parallel to each other and distributed in an array through a DRIE (direct drive etching) process, wherein the length of each metal fin 22 is equal to the distance between the metal rewiring layers 15 on the upper surface and the lower surface of the first substrate 1; the second substrate 2 and the metal fin 22 are made of the same material.
The interposer with the embedded metal microchannel, which is prepared in this embodiment, is used for integrating a high-density chip, and includes a first substrate 1 and a second substrate 2 which are bonded to each other, where the thickness of the first substrate 1 is 300 μm to 500 μm, and a metal microchannel is arranged inside the first substrate;
the first substrate 1 is provided with a plurality of through holes 13, a plurality of through holes 14, an insulating layer 11, a metal interconnection layer 12 and a metal rewiring layer 15; the through holes 13 and the through holes 14 are distributed at intervals on the first substrate 1; the insulating layer 11 is continuously arranged on the side wall of the through hole 13, the side wall of the through hole 14 and the upper and lower surfaces of the first substrate 1; the metal interconnection layer 12 is continuously arranged on the surface of the insulating layer on the side wall of the through hole 13 and the side wall of the through hole 14; a barrier layer is further arranged between the insulating layer 11 and the metal interconnection layer 12, and the insulating layer 11, the metal interconnection layer 12 and the barrier layer arranged on the side wall of the through hole are in cross section; the metal rewiring layer 15 is arranged on a part of the upper surface insulating layer 11 of the first substrate 1, which is in contact with the high-density chip 3, and on a part of the lower surface insulating layer of the first substrate 1, which is in contact with the second substrate 2; the metal rewiring layer 15 is in contact with the metal interconnection layer 12 to form an electric signal path;
the first substrate 1 and the second substrate 2 are provided with bonding structures which are nested with each other, the lower surface of the first substrate is bonded with the upper surface of the second substrate, a plurality of metal fins 22 are arranged at the positions of the bonding surfaces of the second substrate 2 and the first substrate 1, the metal fins 22 are positioned in the through holes 14, the lower ends of the metal fins are fixedly connected with the second substrate 2, and the upper ends of the metal fins extend to the plane of the metal rewiring layer 15 on the upper surface of the first substrate 1;
the metal microchannel comprises a through hole 14 and a metal fin 22; when the high-density chip 3 is integrated on the adapter plate, the high-density chip 3 is arranged above the first substrate 1, the electric signal is redistributed through the metal rewiring layer 15 and the metal interconnection layer on the upper surface of the first substrate 1, and heat generated by the high-density chip 3 is led out through the metal microchannel.
It will be appreciated by those skilled in the art that the same or similar technical effects as those of the above embodiments can be expected when the technical parameters of the present invention are changed within the following ranges:
the material of the first substrate 1 includes silicon, glass, silicon nitride, and gallium arsenide.
The insulating layer 11 is made of silicon oxide, silicon nitride, aluminum oxide, BCB, polyimide, glass, polypropylene or parylene.
The material of the second substrate 2 required by the LIGA electroforming process comprises silicon, glass, silicon nitride and gallium arsenide; the metal fin 22 is made of copper, aluminum, gold, or tungsten.
The second substrate 2 material required by the DRIE process includes tungsten, titanium, molybdenum, titanium tungsten, nickel, germanium and their alloys, and the material of the metal fin 22 is the same as that of the second substrate 2.
The manufacturing method of the through hole 13 and the through hole 14 on the first substrate 1 comprises DRIE, laser, sand blasting, wet etching and ultrasonic processing.
The method for manufacturing the insulating layer 11 includes thermal oxidation, atomic layer deposition, chemical vapor deposition, sputtering, spin coating, glue spraying and combinations thereof.
The manufacturing method of the metal interconnection layer 12 and the metal rewiring layer 15 comprises at least one of evaporation, sputtering, electroplating, electroless plating and chemical vapor deposition.
The above description is only a preferred embodiment of the present invention, and therefore should not be taken as limiting the scope of the invention, which is defined by the appended claims and their equivalents.
Claims (9)
1. The utility model provides an interposer of embedded metal microchannel for integrated high density chip, its characterized in that: the micro-channel structure comprises a first substrate and a second substrate which are bonded with each other, wherein a metal micro-channel is arranged in the first substrate;
the first substrate is provided with a plurality of through holes, an insulating layer, a metal interconnection layer and a metal rewiring layer; the through holes and the through holes are distributed on the first substrate at intervals; the insulating layer is continuously arranged on the side wall of the through hole, the side wall of the through hole and the upper surface and the lower surface of the first substrate; the metal interconnection layer is continuously arranged on the surfaces of the insulating layers of the side walls of the through holes and the side walls of the through holes; the metal rewiring layer is arranged on a part, in contact with the high-density chip, of the first substrate upper surface insulating layer and a part, in contact with the second substrate, of the first substrate lower surface insulating layer; the metal rewiring layer is in contact with the metal interconnection layer to form an electric signal path;
the upper surface of the second substrate is provided with a plurality of metal fins, the metal fins are positioned in the through holes, the lower ends of the metal fins are fixedly connected with the second substrate, and the upper ends of the metal fins extend to the plane of the metal rewiring layer on the upper surface of the first substrate;
the metal microchannel comprises a through hole and a metal fin; when the high-density chip is integrated on the adapter plate, the high-density chip is arranged above the first substrate, the electric signal is redistributed through the metal rewiring layer and the metal interconnection layer on the upper surface of the first substrate, and heat generated by the high-density chip is conducted through the metal microchannel;
the material of the metal fin is the same as that of the second substrate, and the metal fin is formed on the surface of the second substrate through a metal DRIE etching process;
and a barrier layer is arranged between the metal interconnection layer and the insulating layer and between the metal rewiring layer and the insulating layer.
2. The interposer of claim 1, wherein said metal microchannel embedded interposer comprises: the first substrate and the second substrate are bonded with each other, and the bonding mode comprises gold bonding, silicon glass anodic bonding, silicon bonding and BCB bonding.
3. The interposer of claim 1 wherein: the first substrate material comprises silicon, glass, silicon nitride and gallium arsenide.
4. The interposer of claim 1, wherein said metal microchannel embedded interposer comprises: the second substrate is made of silicon, glass, silicon nitride and gallium arsenide; the metal fin is made of copper, aluminum, gold and tungsten and is formed on the surface of the second substrate through a LIGA electroforming process.
5. The interposer of claim 1 wherein: the second substrate material comprises metal and/or metal alloy thereof, and the metal is at least one of tungsten, titanium, molybdenum, titanium tungsten, nickel and germanium.
6. The interposer of claim 1, wherein said metal microchannel embedded interposer comprises: the barrier layer material comprises at least one of Ta, taN and TiW, and the insulating layer, the metal interconnection layer and the barrier layer arranged on the side wall of the through hole are annular in cross section.
7. The method for preparing an interposer with embedded metal microchannels as claimed in any one of claims 1 to 6, wherein: the method comprises the following steps:
(1) Manufacturing a first substrate and an insulating layer: taking a plate-shaped material as a first substrate, and forming a plurality of through holes and a plurality of through holes on the first substrate through DRIE (direct ion etching), laser, sand blasting or wet etching processes, wherein the hole diameter of each through hole is larger than that of each through hole; forming compact insulating layers on the side walls of the through holes, the side walls of the through holes and the upper and lower surfaces of the first substrate by a vapor deposition method, wherein the insulating layers are made of silicon oxide, silicon nitride, aluminum oxide, BCB (barium-boron), polyimide, glass, polypropylene and parylene; the material of the first substrate comprises silicon, glass, silicon nitride and gallium arsenide;
(2) Manufacturing electric signal path and metal fin
(1) Manufacturing an electric signal path: forming a continuous metal layer on the surface of the insulating layer through PVD (physical vapor deposition) sputtering, etching a pattern on the metal layer on the upper surface and the lower surface of the first substrate by utilizing a graphical electroplating process to form a metal rewiring layer, and enabling the metal rewiring layer to be arranged on a part of the upper surface of the first substrate, which is contacted with the high-density chip, and a part of the lower surface of the first substrate, which is contacted with the second substrate; the continuous metal layers distributed on the side walls of the through holes and the surface of the side wall insulating layer of the through holes are metal interconnection layers and are in contact with the metal rewiring layer to form an electric signal path;
(2) manufacturing a metal fin: taking a semiconductor plate as a second substrate, and forming a plurality of metal fins which are distributed in a parallel array by LIGA electroforming, wherein the length of each metal fin is equal to the distance between metal rewiring layers on the upper surface and the lower surface of the first substrate; the second substrate is made of silicon, glass, silicon nitride and gallium arsenide; the metal fin is made of copper, aluminum, gold and tungsten;
(3) And bonding the first substrate and the second substrate through a bonding process, wherein the metal fins are arranged in the through holes, and the through holes and the metal fins form metal microchannels, so that the adapter plate embedded with the metal microchannels is formed.
8. The method for preparing an interposer with embedded metal microchannels as claimed in any one of claims 1 to 6, wherein: the method comprises the following steps:
(1) Manufacturing a first substrate and an insulating layer: taking a plate-shaped material as a first substrate, forming through holes on the first substrate through DRIE (direct ion etching), laser, sand blasting or wet etching processes, and forming a plurality of through holes and a plurality of through holes, wherein the aperture of each through hole is larger than that of each through hole; forming compact insulating layers on the side walls of the through holes, the side walls of the through holes and the upper and lower surfaces of the first substrate by a vapor deposition method, wherein the insulating layers are made of silicon oxide, silicon nitride, aluminum oxide, BCB, polyimide, glass, polypropylene and parylene; the plate-shaped material comprises silicon, glass, silicon nitride and gallium arsenide;
(2) Manufacturing electric signal path and metal fin
(1) Manufacturing an electric signal path: forming a continuous metal layer on the surface of the insulating layer through PVD (physical vapor deposition) sputtering, etching a pattern on the metal layer on the upper surface and the lower surface of the first substrate by utilizing a graphical electroplating process to form a metal rewiring layer, and enabling the metal rewiring layer to be arranged on a part of the upper surface of the first substrate, which is contacted with the high-density chip, and a part of the lower surface of the first substrate, which is contacted with the second substrate; the continuous metal layers distributed on the side walls of the through holes and the surface of the side wall insulating layer of the through holes are metal interconnection layers and are in contact with the metal rewiring layer to form an electric signal path;
(2) manufacturing a metal fin: taking a metal plate or an alloy plate as a second substrate, and forming a plurality of metal fins which are distributed in parallel in an array mode by utilizing a DRIE etching process, wherein the length of each metal fin is equal to the distance between metal rewiring layers on the upper surface and the lower surface of the first substrate; the second substrate and the metal fin are made of the same material and comprise at least one of tungsten, titanium, molybdenum, titanium tungsten, nickel, germanium and metal alloy thereof;
(3) And bonding the first substrate and the second substrate through a bonding process, wherein the metal fins are arranged in the through holes, and the through holes and the metal fins form metal microchannels, so that the adapter plate embedded with the metal microchannels is formed.
9. The production method according to claim 7 or 8, characterized in that:
manufacturing an electric signal path in the step (2) (1): forming a continuous barrier layer and a continuous metal layer on the surface of the insulating layer, wherein the barrier layer is arranged between the metal layer and the insulating layer, and etching patterns on the barrier layer and the metal layer on the upper surface and the lower surface of the first substrate by utilizing a graphical electroplating process to form a metal rewiring layer so that the metal rewiring layer is arranged on the part of the upper surface of the first substrate, which is contacted with the high-density chip, and the part of the lower surface of the first substrate, which is contacted with the second substrate; the continuous metal layers distributed on the side walls of the through holes and the surface of the side wall insulating layer of the through holes are metal interconnection layers and are in contact with the metal rewiring layer to form an electric signal path;
the barrier layer material comprises at least one of Ta, taN and TiW, the insulating layer is arranged on the side wall of the through hole, the metal interconnection layer and the barrier layer are annular in cross section.
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| CN109378296B (en) * | 2018-10-11 | 2020-12-01 | 深圳市修颐投资发展合伙企业（有限合伙） | Method for interconnecting electronic component and substrate |
| CN110707058A (en) * | 2019-09-24 | 2020-01-17 | 杭州臻镭微波技术有限公司 | Manufacturing method of three-dimensional heterogeneous module based on graphene as heat dissipation coating |
| CN113161306B (en) * | 2021-04-15 | 2024-02-13 | 浙江集迈科微电子有限公司 | Efficient heat dissipation structure of chip and preparation process thereof |
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