CN107249107B - Video controller and image processing method and device - Google Patents
Video controller and image processing method and device Download PDFInfo
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- CN107249107B CN107249107B CN201710305378.6A CN201710305378A CN107249107B CN 107249107 B CN107249107 B CN 107249107B CN 201710305378 A CN201710305378 A CN 201710305378A CN 107249107 B CN107249107 B CN 107249107B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/40—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
Abstract
The embodiment of the invention discloses a video controller and an image processing method and device, wherein one or more video sources are selected in the video controller as target video sources required by mutually independent scaling processing, so that the multi-path video finally output by the video controller can be different in resolution and even different in video content, and the technical effect that the video controller supports multiple paths and different outputs is achieved.
Description
Technical Field
The present invention relates to the field of video control and processing technologies, and in particular, to a video controller, an image processing method, and an image processing apparatus.
Background
The current video controllers have a plurality of different output interfaces, but the output resolution, the image quality and the display content of each interface are the same. Thus, in some situations, if there are different devices and different requirements, it is necessary for the video controller to output different resolutions or contents at the same time, and more than one device is needed to implement the resolution or content. Therefore, in view of the considerations of cost performance, ease of use, etc., there is a need for a video controller that can achieve a variety of different outputs.
Disclosure of Invention
Embodiments of the present invention provide a video controller, an image processing method, and an image processing apparatus, which solve the problem in the prior art that the video controller cannot output different resolutions or contents at the same time, so as to achieve the technical effect of supporting multiple different outputs.
In one aspect, a video controller is provided, including: the micro control unit is used for outputting a scaling processing control signal; the image processing unit is connected with the micro control unit and used for selecting a first video source from the multi-path input video sources according to the zooming processing control signal, zooming the first video source to a first target resolution to obtain a first zoomed video and selecting a second video source, zooming the second video source to a second target resolution to obtain a second zoomed video; the first video coding unit is connected with the image processing unit and the first output interface and is used for coding the first zoomed video to obtain a first coded video and outputting the first coded video through the first output interface; and the second video coding unit is connected with the image processing unit and the second output interface and is used for coding the second scaled video to obtain a second coded video and outputting the second coded video through the second output interface.
In one embodiment of the present invention, the video controller further comprises: a video processing chip; the video processing chip is connected with the image processing unit and is used for processing a specified input video source and outputting a processed video source; the processed video source is one of the multi-path input video sources, and the specified input video source is a specified video source selected from video sources except the processed video source in the multi-path input video sources by the image processing unit responding to the video source selection signal output by the micro control unit.
In one embodiment of the present invention, the micro control unit is configured to output a first frame rate control signal and a second frame rate control signal to the image processing unit; the image processing unit is used for responding to the first frame frequency control signal to perform frame frequency conversion processing on the video subjected to the first scaling processing and outputting the video to the first video coding unit at a first fixed frame frequency, and responding to the second frame frequency control signal to perform frame frequency conversion processing on the video subjected to the second scaling processing and outputting the video to the second video coding unit at a second fixed frame frequency.
In one embodiment of the present invention, the video controller further comprises: a transmitting card circuit connected to the image processing unit; the transmitting card circuit comprises a programmable logic device, a network transmission module and a network port which are sequentially connected, and the image processing unit is the programmable logic device.
In one embodiment of the present invention, the first target resolution and the second target resolution are resolutions of different sizes; the first video source and the second video source are selected from the same input video source in the multi-path input video sources, or the first video source and the second video source are selected from the two input video sources in the multi-path input video sources.
In still another aspect, an image processing method is provided, including: receiving a plurality of input video sources; selecting a first video source and a second video source from the multiple input video sources; zooming the first video source to a first resolution to obtain a first zoomed video; performing read-write operation on the first zoomed video to output the first zoomed video; zooming the second video source to a second resolution to obtain a second zoomed video; and performing read-write operation on the second zoomed video to output the second zoomed video.
In one embodiment of the present invention, the receiving the multi-input video source includes: receiving at least one path of first input video source; selecting a specified video source from the at least one first input video source for output; and receiving a second input video source, wherein the second input video source is a processed video source obtained after the video processing chip processes the specified video source.
In an embodiment of the present invention, the performing a read-write operation on the first scaled video to output the first scaled video includes: and controlling the read-write operation of the first scaled video to perform frame frequency conversion on the first scaled video, so that the first scaled video is output at a first fixed frame frequency.
In an embodiment of the present invention, the performing a read-write operation on the second scaled video to output the second scaled video includes: and controlling the read-write operation of the second scaled video to perform frame frequency conversion on the second scaled video, so that the second scaled video is output at a second fixed frame frequency.
In one embodiment of the invention, the first resolution and the second resolution are resolutions of different sizes; the first video source and the second video source are selected from the same input video source in the multi-path input video sources, or the first video source and the second video source are selected from the two input video sources in the multi-path input video sources.
In another aspect, there is provided an image processing apparatus including: the video source receiving module is used for receiving a plurality of paths of input video sources; the video source selection module is used for selecting a first video source and a second video source from the multi-path input video sources; the first zooming module is used for zooming the first video source to a first resolution ratio to obtain a first zoomed video; the first memory access control module is used for performing read-write operation on the first zoomed video so as to output the first zoomed video; the second zooming module is used for zooming the second video source to a second resolution ratio to obtain a second zoomed video; and the second memory access control module is used for performing read-write operation on the second scaled video to output the second scaled video.
In one embodiment of the present invention, the video source receiving module includes: the first input module is used for receiving at least one path of first input video source; the output module is used for selecting a specified video source from the at least one path of first input video source and outputting the selected video source to the video processing chip for processing; and the second input module is used for receiving a second input video source, wherein the second input video source is a processed video source obtained after the video processing chip processes the specified video source.
In one embodiment of the present invention, the image processing apparatus includes: the first frame frequency conversion module is used for controlling the first memory access control module to read and write the first scaled video so as to perform frame frequency conversion on the first scaled video, so that the first scaled video is output at a first fixed frame frequency; and the second frame frequency conversion module is used for controlling the second memory access control module to perform read-write operation on the second scaled video so as to perform frame frequency conversion on the second scaled video, so that the second scaled video is output at a second fixed frame frequency.
In an embodiment of the present invention, the first video source and the second video source are the same input video source selected from the multiple input video sources, or the first video source and the second video source are two input video sources selected from the multiple input video sources.
One of the above technical solutions has the following advantages or beneficial effects: one or more paths of video sources are selected as target video sources required by mutually independent scaling processing, so that the paths of video finally output by the video controller can be different in resolution and even different in video content, and the technical effect that the video controller supports multiple paths of different outputs is achieved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a video controller according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of internal modules associated with an image processing unit in the video controller shown in FIG. 1;
FIG. 3 is a schematic diagram of another internal module of the image processing unit associated with the video controller shown in FIG. 1;
FIG. 4 is a diagram illustrating a video controller according to a second embodiment of the present invention;
FIG. 5 is a schematic diagram of internal modules associated with the image processing unit in the video controller shown in FIG. 4;
FIG. 6 is a schematic diagram of another internal module associated with the image processing unit in the video controller shown in FIG. 4;
fig. 7 is a schematic structural diagram of a video controller according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
First embodiment
As shown in fig. 1, a video controller 10 provided in a first embodiment of the present invention includes: a micro control unit 11, an image processing unit 13, a memory 15, a first video encoding unit 17a, a second video encoding unit 17b, a first output interface 19a and a second output interface 19 b.
The micro control unit 11 is configured to output a scaling control signal to the image processing unit 13. In this embodiment, the MCU 11 is, for example, an MCU, such as an MCU based on an ARM core, and the scaling control signal output by the MCU is mainly responsible for setting the target video source and the target resolution required for performing multi-path scaling in the image processing unit 13.
The image processing unit 13 is connected to the micro control unit 11, and configured to select a first video source from the multiple input video sources according to the scaling control signal output by the micro control unit 11, perform scaling processing on the first video source to a first target resolution to obtain a first scaled video, and select a second video source, perform scaling processing on the second video source to a second target resolution to obtain a second scaled video. In this embodiment, the image processing unit 13 is, for example, a programmable logic device, such as an FPGA (Field programmable gate Array) device.
The memory 15 is connected to the image processing unit 13, is a volatile memory such as an SDRAM, and is used as a buffer when the image processing unit 13 performs image processing.
The first video encoding unit 17a is connected to the image processing unit 13, and is configured to perform encoding processing on the first scaled video to obtain a first encoded video. In this embodiment, the first video encoding unit 17a includes, for example, a digital video decoding chip such as a DVI video encoding chip or an HDMI video encoding chip.
The second video encoding unit 17b is connected to the image processing unit 13, and is configured to perform encoding processing on the second scaled video to obtain a second encoded video. In this embodiment, the second video encoding unit 17b includes, for example, an analog video decoding chip such as a VGA video encoding chip.
The first output interface 19a is connected to the first video encoding unit 17a, and is configured to output the first encoded video. In this embodiment, the first output interface 19a is, for example, a DVI interface or an HDMI interface, and is used to output the first encoded video to a sending card in the LED display screen control system.
The second output interface 19b is connected to the second video encoding unit 17a, and is configured to output the second encoded video. In this embodiment, the second output interface 19b is, for example, a VGA interface, and is used for outputting the second encoded video to the projector.
In view of the above, in the embodiment shown in fig. 1, the resolution of the video images output by the first output interface 19a and the second output interface 19b are different, for example, the output resolution (corresponding to the first target resolution) of the first output interface 19a is 1080P, and the output resolution (corresponding to the second target resolution) of the second output interface 19b is 800 × 600. As for the first video source and the second video source performing the scaling processing, since the two video sources perform the scaling processing independently, when the display output devices respectively connected to the first output interface 19a and the second output interface 19b require the same video content, the first video source and the second video source may be selected from the same video source; if the display output devices respectively connected to the first output interface 19a and the second output interface 19b require different video contents, the first video source and the second video source are selected from two video sources.
Referring to fig. 2, an internal block diagram of the image processing unit 13 is shown. In fig. 2, the image processing unit 13 includes a video source receiving module 131, a video source selecting module 133, a first scaling module 135a, a second scaling module 135b, a first memory access control module 137a, and a second memory access control module 137b, which in this embodiment may be implemented by software modules executed in a programmable logic device, and constitute an image processing apparatus in this embodiment of the present invention.
The video source receiving module 131 is configured to receive the multiple input video sources; the video source selection module 133 is configured to select the first video source and the second video source from the multiple input video sources in response to the scaling control signal output by the micro control unit 11; the first scaling module 135a is configured to scale the first video source to the first target resolution to obtain a first scaled video; the first memory access control module 137a is configured to perform a read-write operation on the first scaled video to output the first scaled video; the second scaling module 135b is configured to scale the second video source to the second target resolution to obtain a second scaled video; the second memory access control module 137b is configured to perform a read-write operation on the second scaled video to output the second scaled video.
As shown in fig. 3, in other embodiments, the image processing unit 13 includes a video source receiving module 131, a video source selecting module 133, a first scaling module 135a, a second scaling module 135b, a first memory access control module 137a, a second memory access control module 137b, a first frame rate conversion module 139a, and a second frame rate conversion module 139 b. These functional modules may be implemented by software modules executed in a programmable logic device in this embodiment, and constitute another image processing apparatus in this embodiment.
The video source receiving module 131 is configured to receive the multiple input video sources; the video source selection module 133 is configured to select the first video source and the second video source from the multiple input video sources in response to the scaling control signal output by the micro control unit 11; the first scaling module 135a is configured to scale the first video source to the first target resolution to obtain a first scaled video; the first memory access control module 137a is configured to perform a read-write operation on the first scaled video to output the first scaled video; the second scaling module 135b is configured to scale the second video source to the second target resolution to obtain a second scaled video; the second memory access control module 137b is configured to perform a read-write operation on the second scaled video to output the second scaled video. The first frame frequency conversion module 139a is configured to control, according to a first frame frequency control signal output by the micro control unit 11, the first memory access control module 137a to perform read-write operation on the first scaled video so as to perform frame frequency conversion on the first scaled video, so that the first scaled video is output at a first fixed frame frequency; the second frame frequency conversion module 139b is configured to control, according to a second frame frequency control signal output by the micro control unit 11, the second memory access control module to perform read-write operation on the second scaled video so as to perform frame frequency conversion on the second scaled video, so that the second scaled video is output at a second fixed frame frequency. In this embodiment, the first frame frequency control signal and the second frame frequency control signal may be generated by the micro control unit 11 after obtaining the EDID of the display output device connected to the first output interface 19a and the second output interface 19b, or may be generated by setting the frame frequency through the human-computer interface, so that the video after the scaling processing may be output to the display output device according to the fixed VESA video standard after the frame frequency conversion.
The first frame rate conversion module 139a and the second frame rate conversion module 139b are provided in this embodiment because: in the practical application process, the processed video source is limited by the performance of the rear-end display output equipment, so that the video signals with various frame frequencies or the video signals with non-VESA standard cannot be displayed in the display output equipment, and the requirements of customers cannot be met, therefore, the video source can output standard time sequence to adapt to the display output equipment by arranging the frame frequency conversion module.
Furthermore, it is worth mentioning that Frame rate conversion is implemented by using multiple Frame buffers (Frame buffers), taking 3 Frame buffers as an example, the processing flow is as follows: 1) starting reading after writing a Frame; 2) after reading one Buffer, if finding that the next Buffer is still in writing, repeating to read the current Buffer (repeating frame), otherwise reading the next Buffer; and 3) after writing one Buffer, if finding that the next Buffer is still read, repeating to write the current Buffer (losing frame), otherwise, writing the next Buffer.
Second embodiment
As shown in fig. 4, a video controller 40 provided in a second embodiment of the present invention includes: the system comprises a micro control unit 41, a human-computer interaction display screen 42, an image processing unit 43, a video processing chip 44, a memory 45, a first video coding unit 47a, a second video coding unit 47b, a first output interface 49a and a second output interface 49 b.
The micro control unit 41 is configured to output a video source selection signal and a zoom processing control signal to the image processing unit 43. In this embodiment, the MCU 41 is, for example, an MCU, such as an MCU based on an ARM core, and the output video source selection signal is mainly responsible for selecting a designated video source from the received input video sources and outputting the selected video source to the video processing chip 44 for processing, and the output zoom processing control signal is mainly responsible for setting a target video source and a target resolution required for performing multi-path zoom processing in the image processing unit 43.
The human-computer interaction display 42 is connected to the micro control unit 41, which is used for human-computer interaction and is, for example, a liquid crystal display.
The image processing unit 43 is connected to the micro control unit 41, and configured to select a designated video source from the received input video sources according to a video source selection signal output by the micro control unit 41, output the selected video source to the video processing chip 44 for processing, select a first video source from the multiple input video sources according to a scaling processing control signal output by the micro control unit 41, perform scaling processing to a first target resolution to obtain a first scaled video, and select a second video source, perform scaling processing to a second target resolution to obtain a second scaled video. In this embodiment, the image processing unit 43 is, for example, a programmable logic device, such as an FPGA device.
The video processing chip 44 is connected to the image processing unit 43, and may be a dedicated video processing chip such as an STDP8028 chip or an FLI32626 chip, or a video processing chip developed based on an FPGA. The video processing chip 44 of the present embodiment is configured to process the specified video source output by the image processing unit 43 to obtain a processed video source, and the processed video source is provided to the image processing unit 43 as an input video source thereof.
The memory 45 is connected to the image processing unit 43, is a volatile memory such as an SDRAM, and is used as a buffer when the image processing unit 43 performs image processing.
The first video encoding unit 47a is connected to the image processing unit 43, and is configured to perform encoding processing on the first scaled video to obtain a first encoded video. In this embodiment, the first video encoding unit 47a includes, for example, a digital video decoding chip such as a DVI video encoding chip or an HDMI video encoding chip.
The second video encoding unit 47b is connected to the image processing unit 43, and is configured to perform encoding processing on the second scaled video to obtain a second encoded video. In this embodiment, the second video encoding unit 47b includes, for example, an analog video decoding chip such as a VGA video encoding chip.
The first output interface 49a is connected to the first video encoding unit 47a, and is configured to output the first encoded video. In this embodiment, the first output interface 49a is, for example, a DVI interface or an HDMI interface, and is used to output the first encoded video to a sending card in the LED display screen control system.
The second output interface 49b is connected to the second video encoding unit 47a, and is configured to output the second encoded video. In this embodiment, the second output interface 49b is, for example, a VGA interface, and is used for outputting the second encoded video to the projector.
In view of the above, in the embodiment shown in fig. 4, the resolution of the video images output by the first output interface 49a and the second output interface 49b are different, for example, the output resolution (corresponding to the first target resolution) of the first output interface 49a is 1080P, and the output resolution (corresponding to the second target resolution) of the second output interface 49b is 800 × 600. As for the first video source and the second video source for performing the scaling processing, since the two video sources perform the scaling processing independently, when the display output devices respectively connected to the first output interface 49a and the second output interface 49b require the same video content, the first video source and the second video source may be selected from the same one of the video source sources; if the display output devices respectively connected to the first output interface 49a and the second output interface 49b require different video contents, the first video source and the second video source are selected from two video sources.
Referring to fig. 5, an internal block diagram of the image processing unit 43 is shown. In fig. 5, the image processing unit 43 includes a video source receiving module 431, a video source selecting module 433, a first scaling module 435a, a second scaling module 435b, a first memory access control module 437a, and a second memory access control module 437b, which in this embodiment may be implemented by software modules executed in a programmable logic device, and constitute still another image processing apparatus in the embodiment of the present invention.
The video source receiving module 431 is used for receiving the multi-channel input video source, and for example, includes a first input module 4310, an output module 4312 and a second input module 4314. The first input module 4310 is configured to receive at least one input video source; the output module 4312 is used for selecting a designated video source from the input video sources received by the first input module 4310 in response to the video source selection signal output by the micro control unit 43 and outputting the selected video source to the video processing chip 44 for processing; the second input module 4314 is used for receiving an input video source, for example, a processed video source obtained by processing the specified video source output by the output module 4312 by the video processing chip 44.
The video source selection module 433 is configured to select the first video source and the second video source from the multiple input video sources in response to the scaling control signal output by the micro control unit 41; the first scaling module 435a is configured to scale the first video source to the first target resolution to obtain a first scaled video; the first memory access control module 437a is configured to perform a read-write operation on the first scaled video to output the first scaled video; the second scaling module 435b is configured to scale the second video source to the second target resolution to obtain a second scaled video; the second memory access control module 437b is configured to perform a read-write operation on the second scaled video, so as to output the second scaled video.
As shown in fig. 6, in another embodiment, the image processing unit 43 includes a video source receiving module 431, a video source selecting module 433, a first scaling module 435a, a second scaling module 435b, a first memory access control module 437a, a second memory access control module 437b, a first frame rate conversion module 439a, and a second frame rate conversion module 439b, and these functional modules may be implemented by software modules executed in a programmable logic device in this embodiment, and constitute still another image processing apparatus in the embodiment of the present invention.
The video source receiving module 431 is used for receiving the multi-channel input video source, and for example, includes a first input module 4310, an output module 4312 and a second input module 4314. The first input module 4310 is configured to receive at least one input video source; the output module 4312 is used for selecting a designated video source from the input video sources received by the first input module 4310 in response to the video source selection signal output by the micro control unit 43 and outputting the selected video source to the video processing chip 44 for processing; the second input module 4314 is used for receiving an input video source, for example, a processed video source obtained by processing the specified video source output by the output module 4312 by the video processing chip 44.
The video source selection module 433 is configured to select the first video source and the second video source from the multiple input video sources in response to the scaling control signal output by the micro control unit 41; the first scaling module 435a is configured to scale the first video source to the first target resolution to obtain a first scaled video; the first memory access control module 437a is configured to perform a read-write operation on the first scaled video to output the first scaled video; the second scaling module 435b is configured to scale the second video source to the second target resolution to obtain a second scaled video; the second memory access control module 437b is configured to perform a read-write operation on the second scaled video, so as to output the second scaled video.
The first frame frequency conversion module 439a is configured to control, according to a first frame frequency control signal output by the micro control unit 41, the read/write operation of the first scaled video by the first memory access control module 437a to perform frame frequency conversion on the first scaled video, so that the first scaled video is output at a first fixed frame frequency. The second frame frequency conversion module 439b is configured to control, according to a second frame frequency control signal output by the micro control unit 41, the second memory access control module to perform read-write operation on the second scaled video so as to perform frame frequency conversion on the second scaled video, so that the second scaled video is output at a second fixed frame frequency. In this embodiment, the first frame rate control signal and the second frame rate control signal may be generated after the micro control unit 41 acquires EDID (Extended Display Identification Data) of the Display output device connected to the first output interface 49a and the second output interface 49b, or may be generated by setting a frame rate through a human-computer interface, and thus, the video after the scaling processing may be output to the Display output device according to the fixed VESA video standard after the frame rate conversion.
The first frame rate conversion module 439a and the second frame rate conversion module 439b are provided in the present embodiment because: in the practical application process, the processed video source is limited by the performance of the rear-end display output equipment, so that the video signals with various frame frequencies or the video signals with non-VESA standard cannot be displayed in the display output equipment, and the requirements of customers cannot be met, therefore, the video source can output standard time sequence to adapt to the display output equipment by arranging the frame frequency conversion module.
Referring to fig. 7, another video controller according to another embodiment of the present invention is provided, which is configured to add a transmitting card circuit 46 to the video controller 40 shown in fig. 4 and connect to the image processing unit 43. In fig. 7, the transmitting card circuit 46 includes: programmable logic device 461, network transport module 463, and port 465 (e.g., a two-way port or more).
The programmable logic device 461 is electrically connected to the image processing unit 43 (for example, a programmable logic device) or the video processing chip 44 to obtain a processed video source output by the video processing chip 44, perform corresponding processing, and then send the processed video source through the network transmission module 463 and the network port 465, so that the LED display screen receives and displays the processed video source through the receiving card; furthermore, the video image data is preferably transmitted between the programmable logic device 461 and the image processing unit 43 (or the video processing chip 44) in a parallel TTL format, and the TTL format video image data is output from the image processing unit 43 (or the video processing chip 44) and then input to the programmable logic device 461 without signal format conversion; of course, the transmission of the processed video source image data between the video processing chip 44 and the image processing unit 43 may also adopt a parallel TTL format without signal format conversion during the transmission process. The network transmission module 463 of the present embodiment includes, for example, an ethernet PHY chip and a network transformer.
Finally, it should be noted that the foregoing embodiments of the present invention are described by taking two independent scaling processes as examples, but the present invention is not limited thereto, and more independent scaling processes may be provided. The first output interface and the second output interface of the video controller are not limited to digital and/or analog video interfaces, and may be other interfaces suitable for outputting video images.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (12)
1. A video controller, comprising:
the micro control unit is used for outputting a scaling processing control signal;
the image processing unit is connected with the micro control unit and used for selecting a first video source from the multi-path input video sources according to the zooming processing control signal, zooming the first video source to a first target resolution to obtain a first zoomed video and selecting a second video source, zooming the second video source to a second target resolution to obtain a second zoomed video;
the first video coding unit is connected with the image processing unit and the first output interface and is used for coding the first zoomed video to obtain a first coded video and outputting the first coded video through the first output interface;
the second video coding unit is connected with the image processing unit and the second output interface and is used for coding the second zoomed video to obtain a second coded video and outputting the second coded video through the second output interface;
the video processing chip is connected with the image processing unit and used for processing an appointed input video source to obtain and output a processed video source in a TTL format, the processed video source in the TTL format is transmitted to the image processing unit without format conversion, and the processed video source in the TTL format is one of the multi-path input video sources; the appointed input video source is an appointed video source selected from video sources except the processed video source in the multi-path input video source by the image processing unit responding to the video source selection signal output by the micro control unit.
2. The video controller according to claim 1, wherein the image processing unit is connected to the programmable logic device, the image processing unit outputs video image data in TTL format, and the video image data in TTL format is input to the programmable logic device without format conversion.
3. The video controller of claim 1, wherein said micro-control unit is configured to output a first frame rate control signal and a second frame rate control signal to said image processing unit;
the image processing unit is used for responding to the first frame frequency control signal to perform frame frequency conversion processing on the video subjected to the first scaling processing and outputting the video to the first video coding unit at a first fixed frame frequency, and responding to the second frame frequency control signal to perform frame frequency conversion processing on the video subjected to the second scaling processing and outputting the video to the second video coding unit at a second fixed frame frequency.
4. The video controller of claim 1, wherein the video controller further comprises: a transmitting card circuit connected to the image processing unit; the transmitting card circuit comprises a programmable logic device, a network transmission module and a network port which are sequentially connected, and the image processing unit is the programmable logic device.
5. The video controller of claim 1,
the first target resolution and the second target resolution are resolutions of different sizes;
the first video source and the second video source are selected from the same input video source in the multi-path input video sources, or the first video source and the second video source are selected from the two input video sources in the multi-path input video sources.
6. An image processing method, comprising:
receiving a plurality of input video sources;
selecting a first video source and a second video source from the multiple input video sources;
zooming the first video source to a first resolution to obtain a first zoomed video;
performing read-write operation on the first zoomed video to output the first zoomed video;
zooming the second video source to a second resolution to obtain a second zoomed video;
performing read-write operation on the second zoomed video to output the second zoomed video;
the receiving of the multiple input video sources comprises receiving at least one first input video source, selecting a specified video source from the at least one first input video source for output, and receiving a second input video source in a TTL format without format conversion, wherein the second input video source is a processed video source in the TTL format obtained by processing the specified video source by a video processing chip.
7. The image processing method according to claim 6, wherein said performing a read-write operation on the first scaled video to output the first scaled video comprises:
and controlling the read-write operation of the first scaled video to perform frame frequency conversion on the first scaled video, so that the first scaled video is output at a first fixed frame frequency.
8. The image processing method according to claim 6, wherein said performing a read-write operation on the second scaled video to output the second scaled video comprises:
and controlling the read-write operation of the second scaled video to perform frame frequency conversion on the second scaled video, so that the second scaled video is output at a second fixed frame frequency.
9. The image processing method according to claim 6,
the first resolution and the second resolution are resolutions of different sizes;
the first video source and the second video source are selected from the same input video source in the multi-path input video sources, or the first video source and the second video source are selected from the two input video sources in the multi-path input video sources.
10. An image processing apparatus characterized by comprising:
the video source receiving module is used for receiving a plurality of paths of input video sources;
the video source receiving module includes:
the first input module is used for receiving at least one path of first input video source;
the output module is used for selecting a specified video source from the at least one path of first input video source and outputting the selected video source to the video processing chip for processing;
the second input module is used for receiving a path of processed video source in TTL format without format conversion, which is obtained after the video processing chip processes the specified video source;
the video source selection module is used for selecting a first video source and a second video source from the multi-path input video sources;
the first zooming module is used for zooming the first video source to a first resolution ratio to obtain a first zoomed video;
the first memory access control module is used for performing read-write operation on the first zoomed video so as to output the first zoomed video;
the second zooming module is used for zooming the second video source to a second resolution ratio to obtain a second zoomed video;
and the second memory access control module is used for performing read-write operation on the second scaled video to output the second scaled video.
11. The image processing apparatus according to claim 10, wherein the image processing apparatus comprises:
the first frame frequency conversion module is used for controlling the first memory access control module to read and write the first scaled video so as to perform frame frequency conversion on the first scaled video, so that the first scaled video is output at a first fixed frame frequency;
and the second frame frequency conversion module is used for controlling the second memory access control module to perform read-write operation on the second scaled video so as to perform frame frequency conversion on the second scaled video, so that the second scaled video is output at a second fixed frame frequency.
12. The image processing apparatus as claimed in claim 10, wherein the first video source and the second video source are the same input video source selected from the multi-input video sources, or wherein the first video source and the second video source are two input video sources selected from the multi-input video sources.
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| CN112449220A (en) * | 2019-08-30 | 2021-03-05 | 西安诺瓦星云科技股份有限公司 | Video playing device and video playing system |
| CN114173054B (en) * | 2020-09-10 | 2024-03-15 | 西安诺瓦星云科技股份有限公司 | Multi-frame frequency spliced video source display control method and system and LED display system thereof |
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