CN107247859A - Verification method, device, electronic equipment and the storage medium of Logic Circuit Design - Google Patents
Verification method, device, electronic equipment and the storage medium of Logic Circuit Design Download PDFInfo
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- CN107247859A CN107247859A CN201710693558.6A CN201710693558A CN107247859A CN 107247859 A CN107247859 A CN 107247859A CN 201710693558 A CN201710693558 A CN 201710693558A CN 107247859 A CN107247859 A CN 107247859A
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The present invention provides a kind of verification method of Logic Circuit Design, including generates configuration data and excited data by verification platform；Configuration and excited data are stored to target memory；It will be configured by verification platform and the excited data sent to object to be tested；References object is controlled to read configuration and excited data from target memory by verification platform, so that references object starts simulation calculation；Object to be tested is the logic circuit code that algorithm is realized with first language, and references object is the code that second language realizes identical algorithms, controls references object to terminate simulation calculation by verification platform；The output data of references object is obtained by verification platform；The output data of object to be tested is obtained by verification platform；The result of object to be tested is determined according to the output data of references object and object to be tested.The present invention also provides a kind of checking device of Logic Circuit Design.The present invention realizes the purpose for accurately verifying object to be tested.
Description
Technical field
The present invention relates to chip design technical field, more particularly to a kind of verification method of Logic Circuit Design, device,
Electronic equipment and storage medium.
Background technology
Because integrated circuit becomes increasingly complex, the logic electricity that digital IC design engineer is write by SystemVerilog
Road code, that is, tested design (Design Under Test, DUT) and also become increasingly complex, how to ensure logic circuit code just
True property is just more and more important.And numeral IC verifies the work of engineer, electric design automation is mainly based upon
The function of (Electronics Design Automation, EDA) software programming test program verifying logic code.It is main at present
The test program of stream is to be based on SystemVerilog language, and this language is Verilog superset, and with object-oriented
Function, can very easily construct the program of higher abstraction hierarchy.
Many algorithm models are complicated at present, such as intelligent algorithm (Artificial Intelligence, AI), and
Include substantial amounts of matrix operation.In the checking of the logic circuit code of the algorithm, if realized with emulator comprising substantial amounts of
The algorithm of matrix operation is, it is necessary to which using more circulation, operational efficiency is low, and debugging is difficult.A kind of method of solution is using straight
Connect DLL (Direct Programming Interface) and call reference model (algorithm model that such as C language is write),
Because the code language of emulator is different from the language of the code of reference model, will result in emulator can not directly read reference
The code of model, certain difficulty is caused to debugging, for example, SystemVerilog emulators can not directly read C code.
The content of the invention
In view of the foregoing, it is necessary to which a kind of verification method of Logic Circuit Design, device, electronic equipment and storage are provided
Medium, by the way that verification platform is combined with references object, is accurately tested the Logic Circuit Design as object to be tested
Card.Also it is avoided that simultaneously and writes substantial amounts of test code, improves the verification efficiency of Logic Circuit Design.
A kind of verification method of Logic Circuit Design, methods described includes：
Configuration data and excited data are generated by verification platform；
The configuration data and excited data are stored to target memory；
The configuration data and the excited data are sent to object to be tested by the verification platform；
References object is controlled to read the configuration data from the target memory and described by the verification platform
Excited data, so that the references object starts simulation calculation, the object to be tested is the logic that algorithm is realized with first language
Circuit code, the references object is that the code of the algorithm is realized with second language, the first language and second language
Speech is different；
The references object is controlled to terminate simulation calculation by the verification platform；
The output data of the references object is obtained by the verification platform；
The output data of the object to be tested is obtained by the verification platform；
According to the output data of the references object and the output data of the object to be tested, the object to be tested is determined
The result.
It is described to store the configuration data and excited data to target memory bag according to the preferred embodiment of the present invention
Include：
The configuration data and excited data are preserved into by text document with preset format, and stored to target storage
Device, the text document includes the combination of one or more of：Plain text document, binary documents, JavaScript object
Marking language document.
According to the preferred embodiment of the present invention, the verification platform is communicated by interface one with the references object, is led to
Cross interface two to be communicated with the object to be tested, the verification platform includes：Data input module, reference model module, number
According to output module and data comparing module；The data input module is used to send the configuration data and the excited data
To object to be tested；The data outputting module is used for the output data for obtaining the object to be tested, and the reference model module is used
In the output data for obtaining the references object, the data comparing module be used for according to the output data of the references object and
The output data of the object to be tested, determines the result of the object to be tested.
It is described to control the references object to be deposited from the target by the verification platform according to the preferred embodiment of the present invention
The configuration data and the excited data are read in reservoir, is included so that the references object starts simulation calculation：
When the verification platform starts, generation controls the process of the references object to start the references object, and
The references object detection is set to store the text document of the configuration data and the excited data；And/or
It is described to control the references object to terminate simulation calculation by the verification platform to include：
Obtain the running state data of the verification platform；The running state data is stored to described with preset format
So that the references object carries out detection done state data in target memory；
When the references object detect it is described include done state data running state data when, the references object
Terminate simulation calculation, and the output data of the references object is stored into the target memory with preset format.
According to the preferred embodiment of the present invention, the output data packet that the references object is obtained by the verification platform
Include：
By the reference model module, the output file of the references object is detected in the target memory, with
Preset format reads the output data of the references object from the output file of the references object.
According to the preferred embodiment of the present invention, the output data according to the references object and the object to be tested it is defeated
Go out data, determining the result of the object to be tested includes：
When the output data of the references object is identical with the output data of the object to be tested, it is described to be tested right to determine
As being verified；And/or
When the output data of the references object and the output data of the object to be tested are differed, determine described to be tested
Banknote validation does not pass through.
According to the preferred embodiment of the present invention, the second language includes Python.
The checking device of a kind of Logic Circuit Design, it is characterised in that methods described includes：
Generation unit, for generating configuration data and excited data by verification platform；
Memory cell, for the configuration data and excited data to be stored to target memory；
Transmitting element, for being sent the configuration data and the excited data to be tested right by the verification platform
As；
Control unit, for by the verification platform control references object read from the target memory described in match somebody with somebody
Data and the excited data are put, so that the references object starts simulation calculation, the object to be tested is real with first language
The logic circuit code of existing algorithm, the references object is that the code of the algorithm is realized with second language；
Control unit, for controlling the references object to terminate simulation calculation by the verification platform；
Acquiring unit, the output data for obtaining the references object by the verification platform；
The acquiring unit is additionally operable to obtain the output data of the object to be tested by the verification platform；
Comparing unit, for the output data according to the references object and the output data of the object to be tested, it is determined that
The result of the object to be tested.
A kind of electronic equipment, the electronic equipment includes memory and processor, and the memory is used to store at least one
Individual instruction, the processor is used to perform at least one described instruction to realize the checking of Logic Circuit Design in any embodiment
In method.
A kind of computer-readable recording medium, the computer-readable recording medium storage has at least one instruction, described
The verification method of Logic Circuit Design, the authentication of the Logic Circuit Design are realized at least one instruction when being executed by processor
Method is included in any embodiment in the verification method of Logic Circuit Design.
As can be seen from the above technical solutions, the present invention generates configuration data and excited data by verification platform；By institute
State configuration data and excited data is stored to target memory；By the verification platform by the configuration data and the excitation
Data are sent to object to be tested；The references object is controlled to be read from the target memory by the verification platform described
Configuration data and the excited data, so that the references object starts simulation calculation；It is described by verification platform control
References object terminates simulation calculation；The output data of the references object is obtained by the verification platform；Pass through the checking
Platform obtains the output data of the object to be tested；According to the output of the output data of the references object and the object to be tested
Data, determine the result of the object to be tested.The present invention by the way that the verification platform is combined with the references object,
Because the references object and the object to be verified can realize the function of identical algorithms, therefore ensureing the references object
When identical with the input data of the object to be tested, by the output data and the object to be tested that judge the references object
The whether identical checking realized to the object to be tested of output data.Simultaneously the verification platform have good autgmentability,
Reusability.So as to avoid substantial amounts of coding work, the verification efficiency of Logic Circuit Design is improved.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
Fig. 1 is the system architecture diagram of the preferred embodiment of the verification method for realizing Logic Circuit Design of the present invention.
Fig. 2 is the flow chart of the preferred embodiment of the verification method of Logic Circuit Design of the present invention.
Fig. 3 is the functional block diagram of the preferred embodiment of the checking device of Logic Circuit Design of the present invention.
Fig. 4 is the structural representation of the preferred embodiment of electronic equipment at least one example of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
In order to facilitate the understanding of the purposes, features and advantages of the present invention, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is further detailed explanation.
As shown in figure 1, Fig. 1 is the system tray of the preferred embodiment of the verification method for realizing Logic Circuit Design of the present invention
Composition.In this preferred embodiment, the system architecture diagram includes, but are not limited to：Verification platform 1, passes through interface 1 and institute
State the references object 2 that verification platform 1 is communicated, and the object to be tested 3 communicated by interface 2 15 and the verification platform 1.
In this preferred embodiment, the verification platform 1 is generic validation methodology (Universal Verification
Methodology, UVM) verification platform 1.The UVM summarizes the conventional step of checking work and function, and there is provided a set of complete
The thinking and framework of whole checking hardware logic.In addition, UVM verification platforms additionally provide abundant class library module, it is only necessary to logical
Cross and extend these class library modules, organized according to the framework of the UVM verification platforms, you can complete building for verification platform 1.
Then emulated again by writing test case, complete the work of verifying logic code.The verification platform 1 has good
Autgmentability, reusability.It is therefore not necessary to directly test program be write with SystemVeilog, so as to avoid substantial amounts of coding work.
The verification platform 1 includes, but are not limited to：Data input module 13, reference model module 11, data outputting module
14 and data comparing module 12.The data input module 13, reference model module 11, data outputting module 14 and comparing
Module 12 is generic module, and it is different from the unit functional module (such as generation unit 100) shown in Fig. 3.The data are defeated
The function of entering module 13, reference model module 11, data outputting module 14 and data comparing module 12 will be in subsequent embodiment
It is described in detail.
In this preferred embodiment, the object 3 to be tested is realizing algorithm (such as intelligent algorithm) with first language
Logic circuit code, i.e. Logic Circuit Design.The references object 2 is the code for the algorithm realized with second language.Its
In, the first language is different from the second language.For example, the second language includes Python, it is described to be tested right
As 3 being the logic circuit based on the Verilog algorithms write.The references object 2 is realized using Python
The code of the algorithm.I.e. described references object 2 can realize the function of identical algorithms with the object 3 to be tested, realize algorithm
Programming language is different.
In this preferred embodiment, the interface 1 is the system function of programming language.For example, Verilog, Python
Deng the system function of programming language, the interface 2 15 is the interface of emulator, such as SystemVerilog interface
Interface.Wherein, Python can be very good to support scientific calculation, be adapted to the various mathematical modelings of processing and computing, no
Need to use circulation just can perform operation to list element, to the operation of matrix such as scalar, substantially increase operational efficiency.
In this preferred embodiment, generation configuration data and excitation number that the electronic equipment passes through the verification platform 1
According to, and sent the configuration data and the excited data to object 3 to be tested by the verification platform 1, it is described to be tested right
Start simulation calculation according to the configuration data configuration operation environment, and according to the excited data as 3, when simulation calculation terminates
Afterwards, the output data of the object to be tested 3 is obtained by the verification platform 1.
The configuration data and excited data are stored to target and stored by the electronic equipment by the verification platform 1
Device, controls the references object 2 to read the configuration data from the target memory and described by the verification platform 1
Excited data, the references object 2 is obtained after the configuration data, according to the configuration data configuration operation environment, and according to
The excited data starts simulation calculation, after simulation calculation terminates, and the references object 2 is obtained by the verification platform 1
Output data.When the output data of the references object 2 is identical with the output data of the object 3 to be tested, it is determined that described
Object 3 to be tested is verified；When the output data of the references object 2 and the output data of the object 3 to be tested are differed,
Determine that the object to be tested 3 is verified not pass through.
As shown in Fig. 2 being the flow chart of the preferred embodiment of the verification method of Logic Circuit Design of the present invention.According to difference
Demand, the order of step can change in the flow chart, and some steps can be omitted.
S10, the electronic equipment generates configuration data and excited data by verification platform 1；
Wherein, the verification platform 1 can include data generating function or data generation generic module.By calling described test
Demonstrate,prove the data generating function or data generation generic module generation configuration data and excited data of platform 1.
In a preferred embodiment, the configuration data includes, but not limited to following one or more：The checking is flat
The configuration data of platform 1, the configuration data of object to be tested 3, the configuration data of references object 2, wherein the configuration of the verification platform 1
Data are used for initializing verification environment, test pattern etc..The configuration data of the object to be tested 3 is mainly used to treat described in initialization
Object 3 is tested, mode of operation etc. is set.At the beginning of the configuration data of the object to be tested 3 includes, but not limited to register configuration, interface
The configuration of beginning state, mode of operation configuration etc..The configuration data of the references object 2 is mainly used to initialize the references object 2,
Mode of operation etc. is set, and it includes, but not limited to register configuration, the configuration of interface original state, mode of operation configuration etc..Institute
Random excited data can also be produced by stating verification platform 1, for being used as algorithm in the object 3 to be tested and the references object 2
Input data, the excited data includes, but not limited to clock, reset, input data etc..Therefore, because to the parameter
Object 2 and the configuration data and excited data of the object to be tested 3 input are identical, then the parameter object 2 and described to be tested right
As 3 input data is identical.
S11, the electronic equipment stores the configuration data and excited data to target memory.
In a preferred embodiment, the target memory can be at least one memory of the electronic equipment, also may be used
To be at least one external memory storage being connected with the electronic equipment.
In a preferred embodiment, the electronic equipment is by the verification platform 1, with preset format by the configuration data
And excited data preserves into text document, and store to the target memory, so that the references object 2 can be with preset format
The text document is parsed, and reads the configuration data and excited data.This ensures that the references object 2 with it is described
The input data of object 3 to be tested it is identical, it is ensured that the correctness of result of calculation.
The text document includes the combination of one or more of：Plain text document, binary documents, JavaScript
Object Markup Language document.
Preferably, the preset format is pre-configured with, is included, but are not limited to：It is pre-configured with text document per a line
Storage content, such as start information, ending message per a line etc..
S12, the electronic equipment is sent the configuration data and the excited data to treating by the verification platform 1
Test object 3.
In a preferred embodiment, by the data input module 13, and the interface 2 15 is utilized by the configuration number
According to and the excited data send to the object 3 to be tested.The object to be tested 3 is according to the configuration data configuration operation ring
Border, and according to the excited data, start simulation calculating, then output data.
S13, the electronic equipment controls the references object 2 from the target memory by the verification platform 1
The configuration data and the excited data are read, so that the references object 2 starts simulation calculation.
In a preferred embodiment, the verification platform 1 can include the generic module of Process flowchart function or Process flowchart.It is logical
The generic module generation for crossing the generation control function for calling the verification platform 1 or Process flowchart controls entering for the references object 2
Journey.
In a preferred embodiment, when the verification platform 1 starts, generation controls the process of the references object 2 to open
Move the references object 2, and make the configuration data that the references object 2 detects that the verification platform 1 generates and described swash
Encourage data.
After the references object 2 starts, storage can persistently be detected in the target memory by built-in function
The configuration data and the excited data text document, and the text document is solved with the preset format
Analysis, reads the configuration data and the excited data to start simulation calculation.
S14, the electronic equipment controls the references object 2 to terminate simulation calculation by the verification platform 1.
In a preferred embodiment, it is described to control the references object 2 to terminate simulation calculation bag by the verification platform 1
Include：Obtain the running state data of the verification platform 1；The running state data is stored to described with the preset format
So that the references object 2 is detected in target memory, when the references object 2 is detected including done state data
During running state data, the references object 2 terminates simulation calculation, and by the output data of the references object 2 with default lattice
Formula is stored into the target memory.
S15, the electronic equipment obtains the output data of the references object 2 by the verification platform 1.
In a preferred embodiment, the electronic equipment is by the reference model module 11, in the target memory
The output file of the references object 2 is detected, the reference is read from the output file of the references object 2 with preset format
The output data of object 2, and the output data of the references object 2 is sent to the data comparing module 12.
S16, the electronic equipment obtains the output data of the object to be tested 3 by the verification platform 1.
In a preferred embodiment, the electronic equipment obtains the object to be tested 3 by the data outputting module 14
Output data, and the output data of the object 3 to be tested is sent to the data comparing module 12.
S17, the electronic equipment according to the output data of the references object 2 and the output data of the object to be tested 3,
Determine the result of the object to be tested 3.
In a preferred embodiment, the electronic equipment is by the data comparing module, according to the defeated of the references object 2
Go out the output data of data and the object to be tested 3, determine the result of the object to be tested 3.
When the output data of the references object 2 is identical with the output data of the object 3 to be tested, determine described to be tested
Object 3 is verified.The logic circuit code of i.e. described object to be tested 3 is correct, can realize represented in the references object 2
Algorithm.
When the output data of the references object 2 and the output data of the object 3 to be tested are differed, it is determined that described treat
Test object 3 and verify and do not pass through.The logic circuit code of i.e. described object to be tested 3 is incorrect, it is impossible to realize in the references object 2
Represented algorithm is, it is necessary to remind the logic circuit code of developer's inspection object 3 to be tested.
The present invention generates configuration data and excited data by verification platform 1；The configuration data and excited data are deposited
Store up to target memory；The configuration data and the excited data are sent to object 3 to be tested by the verification platform 1；
The references object 2 is controlled to read the configuration data from the target memory and described sharp by the verification platform 1
Data are encouraged, so that the references object 2 starts simulation calculation；The references object 2 is controlled to terminate by the verification platform 1 imitative
It is true to calculate；The output data of the references object 2 is obtained by the verification platform 1；Obtain described by the verification platform 1
The output data of object 3 to be tested；According to the output data of the references object 2 and the output data of the object to be tested 3, it is determined that
The result of the object to be tested 3.The verification platform 1 is combined by the present invention with the references object 2, due to the ginseng
Identical algorithms, and the input number of the references object 2 and the object to be tested 3 can be realized by examining object 2 and the object 3 to be tested
According to identical, thus by determine the references object 2 output data and the object to be tested 3 output data it is whether identical i.e.
It can determine that the correctness of the object to be tested 3.The output data of i.e. described object to be tested 3 and the output number of the references object 2
According to identical, then the object to be tested is correct (Logic Circuit Design is correct).If the output data of the object to be tested 3 and the ginseng
The output data for examining object 2 is differed, then the object mistake to be tested (Logic Circuit Design mistake).Meanwhile, the checking is flat
Platform 1 has good autgmentability, reusability.Without directly writing test program with SystemVeilog, so as to avoid substantial amounts of
Coding work, improves the verification efficiency of Logic Circuit Design.
As shown in figure 3, the functional block diagram of the preferred embodiment of the checking device of Logic Circuit Design of the present invention.It is described to patrol
The checking device 16 of volume circuit design includes generation unit 100, memory cell 101, transmitting element 102, control unit 103, obtained
Take unit 104 and comparing unit 105.Unit alleged by the present invention refer to it is a kind of can be by the checking device 16 of Logic Circuit Design
Processor it is performed and the series of computation machine program segment of fixing function can be completed, it is stored in memory.At this
In embodiment, the function on each unit will be described in detail in follow-up embodiment.
The generation unit 100 generates configuration data and excited data by verification platform 1.
In a preferred embodiment, the verification platform 1 can include data generating function or data generation generic module.Pass through
Call the data generating function or data generation generic module generation configuration data and excited data of the verification platform 1.
In a preferred embodiment, the generation unit 100 generates configuration data and excitation number by verification platform 1 at random
According to.The configuration data includes, but not limited to following one or more：It is the configuration data of the verification platform 1, to be tested right
Configuration data, the configuration data of references object 2 as 3, wherein the configuration data of the verification platform 1 is used for initializing checking ring
Border, test pattern etc..The configuration data of the object to be tested 3 is mainly used to initialize the object to be tested 3, sets mode of operation
Deng.The configuration data of the object to be tested 3 includes, but not limited to register configuration, the configuration of interface original state, mode of operation
Configuration etc..The configuration data of the references object 2 is mainly used to initialize the references object 2, sets mode of operation etc., and it is wrapped
Include, but be not limited to, register configuration, the configuration of interface original state, mode of operation configuration etc..The generation unit 100 also passes through
Verification platform 1 produces random excited data, for as in the object 3 to be tested and the references object 2 algorithm it is defeated
Enter data, the excited data includes, but not limited to clock, reset, input data etc..Therefore, because to the parameter object
2 and the object to be tested 3 input configuration data and excited data it is identical, then the parameter object 2 and the object to be tested 3
Input data is identical.
The memory cell 101 stores the configuration data and excited data to target memory.
In a preferred embodiment, the target memory can be at least one memory of the electronic equipment, also may be used
To be at least one external memory storage being connected with the electronic equipment.
In a preferred embodiment, the memory cell 101 is by the verification platform 1, with preset format by the configuration
Data and excited data preserve into text document, and store to the target memory, so that the references object 2 can be with default
Text document described in format analysis, and read the configuration data and excited data.This ensures that the references object 2 with
The input data of the object to be tested 3 it is identical, it is ensured that the correctness of result of calculation.
The text document includes the combination of one or more of：Plain text document, binary documents, JavaScript
Object Markup Language document.
Preferably, the preset format is pre-configured with, is included, but are not limited to：It is pre-configured with text document per a line
Storage content, such as start information, ending message per a line etc..
The transmitting element 102 is sent the configuration data and the excited data to treating by the verification platform 1
Test object 3.
In a preferred embodiment, the transmitting element 102 is by the data input module 13, and utilizes the interface two
15 send the configuration data and the excited data to the object 3 to be tested.The object to be tested 3 is according to the configuration number
According to configuration operation environment, and according to the excited data, start simulation calculating, then output data.
Described control unit 103 controls the references object 2 to be read from the target memory by the verification platform 1
The configuration data and the excited data are taken, so that the references object 2 starts simulation calculation.
In a preferred embodiment, the verification platform 1 can include the generic module of Process flowchart function or Process flowchart.It is logical
The generic module generation for crossing the generation control function for calling the verification platform 1 or Process flowchart controls entering for the references object 2
Journey.
In a preferred embodiment, when the verification platform 1 starts, the generation control of control unit 103 references object 2
Process to start the references object 2, and the references object 2 is detected the configuration number that the verification platform 1 is generated
According to and the excited data.
After the references object 2 starts, storage can persistently be detected in the target memory by built-in function
The configuration data and the excited data text document, and the text document is solved with the preset format
Analysis, reads the configuration data and the excited data to start simulation calculation.
Described control unit 103 controls the references object 2 to terminate simulation calculation by the verification platform 1.
In a preferred embodiment, described control unit 103 controls the references object 2 to terminate by the verification platform 1
Simulation calculation includes：Obtain the running state data of the verification platform 1；By the running state data with the preset format
Store into the target memory so that the references object 2 is detected, when the references object 2 is detected including terminating
During the running state data of status data, the references object 2 terminates simulation calculation, and by the defeated of the references object 2
Go out data to store into the target memory with preset format.
The acquiring unit 104 obtains the output data of the references object 2 by the verification platform 1.
In a preferred embodiment, the acquiring unit 104 is by the reference model module 11, in the target memory
The output file of the middle detection references object 2, the ginseng is read with preset format from the output file of the references object 2
The output data of object 2 is examined, and the output data of the references object 2 is sent to the data comparing module 12.
The acquiring unit 104 obtains the output data of the object to be tested 3 by the verification platform 1.
In a preferred embodiment, the acquiring unit 104 obtains the object to be tested 3 by the data outputting module 14
Output data, and the output data of the object 3 to be tested is sent to the data comparing module 12.
The comparing unit 105 according to the output data of the references object 2 and the output data of the object to be tested 3,
Determine the result of the object to be tested 3.
In a preferred embodiment, the comparing unit 105 is by the data comparing module 12, according to the references object
The output data of 2 output data and the object to be tested 3, determines the result of the object to be tested 3.
When the output data of the references object 2 is identical with the output data of the object 3 to be tested, determine described to be tested
Object 3 is verified.The logic circuit code of i.e. described object to be tested 3 is correct, can realize represented in the references object 2
Algorithm.
When the output data of the references object 2 and the output data of the object 3 to be tested are differed, it is determined that described treat
Test object 3 and verify and do not pass through.The logic circuit code of i.e. described object to be tested 3 is incorrect, it is impossible to realize in the references object 2
Represented algorithm is, it is necessary to remind the logic circuit code of developer's inspection object 3 to be tested.
The present invention generates configuration data and excited data by verification platform 1；The configuration data and excited data are deposited
Store up to target memory；The configuration data and the excited data are sent to object 3 to be tested by the verification platform 1；
The references object 2 is controlled to read the configuration data from the target memory and described sharp by the verification platform 1
Data are encouraged, so that the references object 2 starts simulation calculation；The references object 2 is controlled to terminate by the verification platform 1 imitative
It is true to calculate；The output data of the references object 2 is obtained by the verification platform 1；Obtain described by the verification platform 1
The output data of object 3 to be tested；According to the output data of the references object 2 and the output data of the object to be tested 3, it is determined that
The result of the object to be tested 3.The verification platform 1 is combined by the present invention with the references object 2, due to the ginseng
Identical algorithms, and the input number of the references object 2 and the object to be tested 3 can be realized by examining object 2 and the object 3 to be tested
According to identical, thus by determine the references object 2 output data and the object to be tested 3 output data it is whether identical i.e.
The checking (correctness for determining the object to be tested 3) to the object 3 to be tested can be achieved.The output of i.e. described object to be tested 3
Data are identical with the output data of the references object 2, then the object to be tested is correct (Logic Circuit Design is correct).If described
The output data of the output data of object 3 to be tested and the references object 2 is differed, then object mistake to be tested (the logic electricity
Road design mistake).Meanwhile, the verification platform 1 has good autgmentability, reusability.Without directly using SystemVeilog
Test program is write, so as to avoid substantial amounts of coding work, the verification efficiency of Logic Circuit Design is improved.
The above-mentioned integrated unit realized in the form of software function module, can be stored in an embodied on computer readable and deposit
In storage media.Above-mentioned software function module is stored in a storage medium, including some instructions are to cause a computer
It is each that equipment (can be personal computer, server, or network equipment etc.) or processor (processor) perform the present invention
The part steps of embodiment methods described.
As shown in figure 4, the electronic equipment 4 includes at least one dispensing device 31, at least one memory 32, at least one
Individual processor 33, at least one reception device 34, at least one display (not shown) and at least one communication bus.
Wherein, the communication bus is used to realize the connection communication between these components.
The electronic equipment 4 be it is a kind of can according to the instruction for being previously set or storing, it is automatic carry out numerical computations and/or
The equipment of information processing, its hardware includes but is not limited to microprocessor, application specific integrated circuit (Application Specific
Integrated Circuit, ASIC), programmable gate array (Field-Programmable Gate Array, FPGA), number
Word processing device (Digital Signal Processor, DSP), embedded device etc..The electronic equipment 4 may also include network
Equipment and/or user equipment.Wherein, the network equipment includes but is not limited to single network server, multiple webservers
The server group of composition or the cloud being made up of a large amount of main frames or the webserver based on cloud computing (Cloud Computing),
Wherein, cloud computing is one kind of Distributed Calculation, a super virtual computing being made up of the computer collection of a group loose couplings
Machine.
The electronic equipment 4, which may be, but not limited to, any one, to pass through keyboard, touch pad or voice-operated device with user
Etc. the electronic product that mode carries out man-machine interaction, for example, tablet personal computer, smart mobile phone, personal digital assistant (Personal
Digital Assistant, PDA), intellectual Wearable, picture pick-up device, the terminal such as monitoring device.
Network residing for the electronic equipment 4 includes, but are not limited to internet, wide area network, Metropolitan Area Network (MAN), LAN, virtual
Dedicated network (Virtual Private Network, VPN) etc..
Wherein, the reception device 34 and the dispensing device 31 can be wired sending ports, or wirelessly set
It is standby, such as including antenna assembly, for entering row data communication with other equipment.
The memory 32 is used for store program codes.The memory 32 can not have physical form in integrated circuit
The circuit with store function, such as RAM (Random-Access Memory, random access memory), FIFO (First In
First Out) etc..Or, the memory 32 can also be the memory with physical form, such as memory bar, TF cards
(Trans-flash Card), smart media card (smart media card), safe digital card (secure digital
Card), storage facilities such as flash memory cards (flash card) etc..
The processor 33 can include one or more microprocessor, digital processing unit.The processor 33 is adjustable
With the program code stored in memory 32 with perform correlation function.For example, the unit described in Fig. 3 is stored in institute
The program code in memory 32 is stated, and as performed by the processor 33, to realize a kind of authentication of Logic Circuit Design
Method.The processor 33 is also known as central processing unit (CPU, Central Processing Unit), is one piece of ultra-large collection
It is arithmetic core (Core) and control core (Control Unit) into circuit.
The embodiment of the present invention also provides a kind of computer-readable recording medium, is stored thereon with computer instruction, the finger
Make when the electronic equipment for being included one or more processors is performed, electronic equipment is performed as described in embodiment of the method above
Logic Circuit Design verification method.
In several embodiments provided by the present invention, it should be understood that disclosed system, apparatus and method can be with
Realize by another way.For example, device embodiment described above is only schematical, for example, the module
Divide, only a kind of division of logic function there can be other dividing mode when actually realizing.
The module illustrated as separating component can be or may not be it is physically separate, it is aobvious as module
The part shown can be or may not be physical location, you can with positioned at a place, or can also be distributed to multiple
On NE.Some or all of module therein can be selected to realize the mesh of this embodiment scheme according to the actual needs
's.
In addition, each functional module in each embodiment of the invention can be integrated in a processing unit, can also
That each unit is individually physically present, can also two or more units it is integrated in a unit.Above-mentioned integrated list
Member can both be realized in the form of hardware, it would however also be possible to employ hardware adds the form of software function module to realize.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie
In the case of without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, embodiment all should be regarded as exemplary, and be nonrestrictive, the scope of the present invention is by appended power
Profit is required rather than described above is limited, it is intended that all in the implication and scope of the equivalency of claim by falling
Change is included in the present invention.The right that any attached associated diagram mark in claim should not be considered as involved by limitation will
Ask.Furthermore, it is to be understood that the word of " comprising " one is not excluded for other units or step, odd number is not excluded for plural number.Stated in system claims
Multiple units or device can also be realized by a unit or device by software or hardware.Second grade word is used for table
Show title, and be not offered as any specific order.
Finally it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention and it is unrestricted, although reference
The present invention is described in detail for preferred embodiment, it will be understood by those within the art that, can be to the present invention's
Technical scheme is modified or equivalent substitution, without departing from the spirit and scope of technical solution of the present invention.
Claims (10)
1. a kind of verification method of Logic Circuit Design, it is characterised in that methods described includes：
Configuration data and excited data are generated by verification platform；
The configuration data and excited data are stored to target memory；
The configuration data and the excited data are sent to object to be tested by the verification platform；
References object is controlled to read the configuration data and the excitation from the target memory by the verification platform
Data, so that the references object starts simulation calculation, the object to be tested is the logic circuit that algorithm is realized with first language
Code, the references object is that the code of the algorithm is realized with second language, and the first language and the second language are not
Together；
The references object is controlled to terminate simulation calculation by the verification platform；
The output data of the references object is obtained by the verification platform；
The output data of the object to be tested is obtained by the verification platform；
According to the output data of the references object and the output data of the object to be tested, the checking of the object to be tested is determined
As a result.
2. the verification method of Logic Circuit Design as claimed in claim 1, it is characterised in that it is described by the configuration data and
Excited data, which is stored to target memory, to be included：
The configuration data and excited data are preserved into by text document with preset format, and stored to the target memory,
The text document includes the combination of one or more of：Plain text document, binary documents, JavaScript object mark
Language Document.
3. the verification method of Logic Circuit Design as claimed in claim 1, it is characterised in that the verification platform passes through interface
One is communicated with the references object, is communicated by interface two with the object to be tested, the verification platform includes：Number
According to input module, reference model module, data outputting module and data comparing module；The data input module is used for will be described
Configuration data and the excited data are sent to object to be tested；The data outputting module is used to obtain the defeated of the object to be tested
Go out data, the reference model module is used for the output data for obtaining the references object, and the data comparing module is used for root
According to the output data and the output data of the object to be tested of the references object, the result of the object to be tested is determined.
4. the verification method of Logic Circuit Design as claimed in claim 1, it is characterised in that described to pass through the verification platform
The references object is controlled to read the configuration data and the excited data from the target memory, so that the reference
Object, which starts simulation calculation, to be included：
When the verification platform starts, the process of the generation control references object makes institute to start the references object
State the text document that references object detection stores the configuration data and the excited data；And/or
It is described to control the references object to terminate simulation calculation by the verification platform to include：
Obtain the running state data of the verification platform；The running state data is stored to the target with preset format
So that the references object carries out detection done state data in memory；
When the references object detect it is described include done state data running state data when, the references object terminates
Simulation calculation, and the output data of the references object is stored into the target memory with preset format.
5. the verification method of Logic Circuit Design as claimed in claim 3, it is characterised in that described to pass through the verification platform
Obtaining the output data of the references object includes：
By the reference model module, the output file of the references object is detected in the target memory, with default
Form reads the output data of the references object from the output file of the references object.
6. the verification method of Logic Circuit Design as claimed in claim 1, it is characterised in that described according to the references object
Output data and the object to be tested output data, determining the result of the object to be tested includes：
When the output data of the references object is identical with the output data of the object to be tested, determine that the object to be tested is tested
Card passes through；And/or
When the output data of the references object and the output data of the object to be tested are differed, the object to be tested is determined
Checking does not pass through.
7. the verification method of the Logic Circuit Design as any one of claim 1 to 6, it is characterised in that described second
Language includes Python.
8. the checking device of a kind of Logic Circuit Design, it is characterised in that methods described includes：
Generation unit, for generating configuration data and excited data by verification platform；
Memory cell, for the configuration data and excited data to be stored to target memory；
Transmitting element, for being sent the configuration data and the excited data to object to be tested by the verification platform；
Control unit, for controlling references object to read the configuration number from the target memory by the verification platform
According to and the excited data so that the references object starts simulation calculation, the object to be tested is to be realized to calculate with first language
The logic circuit code of method, the references object is that the code of the algorithm is realized with second language；
Control unit, for controlling the references object to terminate simulation calculation by the verification platform；
Acquiring unit, the output data for obtaining the references object by the verification platform；
The acquiring unit is additionally operable to obtain the output data of the object to be tested by the verification platform；
Comparing unit, for the output data according to the references object and the output data of the object to be tested, it is determined that described
The result of object to be tested.
9. a kind of electronic equipment, it is characterised in that the electronic equipment includes memory and processor, the memory is used to deposit
At least one instruction is stored up, the processor is used to perform at least one described instruction to realize that claim 1 to 7 any one is patrolled
In the verification method for collecting circuit design.
10. a kind of computer-readable recording medium, it is characterised in that the computer-readable recording medium storage has at least one
The verification method of Logic Circuit Design is realized in instruction, at least one described instruction when being executed by processor, the logic circuit is set
The verification method of meter is included in the verification method of claim 1 to 7 any one Logic Circuit Design.
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