CN107239348A - A kind of polycaryon processor dispatching method, device and mobile terminal - Google Patents
A kind of polycaryon processor dispatching method, device and mobile terminal Download PDFInfo
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- CN107239348A CN107239348A CN201710486456.7A CN201710486456A CN107239348A CN 107239348 A CN107239348 A CN 107239348A CN 201710486456 A CN201710486456 A CN 201710486456A CN 107239348 A CN107239348 A CN 107239348A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
Abstract
The invention discloses a kind of polycaryon processor dispatching method, perform in the terminal, this method includes：Every predetermined interval, the minimum utilization rate of processor is obtained, minimum utilization rate is the minimum value of the utilization rate of in running order each core；When minimum utilization rate is more than or equal to first threshold, judge currently to whether there is idle cores；If there are idle cores, an idle cores are opened, and are intermediate frequency by its clock set of frequency；If in the absence of idle cores, judging whether minimum utilization rate is more than or equal to Second Threshold, wherein, Second Threshold is more than first threshold；When minimum utilization rate is more than or equal to Second Threshold, a clock frequency less than frequency core is heightened, wherein, it is the core that clock frequency is less than peak frequency less than frequency core.In addition, the invention also discloses the polycaryon processor dispatching device that can implement the above method, and the mobile terminal including said apparatus.
Description
Technical field
The present invention relates to communication technical field, more particularly to a kind of polycaryon processor dispatching method, device and mobile terminal.
Background technology
With the development of mobile communication technology, the processor (CPU, Central Processing Unit) of mobile terminal
Upgrade to multinuclear (such as double-core, four cores, eight cores) from monokaryon, so as to be provided for larger application of the expenses such as video, game etc.
More preferable service condition.
At present, regulated and controled more than the working condition of mobile terminal multi-core CPU using list of application, i.e. will apply according to CPU overhead
Sort out, the working condition of multi-core CPU is adjusted according to the applicating category currently run.If for example, being run in current mobile terminal
The expense larger applications such as game, video, then set CPU to work in the state of multinuclear, high frequency；If it is current run it is social,
The less application of the expenses such as information, then set CPU to work in the state of few core, low frequency.But, this regulation and control method be it is narrow and
Machinery, it can not be applied to all application scenarios.In addition, in fact, simultaneously the game of not all, Video Applications necessarily take
More cpu resource, nor all social activities, information application necessarily take less cpu resource.Above-mentioned regulation and control method still may be used
The situation that cpu resource is not enough or wastes can occurs, when cpu resource is not enough, it is impossible to meet the demand of current application；Work as CPU
During resource excess, the practical efficiency of cpu resource is reduced, has increased power consumption on foot.
The content of the invention
Therefore, the present invention provides a kind of polycaryon processor dispatching method, device and mobile terminal, to solve or at least alleviate
The problem of existing above.
According to an aspect of the present invention there is provided a kind of polycaryon processor dispatching method, perform in the terminal, the party
Method includes：Every predetermined interval, the minimum utilization rate of processor is obtained, minimum utilization rate is in running order each core
The minimum value of the utilization rate of the heart；When minimum utilization rate is more than or equal to first threshold, judge currently to whether there is idle cores；If
There are idle cores, then open an idle cores, and be intermediate frequency by its clock set of frequency；If in the absence of idle core
The heart, then judge whether minimum utilization rate is more than or equal to Second Threshold, wherein, Second Threshold is more than first threshold；When minimum is used
When rate is more than or equal to Second Threshold, a clock frequency less than frequency core is heightened, wherein, it is that clock frequency is small less than frequency core
In the core of peak frequency.
Alternatively, in the polycaryon processor dispatching method according to the present invention, the minimum utilization rate of processor is being obtained
Before step, in addition to step：Obtain the quantity for the core for being currently at working condition；If currently only one core is in work
Make state, then obtain the utilization rate and clock frequency of the core；When the clock frequency of the core is equal to intermediate frequency, and utilization rate
During more than or equal to first threshold, an idle cores are opened, and are intermediate frequency by its clock set of frequency；When the core
When clock frequency is more than or equal to Second Threshold less than intermediate frequency, and utilization rate, the clock frequency of the core is set to middle frequency
Rate.
Alternatively, in the polycaryon processor dispatching method according to the present invention, the step of opening an idle cores includes：
Open the minimum idle cores of numbering；The step of heightening a clock frequency less than frequency core includes：Heighten numbering minimum
Less than the clock frequency of frequency core.
Alternatively, in the polycaryon processor dispatching method according to the present invention, intermediate frequency is the frequency of processor core
With the immediate clock frequency of half of peak frequency in list.
Alternatively, in the polycaryon processor dispatching method according to the present invention, when all cores are in working condition, and
When minimum utilization rate is less than three threshold values, the clock frequency of a core is turned down；Wherein, the 3rd threshold value is less than Second Threshold.
Alternatively, in the polycaryon processor dispatching method according to the present invention, the step of the clock frequency of a core is turned down
Suddenly include：Turn down the clock frequency of the largest number of core.
Alternatively, in the polycaryon processor dispatching method according to the present invention, first threshold is 60%, and Second Threshold is
90%, the 3rd threshold value is 80%.
Alternatively, in the polycaryon processor dispatching method according to the present invention, in addition to step：When the use of a core
When rate is 0, the core is closed.
Alternatively, in the polycaryon processor dispatching method according to the present invention, when scheduling operation is one idle core of unlatching
The heart or when heightening a clock frequency less than frequency core, the first value is set to by predetermined interval；When scheduling operation is tune
During one core of clock frequency or closing of a low core, predetermined interval is set to second value；Wherein, the first value is small
In second value.
Alternatively, in the polycaryon processor dispatching method according to the present invention, the first value is 20ms, and second value is 80ms.
According to an aspect of the present invention there is provided a kind of polycaryon processor dispatching device, reside in mobile terminal, its quilt
It is configured and adapted to mobile terminal is performed polycaryon processor dispatching method as described above.
According to an aspect of the present invention there is provided a kind of mobile terminal, including：It is each in polycaryon processor, polycaryon processor
The working condition of core can be dispatched by programmed instruction；With the memory for the instruction that has program stored therein, described program instruction includes
Polycaryon processor dispatching device as described above so that mobile terminal can perform polycaryon processor dispatching party as described above
Method.
According to an aspect of the present invention there is provided a kind of readable storage medium storing program for executing for the instruction that has program stored therein, deposited when this is readable
When the programmed instruction stored in storage media is read by the mobile terminal so that the mobile terminal performs polycaryon processor as described above
Dispatching method.
Technique according to the invention scheme, can according to the utilization rate (utilization rate can reflect loading condition) of each core from
Adaptively adjust the quantity of in running order core and the clock frequency of each core.
When processor resource is unsatisfactory for the demand of current application, triggering rises core, raising frequency mechanism：When the minimum of processor makes
When being more than or equal to first threshold with rate and there are idle cores, an idle cores are newly opened；When minimum utilization rate is more than or equal to
Second Threshold and in the absence of idle cores when, heighten a clock frequency less than frequency core.Above-mentioned first threshold is less than second
Threshold value, so, technical scheme first rise core, again raising frequency, so that processor equivalent to when processor resource is not enough
Resource can match with application demand, it is ensured that fluency during application operation, while avoiding increasing too many power consumption, save electricity
Amount.
When processor resource is superfluous, triggering frequency reducing, drop core mechanism：When all cores are in working condition, and minimum
When utilization rate is less than three threshold values, the clock frequency of a core is reduced.When the utilization rate of some core is 0, the core is closed
The heart, wherein, the 3rd threshold value is less than Second Threshold.So, technical scheme is first equivalent to when processor resource is superfluous
Frequency reducing, drop core again, close unnecessary processor resource, improve the practical efficiency of processor resource, reduce power consumption, save electricity
Amount.
In addition, the polycaryon processor scheduling scheme of the present invention is lasting progress, i.e. every predetermined interval, obtain
The utilization rate of each core of processor, the quantity and each core of in running order core are adjusted according to the utilization rate of each core
The clock frequency of the heart.Especially, when scheduling operation is rises core or raising frequency, predetermined interval is set to the first value, works as tune
When degree operation is frequency reducing or drop core, predetermined interval is set to second value, wherein, the first value is less than second value.So, originally
Invention can realize it is quick rise core/raising frequency, frequency reducing/drop core at a slow speed, it is ensured that fluency during application operation, it is to avoid system card
, while reducing power consumption, save electricity.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of specification, and in order to allow above and other objects of the present invention, feature and advantage can
Become apparent, below especially exemplified by the embodiment of the present invention.
Brief description of the drawings
In order to realize above-mentioned and related purpose, some illustrative sides are described herein in conjunction with following description and accompanying drawing
Face, these aspects indicate the various modes of principles disclosed herein that can put into practice, and all aspects and its equivalent aspect
It is intended to fall under in the range of theme claimed.The following detailed description by being read in conjunction with the figure, the disclosure it is above-mentioned
And other purposes, feature and advantage will be apparent.Throughout the disclosure, identical reference generally refers to identical
Part or element.
Fig. 1 shows the structure chart of mobile terminal 1 00 according to an embodiment of the invention；
Fig. 2 shows the flow chart of polycaryon processor dispatching method 200 according to an embodiment of the invention；
Fig. 3 shows the schematic diagram of polycaryon processor scheduling process according to an embodiment of the invention.
Embodiment
The exemplary embodiment of the disclosure is more fully described below with reference to accompanying drawings.Although showing the disclosure in accompanying drawing
Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here
Limited.On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be by the scope of the present disclosure
Complete conveys to those skilled in the art.
Fig. 1 shows the structure chart of mobile terminal 1 00 according to an embodiment of the invention.As shown in figure 1, mobile terminal
100 can include memory interface 102, polycaryon processor 104, and peripheral interface 106.
Memory interface 102, polycaryon processor 104 and/or peripheral interface 106 both can be discrete components, can also collect
Into in one or more integrated circuits.In the mobile terminal 100, various elements can by one or more communication bus or
Signal wire is coupled.Sensor, equipment and subsystem may be coupled to peripheral interface 106, to help to realize a variety of functions.
For example, acceleration transducer 110, magnetic field sensor 112 and gravity sensor 114 may be coupled to peripheral interface
106, acceleration transducer 110 can gather the acceleration information on three change in coordinate axis direction of fuselage coordinates system, and magnetic field is passed
Sensor 112 can gather the magnetic field data (magnetic induction intensity) on three change in coordinate axis direction of fuselage coordinates system, gravity sensitive
Device 114 can gather the gravimetric data in three reference axis of fuselage coordinates system, above sensor can conveniently realize meter step,
The functions such as orientation, horizontal/vertical screen intelligence switching.Other sensors 116 can equally be connected with peripheral interface 106, such as alignment system
(such as GPS), temperature sensor, biometric sensor or other sensor devices, it is possible thereby to help to implement correlation
Function.
Camera sub-system 120 and optical sensor 122 can be used for the camera of convenient such as recording photograph and video clipping
The realization of function, wherein the camera sub-system and optical sensor for example can be charge coupling device (CCD) or complementary gold
Belong to oxide semiconductor (CMOS) optical sensor.It can help to realize by one or more radio communication subsystems 124
Communication function, wherein radio communication subsystem can include radio-frequency transmitter and emitter and/or light (such as infrared) receiver
And emitter.The particular design and embodiment of radio communication subsystem 124 can depend on mobile terminal 1 00 is supported one
Individual or multiple communication networks.For example, mobile terminal 1 00 can include be designed to support LTE, 3G, GSM network, GPRS network,
The communication subsystem 124 of EDGE network, Wi-Fi or WiMax network and BlueboothTM networks.
Audio subsystem 126 can be coupled with loudspeaker 128 and microphone 130, to help to implement to enable voice
Function, such as speech recognition, speech reproduction, digital record and telephony feature.I/O subsystems 140 can include touch-screen control
Device 142 processed and/or other one or more input controllers 144.Touch screen controller 142 may be coupled to touch-screen 146.Lift
For example, the touch-screen 146 and touch screen controller 142 can use any one of a variety of touch-sensing technologies to detect
The contact and movement or pause carried out therewith, wherein detection technology include but is not limited to capacitive character, resistive, infrared and table
Face technology of acoustic wave.Other one or more input controllers 144 may be coupled to other input/control devicess 148, such as one
Or the pointer device of multiple buttons, rocker switch, thumb wheel, infrared port, USB port, and/or instruction pen etc.It is described
One or more button (not shown)s can include the up/down for controlling loudspeaker 128 and/or the volume of microphone 130
Button.
Memory interface 102 can be coupled with memory 150.The memory 150 can include internal storage and outer
Portion's memory, internal storage for example can be static RAM (SRAM), nonvolatile memory (NVRAM)
Deng, but not limited to this；External memory storage is such as can be hard disk, mobile hard disk, USB flash disk, but not limited to this.Memory 150
It can be instructed with storage program, programmed instruction can for example include operating system 152 and apply 154.Operating system 152 for example can be with
It is Android, iOS, Windows Phone etc., it includes being used to handle basic system services and performing dependent on hardware
The programmed instruction of task.Memory 150 can also store and apply 154, can include being used to realize that various users expect using 154
Function programmed instruction.It can be independently of using 154 operating system offer or that operating system is carried.Separately
Outside, when being installed to using 154 in mobile terminal 1 00, drive module can also be added to operating system.In mobile device operation
When, operating system 152 can be loaded from memory 150, and performed by processor 104.Using 154 operationally, also can be from
Load, and performed by processor 104 in memory 150.Operated in using 154 on operating system, using operating system and
The interface that bottom hardware is provided realizes the desired function of various users, such as hardware management, instant messaging, web page browsing.
In above-mentioned various applications 154, a kind of application therein is the polycaryon processor dispatching device according to the present invention
160, it can obtain the utilization rate of each core in current polycaryon processor 104, at the dynamic adjustment of the utilization rate of each core
In the quantity and the clock frequency of each core of the core of working condition, the adaptive tune of each core in polycaryon processor 104 is realized
Degree, makes the application load demand in the computing resource and current mobile terminal that each core provided match, so as to improve many
The utilization ratio of core processor 104, it is ensured that fluency during application operation, while reducing power consumption, saves electricity.
Fig. 2 shows the flow chart of polycaryon processor dispatching method 200 according to an embodiment of the invention.Method 200
Suitable for being performed in the mobile terminal for being populated with polycaryon processor dispatching device 160.
As shown in Fig. 2 method 200 starts from step S210.
In step S210, every predetermined interval, the minimum utilization rate of processor is obtained.The minimum of processor is used
Rate is the minimum value of the utilization rate of in running order each core.For example, the core for being currently at working condition have CPU0,
CPU1, CPU2, the utilization rate of each core is respectively 80%, 75%, 70%, then, the minimum utilization rate above three of processor
The minimum value of utilization rate, i.e., 70%.It should be pointed out that in general, the utilization rate for the core opened recently is minimum, therefore, big
In most cases, step S210 is equivalent to obtain the utilization rate for the core opened recently.
Then, in step S220, judge whether minimum utilization rate is more than or equal to first threshold, if so, then performing step
S230；If it is not, not doing any operation then.It should be pointed out that the specific value of first threshold can be by those skilled in the art voluntarily
Set, for example, first threshold can be 60%, certainly, it can also be arranged to other numerical value, and the present invention is to first threshold
Specific value is not limited.
In step S230, judge currently to whether there is idle cores.Idle cores are to be not presently within working condition
Core.If so, then performing step S240；If it is not, then performing step S250.
In step S240, an idle cores are opened, and are intermediate frequency by its clock set of frequency.It should be pointed out that
The a certain moment there may be multiple idle cores.At this moment, according to a kind of embodiment, the minimum idle cores of numbering are opened, with side
Just the management of processor resource.For example, certain polycaryon processor includes four 0~CPU3 of core CPU, working condition is currently at
Core is CPU0 and CPU1, and CPU2 and CPU3 are idle cores, and minimum utilization rate is more than or equal to first threshold.At this moment, open
Minimum idle cores are numbered, that is, open CPU2.
According to a kind of embodiment, intermediate frequency is closest for the half in the list of frequency of processor core with peak frequency
Clock frequency, i.e. the clock frequency minimum with the absolute value of the difference of (peak frequency * 0.5).For example, CPU2 list of frequency
It is as shown in table 1 below.
Table 1.CPU2 list of frequencys
| Frequency level | Clock frequency (kHz) | Operating voltage (10^ (- 5) V) | Remarks |
| 1 | 1391000 | 105000 | Peak frequency |
| 2 | 1339000 | 104000 | |
| 3 | 1287000 | 102000 | |
| 4 | 1222000 | 100000 | |
| 5 | 1118000 | 95000 | |
| 6 | 1092000 | 95000 | |
| 7 | 949000 | 90000 | |
| 8 | 897000 | 89000 | |
| 9 | 806000 | 86000 | |
| 10 | 715000 | 83000 | Intermediate frequency |
| 11 | 624000 | 80000 | |
| 12 | 559000 | 79000 | |
| 13 | 481000 | 79000 | |
| 14 | 416000 | 79000 | |
| 15 | 338000 | 79000 | |
| 16 | 221000 | 78000 | Minimum frequency |
As shown in Table 1, CPU2 peak frequency is 1391000kHz, and the half of peak frequency is 695500kHz, in list
It is 715000kHz with the immediate clock frequencies of 695500kHz, therefore, CPU2 intermediate frequency is 715000kHz.Work as unlatching
During CPU2, CPU2 clock frequency is set to intermediate frequency 715000kHz.
It should be pointed out that the list of frequency of each core may be identical in polycaryon processor, it is also possible to different.Based on this, each core
Peak frequency, intermediate frequency, the minimum frequency of the heart are also not necessarily identical.
When in the absence of idle cores, step S250 is performed.In step s 250, judge whether minimum utilization rate is more than
In Second Threshold, if so, then performing step S260；If it is not, not performing any operation then.Herein, Second Threshold should be greater than foregoing
First threshold.Specifically, the value of Second Threshold can voluntarily be set by those skilled in the art.For example, Second Threshold can be with
It it was 90% (being more than pre-determined first threshold 60%), certainly, it can also be arranged to other numerical value, and the present invention is to Second Threshold
Specific value is not limited.
In step S260, a clock frequency less than frequency core is heightened.It is that clock frequency is less than most less than frequency core
The core of big frequency.It should be pointed out that a certain moment there may be it is multiple less than frequency core.At this moment, according to a kind of embodiment, heighten
Number the minimum clock frequency less than frequency core.In addition, according to a kind of embodiment, heightening the clock frequency less than frequency core
When, the clock frequency of the core can be heightened step by step according to frequency level listed in the list of frequency less than frequency core；
The clock frequency of the core can also be heightened every level；Directly the clock frequency of the core can also be heightened to peak frequency.Should
When pointing out, when performing step S260, the specific of clock frequency heightens rule and can voluntarily set by those skilled in the art, this
Invention is not limited to it.
For example, certain polycaryon processor includes four 0~CPU3 of core CPU, current four cores be in working condition and
Respective intermediate frequency (less than frequency) is worked in, minimum utilization rate is more than or equal to Second Threshold.At this moment, numbering is heightened minimum
The clock frequency less than frequency core, that is, heighten CPU0 clock frequency.Assuming that for example foregoing table 1 of CPU0 list of frequency, will
CPU0 heightens a supreme frequency level, i.e., CPU0 clock frequency is adjusted into 0.806GHz.
Step S210~S260 shows a process for according to the utilization rate of each core rise core, raising frequency.For place
Manage for device, there is below equation：
Processor performance=clock frequency * IPC (1)
Power consumption of processing unit ∝ electric capacity * voltage * voltage * clock frequencies (2)
In above-mentioned two formula, clock frequency is the clock periodicity of execution per second, IPC (Instruction Per
Cycle it is) the instruction number that completes in a clock cycle, symbol ∝ is represented " being proportional to ".
Based on above formula, in order to increase processor performance, clock frequency or IPC can be increased.And IPC and electric capacity are into just
Than, be also directly proportional to the quantity of processor core, clock frequency is directly proportional (reference can be made to table 1) to voltage, therefore, in fact, having
Power consumption of processing unit ∝ core amounts * clock frequencies3 (3)
Therefore, increase dominant frequency can increase power consumption with three cubed speed, and increase check figure can increase power consumption with linear velocity, because
This, when increasing processor performance, preferentially increases core amounts, when core amounts are expired, is further added by clock frequency, Ke Yi
While improving processor performance, power consumption increase must be unlikely to too many, i.e. save electric power while processor performance is improved.
In the method shown by step S210~S260, due to first threshold be less than Second Threshold, therefore this method equivalent to first rise core,
Raising frequency again, this is consistent with the principle shown by aforementioned formula (1)~(3), processor resource can be made to match with application demand,
Ensure fluency during application operation, while avoiding increasing too many power consumption, save electricity.
According to a kind of embodiment, before step S210, further comprising the steps of (not shown in Fig. 2) S201~S206：
Step S201：Obtain the quantity for the core for being currently at working condition.
Step S202：Judge whether the quantity for being currently at the core of working condition is equal to 1, if so, then performing step
S203；If it is not, then performing step S210.
Step S203：Judge whether that the clock frequency of the core is equal to intermediate frequency and utilization rate and is more than or equal to the first threshold
Value, if so, performing step S204；If it is not, performing step S205.
Step S204：An idle cores are opened, and are intermediate frequency by its clock set of frequency.Step S204 process
Identical with abovementioned steps S240, here is omitted.
Step S205：Judge whether that the clock frequency of the core is less than intermediate frequency and utilization rate and is more than or equal to the second threshold
Value, if so, performing step S206；If it is not, not performing any operation.
Step S206：The clock frequency of the core is set to intermediate frequency.
Above-mentioned steps S201~S206 is shown when current only one of which core is in running order, according to the core
Utilization rate and clock frequency carry out rising core, the process of raising frequency.Shown in step S201~S206 and abovementioned steps S210~S260
Method is slightly different, and its difference is, step S201~S206 needs first to be currently at unique core of working condition
Clock frequency is adjusted to intermediate frequency, then is performed such as step S210~S260 method, in this manner it is ensured that the core newly opened
The clock frequency of core with having turned on is consistent (being the intermediate frequency of each core), is conducive to the load of polycaryon processor equal
Weighing apparatus.
Step S201~S206 shown when current only one of which core is in running order, rise a core, raising frequency
Process；Step S210~S260 show it is current have two and the in running order above core when, rise a core, raising frequency
Process.According to a kind of embodiment, present invention additionally comprises frequency reducing, nuclear process drops, i.e.,：When all cores are in working condition, and
When minimum utilization rate is less than three threshold values, the clock frequency of a core is turned down.Wherein, the 3rd threshold value is less than foregoing second threshold
Value.It should be pointed out that the specific value of the 3rd threshold value can voluntarily be set by those skilled in the art, for example, the 3rd threshold value can be with
It it was 80% (being less than foregoing Second Threshold 90%), certainly, it can also be arranged to other numerical value, and the present invention is to the 3rd threshold value
Specific value is not limited.
Further, it is noted that a certain moment may have the clock frequency of multiple cores can be turned down (as long as core when
Clock frequency is not the minimum frequency in list of frequency, and the clock frequency of the core can just be turned down).At this moment, according to a kind of real
Example is applied, the clock frequency of the largest number of core is turned down, with the management of convenient processor resource.In addition, turning down certain core
During clock frequency, the clock frequency of the core according to frequency level listed in the list of frequency of the core, can be turned down step by step
Rate；The clock frequency of the core can also be turned down every level；Directly the clock frequency of the core can also be turned down to minimum frequency.
It should be pointed out that the specific of clock frequency turns down rule and can voluntarily set by those skilled in the art, the present invention is not limited it
System.
For example, certain polycaryon processor includes four 0~CPU3 of core CPU, current all cores be in working condition and
Respective intermediate frequency is worked in, minimum utilization rate is less than the 3rd threshold value.At this moment, the clock frequency of the largest number of core is turned down
Rate, that is, turn down CPU3 clock frequency.Assuming that for example foregoing table 1 of CPU3 list of frequency, CPU0 is turned down to next frequency etc.
Level, i.e., be adjusted to 0.624GHz by CPU0 clock frequency.
According to a kind of embodiment, when the utilization rate of a core is 0, the core is closed.So, technical side of the invention
Case first frequency reducing, drops core again when processor resource is superfluous, closes unnecessary processor resource, improves the reality of processor resource
Border utilization rate, reduces power consumption, saves electricity.
It should be pointed out that the present invention polycaryon processor scheduling scheme be lasting progress, every predetermined interval (referring to
Step S210), the utilization rate of each core of processor is obtained, in running order core is adjusted according to the utilization rate of each core
Quantity and each core clock frequency.According to a kind of embodiment, when scheduling operation is one idle cores of unlatching or heightens
During one clock frequency less than frequency core, predetermined interval is set to the first value；When scheduling operation is one core of reduction
During one core of clock frequency or closing of the heart, predetermined interval is set to second value；Wherein, the first value is less than second
Value.The specific value of first value and second value can voluntarily be set by those skilled in the art, and the present invention is without limitation.Example
Such as, the first value can be set to 20ms, second value is set to 80ms.Due to first value be less than second value, therefore the present invention skill
Art scheme can realize it is quick rise core/raising frequency, frequency reducing/drop core at a slow speed, it is ensured that fluency during application operation, it is to avoid system
Interim card, while power consumption can be reduced, saves electricity.
Fig. 3 shows the schematic diagram of polycaryon processor scheduling process according to an embodiment of the invention.It is many shown in Fig. 3
Core processor includes four 0~CPU3 of core CPU, the list of frequency of each core as shown in foregoing table 1, then each core it is maximum frequently
Rate is 1.391GHz, and minimum frequency is 0.221GHz, and intermediate frequency is 0.715GHz.Setting heightens clock frequency or turns down clock
The rule of frequency is to adjust (being adjusted according to frequency level ± 3) every two-stage；First threshold is 60%, and Second Threshold is
90%, the 3rd threshold value is 80%；First value of predetermined interval is 20ms, and second value is 80ms；Regulation is any when being not carried out
During operation, predetermined interval is also set to the first value 20ms.
In t1Moment, only CPU0 are in running order, and its clock frequency is 0.416GHz, less than intermediate frequency
0.715GHz；But its utilization rate is 82%, not up to Second Threshold 90%, therefore the moment does not perform any operation, between predetermined
Every set of time be the first value 20ms.
After 20ms, t is reached2Moment.At the moment, still only CPU0 is in running order, its clock frequency still less than
Intermediate frequency, but its utilization rate is changed into 95%, has exceeded Second Threshold, therefore need CPU0 clock frequency rising to intermediate frequency
0.715GHz.Due to performing raising frequency operation, predetermined time interval is set to the first value 20ms.
After 20ms, t is reached3Moment.At the moment, still only CPU0 is in running order, and its clock frequency is centre
Frequency 0.715GHz；Utilization rate is 80%, has exceeded first threshold 60%, therefore needs to open the minimum idle cores of numbering
CPU1.Due to performing a liter core operation, predetermined time interval is set to the first value 20ms.
After 20ms, t is reached4Moment.At the moment, CPU0, CPU1 are in running order, and the minimum utilization rate of processor is
75%, more than first threshold 60%, therefore need to open the minimum idle cores CPU2 of numbering., will due to performing a liter core operation
Predetermined time interval is set to the first value 20ms.
After 20ms, t is reached5Moment.At the moment, CPU0~CPU2 is in running order, the minimum utilization rate of processor
For 68%, more than first threshold 60%, therefore need to open the minimum idle core CPU3 of numbering., will due to performing a liter core operation
Predetermined time interval is set to the first value 20ms.
After 20ms, t is reached6Moment.At the moment, CPU0~CPU3 is in working condition, in the absence of idle cores, place
The minimum utilization rate for managing device is 70%, not up to Second Threshold 90%, therefore the moment does not perform any operation, during by predetermined space
Between be set to the first value 20ms.
After 20ms, t is reached7Moment.At the moment, CPU0~CPU3 is in working condition, in the absence of idle cores, and
Each core is less than frequency (clock frequency is less than peak frequency).The minimum utilization rate of processor is 91%, more than Second Threshold
90%, therefore need the clock frequency for numbering minimum core CPU 0 heightening Three Estate, it is changed into 0.949GHz.Due to performing
Raising frequency is operated, and predetermined interval is set into the first value 20ms.
After 20ms, t is reached8Moment.At the moment, CPU0~CPU3 is in working condition, in the absence of idle cores, and
Each core is less than frequency.The minimum utilization rate of processor is 85%, less than Second Threshold 90%, therefore does not perform any operation, will
Predetermined interval is set to the first value 20ms.
After 20ms, t is reached9Moment.At the moment, CPU0~CPU3 is in working condition, in the absence of idle cores, and
Each core is less than frequency.The minimum utilization rate of processor is 81%, less than Second Threshold 90%, therefore does not perform any operation, will
Predetermined interval is set to the first value 20ms.
After 20ms, t is reached10Moment.At the moment, CPU0~CPU3 is in working condition, in the absence of idle cores, and
Each core is less than frequency not also in low-limit frequency.The minimum utilization rate of processor is 74%, less than the 3rd threshold value 80%, therefore is needed
The clock frequency of the largest number of core CPU 3 is turned down into Three Estate, is changed into 0.481GHz.Due to performing frequency redution operation,
Predetermined interval is set to second value 80ms.
After 80ms, t is reached11Moment.At the moment, CPU0~CPU3 is in working condition, in the absence of idle cores, and
Each core is less than frequency not also in low-limit frequency.The minimum utilization rate of processor is 30%, less than the 3rd threshold value 80%, therefore is needed
The clock frequency of the largest number of core CPU 3 is turned down into Three Estate, is changed into 0.221GHz.Due to performing frequency redution operation,
Predetermined interval is set to second value 80ms.
After 80ms, t is reached12Moment.At the moment, CPU3 utilization rate is reduced to 0, therefore closes the core.Due to performing
Core operation is dropped, predetermined interval is set to second value 80ms.
After 80ms, t is reached13Moment.At the moment, CPU0~CPU2 is in running order, the minimum utilization rate of processor
For 50%, not up to first threshold 60%, therefore any operation is not performed, predetermined time interval is set to the first value 20ms.
After 20ms, t is reached14Moment.At the moment, CPU2 utilization rate is reduced to 0, therefore closes the core.Due to performing
Core operation is dropped, predetermined interval is set to second value 80ms.
t14After moment, according to the utilization rate of each core, can continue to adjust the quantity of in running order core with
And the clock frequency of each core.By length is limited, it will not enumerate herein.
A8：Method any one of A5-7, wherein, in addition to step：When the utilization rate of a core is 0, close
Close the core.
A9：Method described in A8, wherein, when scheduling operation is one idle cores of unlatching or heightens one less than frequency core
Clock frequency when, predetermined interval is set to the first value；When scheduling operation be turn down core clock frequency or
When closing a core, predetermined interval is set to second value；Wherein, first value is less than second value.
A10：Method described in A9, wherein, first value is 20ms, and second value is 80ms.
Various technologies described herein can combine hardware or software, or combinations thereof is realized together.So as to the present invention
Method and apparatus, or the process and apparatus of the present invention some aspects or part can take embedded tangible media, for example may be used
Program code (instructing) in mobile hard disk, USB flash disk, floppy disk, CD-ROM or other any machine readable storage mediums
Form, wherein when program is loaded into the machine of such as computer, mobile terminal etc, and when being performed by the machine, the machine
The equipment that device becomes the practice present invention.
In the case where program code is performed on programmable computers, mobile terminal generally comprises processor, processor
Readable storage medium (including volatibility and nonvolatile memory and/or memory element), at least one input unit, and extremely
A few output device.Wherein, memory is arranged to store program codes；Processor is arranged to according to the memory
Instruction in the described program code of middle storage, performs the polycaryon processor dispatching method of the present invention.
By way of example and not limitation, computer-readable recording medium includes readable storage medium storing program for executing and communication media.Readable storage medium storing program for executing
Store the information such as computer-readable instruction, data structure, program module or other data.Communication media is general such as to carry
The modulated message signal such as ripple or other transmission mechanisms embodies computer-readable instruction, data structure, program module or other
Data, and including any information transmitting medium.Any combination above is also included within the scope of computer-readable recording medium.
This place provide specification in, algorithm and display not with any certain computer, virtual system or other
Equipment is inherently related.Various general-purpose systems can also be used together with the example of the present invention.As described above, construct this kind of
Structure required by system is obvious.In addition, the present invention is not also directed to any certain programmed language.It should be understood that can
To realize the content of invention described herein using various programming languages, and the description done above to language-specific be for
Disclose the preferred forms of the present invention.
In the specification that this place is provided, numerous specific details are set forth.It is to be appreciated, however, that the implementation of the present invention
Example can be put into practice in the case of these no details.In some instances, known method, knot is not been shown in detail
Structure and technology, so as not to obscure the understanding of this description.
Similarly, it will be appreciated that in order to simplify the disclosure and help to understand one or more of each inventive aspect, exist
Above in the description of the exemplary embodiment of the present invention, each feature of the invention is grouped together into single implementation sometimes
In example, figure or descriptions thereof.However, the method for the disclosure should be construed to reflect following intention：It is i.e. required to protect
The application claims of shield are than the feature more features that is expressly recited in each claim.More precisely, as following
As claims reflect, inventive aspect is all features less than single embodiment disclosed above.Therefore, abide by
Thus the claims for following embodiment are expressly incorporated in the embodiment, wherein each claim is in itself
It is used as the separate embodiments of the present invention.
Those skilled in the art should be understood the module or unit or group of the equipment in example disclosed herein
Part can be arranged in equipment as depicted in this embodiment, or alternatively can be positioned at and the equipment in the example
In different one or more equipment.Module in aforementioned exemplary can be combined as a module or be segmented into addition multiple
Submodule.
Those skilled in the art, which are appreciated that, to be carried out adaptively to the module in the equipment in embodiment
Change and they are arranged in one or more equipment different from the embodiment.Can be the module or list in embodiment
Member or component be combined into a module or unit or component, and can be divided into addition multiple submodule or subelement or
Sub-component.In addition at least some in such feature and/or process or unit exclude each other, it can use any
Combination is disclosed to all features disclosed in this specification (including adjoint claim, summary and accompanying drawing) and so to appoint
Where all processes or unit of method or equipment are combined.Unless expressly stated otherwise, this specification (including adjoint power
Profit is required, summary and accompanying drawing) disclosed in each feature can or similar purpose identical, equivalent by offer alternative features come generation
Replace.
Although in addition, it will be appreciated by those of skill in the art that some embodiments described herein include other embodiments
In included some features rather than further feature, but the combination of the feature of be the same as Example does not mean in of the invention
Within the scope of and form different embodiments.For example, in the following claims, times of embodiment claimed
One of meaning mode can be used in any combination.
In addition, be described as herein can be by the processor of computer system or by performing for some in the embodiment
Method or the combination of method element that other devices of the function are implemented.Therefore, with for implementing methods described or method
The processor of the necessary instruction of element forms the device for implementing this method or method element.In addition, device embodiment
Element described in this is the example of following device：The device is used to implement as in order to performed by implementing the element of the purpose of the invention
Function.
As used in this, unless specifically stated so, come using ordinal number " first ", " second ", " the 3rd " etc.
Description plain objects are merely representative of the different instances for being related to similar object, and are not intended to imply that the object being so described must
Must have the time it is upper, spatially, in terms of sequence or given order in any other manner.
Although describing the present invention according to the embodiment of limited quantity, above description, the art are benefited from
It is interior it is clear for the skilled person that in the scope of the present invention thus described, it can be envisaged that other embodiments.Additionally, it should be noted that
The language that is used in this specification primarily to readable and teaching purpose and select, rather than in order to explain or limit
Determine subject of the present invention and select.Therefore, in the case of without departing from the scope and spirit of the appended claims, for this
Many modifications and changes will be apparent from for the those of ordinary skill of technical field.For the scope of the present invention, to this
The done disclosure of invention is illustrative and be not restrictive, and it is intended that the scope of the present invention be defined by the claims appended hereto.
Claims (10)
1. a kind of polycaryon processor dispatching method, is performed, this method includes in the terminal：
Every predetermined interval, the minimum utilization rate of processor is obtained, the minimum utilization rate is in running order each
The minimum value of the utilization rate of core；
When minimum utilization rate is more than or equal to first threshold, judge currently to whether there is idle cores；
If there are idle cores, an idle cores are opened, and are intermediate frequency by its clock set of frequency；
If in the absence of idle cores,
Judge whether minimum utilization rate is more than or equal to Second Threshold, wherein, the Second Threshold is more than the first threshold；
When minimum utilization rate be more than or equal to Second Threshold when, heighten a clock frequency less than frequency core, wherein, it is described less than
Frequency core is the core that clock frequency is less than peak frequency.
2. the method for claim 1, wherein it is described acquisition processor minimum utilization rate the step of before, also wrap
Include step：
Obtain the quantity for the core for being currently at working condition；
If currently an only core is in running order, the utilization rate and clock frequency of the core are obtained；
When the clock frequency of the core is more than or equal to first threshold equal to intermediate frequency, and utilization rate, an idle core is opened
The heart, and be intermediate frequency by its clock set of frequency；
When the clock frequency of the core is more than or equal to Second Threshold less than intermediate frequency, and utilization rate, by the clock of the core
Set of frequency is intermediate frequency.
3. method as claimed in claim 1 or 2, wherein, include the step of one idle cores of the unlatching：Open numbering most
Small idle cores；
It is described heighten one less than frequency core clock frequency the step of include：Heighten the minimum clock less than frequency core of numbering
Frequency.
4. the method as any one of claim 1-3, wherein, intermediate frequency in the list of frequency of processor core with
The immediate clock frequency of half of peak frequency.
5. the method for claim 1, wherein also include step：
When all cores are in working condition, and minimum utilization rate is when being less than three threshold values, turns down the clock frequency of a core
Rate；Wherein, the 3rd threshold value is less than the Second Threshold.
6. method as claimed in claim 5, wherein, it is described turn down core clock frequency the step of include：Turn down volume
The clock frequency of number maximum core.
7. method as claimed in claim 5, wherein, the first threshold is 60%, and Second Threshold is 90%, and the 3rd threshold value is
80%.
8. a kind of polycaryon processor dispatching device, is resided in mobile terminal, described device is configured as being suitable to make the movement
Terminal performs the polycaryon processor dispatching method as any one of claim 1-7.
9. a kind of mobile terminal, including：
The working condition of each core can be dispatched by programmed instruction in polycaryon processor, the polycaryon processor；With
Have program stored therein the memory of instruction, and described program instruction includes polycaryon processor scheduling as claimed in claim 8 and filled
Put so that the mobile terminal can perform the polycaryon processor dispatching method as any one of claim 1-7.
10. a kind of readable storage medium storing program for executing for the instruction that has program stored therein, when the programmed instruction quilt stored in the readable storage medium storing program for executing
When mobile terminal is read so that the mobile terminal performs the polycaryon processor scheduling as any one of claim 1-7
Method.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108984360A (en) * | 2018-06-06 | 2018-12-11 | 北京嘉楠捷思信息技术有限公司 | Chip frequency modulation method and device of computing equipment, computing force board, computing equipment and storage medium |
| CN109388494A (en) * | 2018-10-29 | 2019-02-26 | 济南浪潮高新科技投资发展有限公司 | A kind of method that multi-core network controller dynamic energy consumption is adjusted |
| CN110321266A (en) * | 2019-06-05 | 2019-10-11 | 上海易点时空网络有限公司 | CPU multi-core utilization rate optimization processing method and device for single server |
| CN110764605A (en) * | 2019-10-30 | 2020-02-07 | Oppo广东移动通信有限公司 | Multi-core processor control method and device, electronic equipment and storage medium |
| CN111026448A (en) * | 2019-12-10 | 2020-04-17 | 航天新长征大道科技有限公司 | Compact peripheral interconnection bus control system |
| CN111506154A (en) * | 2020-04-14 | 2020-08-07 | 深圳比特微电子科技有限公司 | Method and system for increasing computing power and reducing computing power ratio of computer |
| CN112068690A (en) * | 2020-09-04 | 2020-12-11 | 龙芯中科技术有限公司 | Processor frequency modulation method and device |
| CN114664426A (en) * | 2018-02-12 | 2022-06-24 | 北京绪水互联科技有限公司 | Analysis method for work schedule of medical equipment |
| CN117136344A (en) * | 2021-04-01 | 2023-11-28 | 高通股份有限公司 | Adaptive dynamic clock and voltage scaling |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101981529A (en) * | 2008-03-28 | 2011-02-23 | 微软公司 | Power-aware thread scheduling and dynamic use of processors |
| CN102866921A (en) * | 2012-08-29 | 2013-01-09 | 惠州Tcl移动通信有限公司 | Method and system for regulating and controlling multi-core central processing unit (CPU) |
| CN102955549A (en) * | 2011-08-29 | 2013-03-06 | 华为技术有限公司 | Power supply management method and power supply management system for multi-core CPU (central processing unit) and CPU |
| CN106502962A (en) * | 2015-09-04 | 2017-03-15 | 联发科技股份有限公司 | The method of the operation of control process device core in electronic installation and electronic installation |
-
2017
- 2017-06-23 CN CN201710486456.7A patent/CN107239348B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101981529A (en) * | 2008-03-28 | 2011-02-23 | 微软公司 | Power-aware thread scheduling and dynamic use of processors |
| CN102955549A (en) * | 2011-08-29 | 2013-03-06 | 华为技术有限公司 | Power supply management method and power supply management system for multi-core CPU (central processing unit) and CPU |
| CN102866921A (en) * | 2012-08-29 | 2013-01-09 | 惠州Tcl移动通信有限公司 | Method and system for regulating and controlling multi-core central processing unit (CPU) |
| CN106502962A (en) * | 2015-09-04 | 2017-03-15 | 联发科技股份有限公司 | The method of the operation of control process device core in electronic installation and electronic installation |
Non-Patent Citations (3)
| Title |
|---|
| WEI ZHANG 等: "Dynamic core scaling: Trading off performance and energy beyond DVFS", 《2015 33RD IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD)》 * |
| WONYOUNG KIM 等: "System level analysis of fast, per-core DVFS using on-chip switching regulators", 《2008 IEEE 14TH INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE》 * |
| 刘海峰: "基于Android嵌入式系统的低功耗优化", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114664426B (en) * | 2018-02-12 | 2023-06-02 | 北京绪水互联科技有限公司 | Analysis method for work schedule of medical equipment |
| CN114664426A (en) * | 2018-02-12 | 2022-06-24 | 北京绪水互联科技有限公司 | Analysis method for work schedule of medical equipment |
| CN108984360A (en) * | 2018-06-06 | 2018-12-11 | 北京嘉楠捷思信息技术有限公司 | Chip frequency modulation method and device of computing equipment, computing force board, computing equipment and storage medium |
| CN109388494A (en) * | 2018-10-29 | 2019-02-26 | 济南浪潮高新科技投资发展有限公司 | A kind of method that multi-core network controller dynamic energy consumption is adjusted |
| CN110321266B (en) * | 2019-06-05 | 2021-11-09 | 上海易点时空网络有限公司 | CPU multi-core utilization rate optimization processing method and device for single server |
| CN110321266A (en) * | 2019-06-05 | 2019-10-11 | 上海易点时空网络有限公司 | CPU multi-core utilization rate optimization processing method and device for single server |
| CN110764605A (en) * | 2019-10-30 | 2020-02-07 | Oppo广东移动通信有限公司 | Multi-core processor control method and device, electronic equipment and storage medium |
| CN111026448A (en) * | 2019-12-10 | 2020-04-17 | 航天新长征大道科技有限公司 | Compact peripheral interconnection bus control system |
| CN111506154B (en) * | 2020-04-14 | 2021-05-25 | 深圳比特微电子科技有限公司 | Method and system for increasing computing power and reducing computing power ratio of computer |
| CN111506154A (en) * | 2020-04-14 | 2020-08-07 | 深圳比特微电子科技有限公司 | Method and system for increasing computing power and reducing computing power ratio of computer |
| CN112068690A (en) * | 2020-09-04 | 2020-12-11 | 龙芯中科技术有限公司 | Processor frequency modulation method and device |
| CN112068690B (en) * | 2020-09-04 | 2022-09-20 | 龙芯中科技术股份有限公司 | Processor frequency modulation method and device |
| CN117136344A (en) * | 2021-04-01 | 2023-11-28 | 高通股份有限公司 | Adaptive dynamic clock and voltage scaling |
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