CN107229153B - Embedded touch control type array substrate and production method and display device - Google Patents
Embedded touch control type array substrate and production method and display device Download PDFInfo
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- CN107229153B CN107229153B CN201710553129.9A CN201710553129A CN107229153B CN 107229153 B CN107229153 B CN 107229153B CN 201710553129 A CN201710553129 A CN 201710553129A CN 107229153 B CN107229153 B CN 107229153B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Geometry (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
A kind of embedded touch control type array substrate and production method and display device, the embedded touch control type array substrate includes common electrode layer and induction line layer, the common electrode layer includes the multiple public electrode blocks for being spaced apart from each other and being arranged in array, the induction line layer includes the multiple induction lines for being spaced apart from each other arrangement, one end of every induction line is electrically connected by via hole public electrode block electrical connection corresponding with one in the common electrode layer, the other end of every induction line with touch-control driving integrated chip in the induction line layer.The production method of the embedded touch control type array substrate is by making common electrode layer and induction line layer using an intermediate tone mask version, single exposure can be reduced, shorten processing time, reduces production cost, and will not impact to touch-control sensitivity and pixel aperture ratio.
Description
Technical field
The present invention relates to field of display technology, and in particular to a kind of embedded touch control type array substrate and production method and aobvious
Showing device.
Background technique
With the rapid development of display technology, touch screen (touch panel) has spread each side in people's life
Face.With being constantly progressive for touch technology, requirement of the people to touch-control product is also higher and higher, while paying close attention to sensitivity also
Consider it is frivolous so that display panel manufacturer processing procedure cost is significantly promoted.
Currently, touch screen can be divided into according to composed structure: covering surface-type touch screen (On-cell touch panel)
And In-cell touch panel (In-cell touch panel).In-cell touch panel is to be embedded in the touch control electrode of touch screen
Inside display screen, such as touch control electrode is embedded in array substrate.Wherein there is a kind of mode, is to utilize the public affairs in array substrate
Common electrode layer (common electrode) serves as touch control electrode, and common electrode layer takes time-sharing multiplex, shows that picture and touching
Alternately, i.e. a frame picture is divided into display period and touch-control period to control sensing, and common electrode layer is used in the display period
It carries out picture in driving liquid crystal molecule to show, in the touch-control period for realizing touch-control sensing detection.
As shown in Figure 1, a kind of existing array substrate is equipped with common electrode layer and induction line layer, wherein public electrode
Layer includes being arranged in array and multiple public electrode blocks 81 of mutually insulated, induction line layer include a plurality of induction of mutually insulated
Route 82, a plurality of induction line 82 corresponds respectively with the multiple public electrode block 81 to be electrically connected.Specifically, public
It is equipped with insulating layer between electrode layer and induction line layer, is equipped in insulating layer in position corresponding with each public electrode block 81
Via hole 83, one end of every induction line 82 passes through the public electrode block 81 corresponding with one of via hole 83 in induction line layer
It is electrically connected, the other end of every induction line 82 is electrically connected with touch-control driving integrated chip 90 in induction line layer.
As shown in Fig. 2, be additionally provided in the array substrate intersected by the insulation of scan line 86 and data line 87 limit it is multiple
Pixel unit, each pixel unit is interior to be equipped with pixel electrode 88 and thin film transistor (TFT) 70.Fig. 2 show each item of induction line layer
Induction line 82 is overlapped with about 87 data line.
As shown in figure 3, the array substrate at least needs to undergo eight etch process in production.First of etching system
Journey is used to make the grid 71 and scan line 86 of thin film transistor (TFT) 70；Second etch process is for making thin film transistor (TFT) 70
Semiconductor layer 72；Third road etch process is used to make the source electrode 73 of thin film transistor (TFT) 70 and drain 74 and data line 87；
4th etch process is used to make the contact hole 89 of switch on pixel electrode 88；5th etch process is for making pixel electrode
88；6th etch process is used to make the induction line 82 of induction line layer；7th etch process is public for making conducting
The via hole 83 of common electrode block 81；8th etch process is used to make the public electrode block 81 of common electrode layer.This technique
Method needs multiple exposure and etching, and processing time is long and increases cost of manufacture.
Fig. 4 is the structural schematic diagram of single pixel unit in existing another array substrate, and Fig. 4 show induction line
Layer each induction line 82 and data line 87 same layer and close to be arranged side by side.
As shown in figure 5, the array substrate, in production, first of etch process is used to make the grid of thin film transistor (TFT) 70
Pole 71 and scan line 86；Second etch process is used to make the semiconductor layer 72 of thin film transistor (TFT) 70；Third road etching system
Journey is used to make the induction line 82 of the source electrode 73 of thin film transistor (TFT) 70, drain 74 and data line 87 and induction line layer；The
For making pixel electrode 88, pixel electrode 88 is directly contacted with the drain electrode 74 of thin film transistor (TFT) 70 four etch process；5th
Road etch process is used to make the via hole 83 of conducting public electrode block 81；6th etch process is for making common electrode layer
Public electrode block 81.The etch process that this process needs to undergo is reduced, and reduces processing time and cost of manufacture, but
It is each induction line 82 and data line 87 due to induction line layer close to being arranged side by side, leads to the load of induction line 82
Weight, touch-control sensitivity is poor, and pixel aperture ratio is also decreased obviously.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of embedded touch control type array substrate and production methods and display dress
It sets, processing time and cost of manufacture can be reduced, and will not impact to touch-control sensitivity and pixel aperture ratio.
The embodiment of the present invention provides a kind of embedded touch control type array substrate, comprising:
Substrate；
Form multi-strip scanning line over the substrate and multiple data lines and multiple thin film transistor (TFT)s, it is described a plurality of to sweep
It retouches line and intersects the multiple pixel units limited in array distribution, the multiple thin film transistor (TFT) point with multiple data lines insulation
It Wei Yu not be in the multiple pixel unit；
First insulating layer, first insulating layer are covered on the multiple thin film transistor (TFT)；
Common electrode layer, the common electrode layer are formed on the first insulating layer, and the common electrode layer includes phase
The multiple public electrode blocks for being mutually spaced and being arranged in array；
Second insulating layer, the second insulating layer are formed in the common electrode layer, and the second insulating layer is adjacent
The public electrode block separated and correspond to each public electrode block and be equipped with via hole；
Induction line layer, the induction line layer are formed on the second insulating layer, and the induction line layer includes phase
The multiple induction lines being mutually intervally arranged, every induction line two neighboring public electrode block in their extension direction
Between be disconnect；
Third insulating layer, the third insulating layer are formed on the induction line layer, and the third insulating layer covering is each
Induction line described in item corresponds to every induction line in the third insulating layer at the both ends of open position and is equipped with bridge joint
Hole corresponds to the leakage of each thin film transistor (TFT) in the third insulating layer, the second insulating layer and first insulating layer
Pole is equipped with contact hole；
Pixel electrode layer, the pixel electrode layer are formed on the third insulating layer, and the pixel electrode layer includes more
A conductive bar and multiple pixel electrodes, wherein each conductive bar insert in the corresponding bridge joint hole and will it is corresponding described in
Induction line conductive communication between the two neighboring public electrode block, each pixel electrode are located at corresponding pixel list
It is connected in first and in the corresponding contact hole of filling with the Drain Electrodes Conductive of the corresponding thin film transistor (TFT).
Further, one end of every induction line passes through the via hole and the public affairs in the induction line layer
A corresponding public electrode block electrical connection, the other end and the touch-control driving of every induction line collect in common electrode layer
It is electrically connected at chip.
Further, each public electrode block corresponds to multiple pixel units.
Further, induction line described in each item is Chong Die with above and below the multiple data lines in the induction line layer sets
It sets.
Further, the common electrode layer and the pixel electrode layer are made of electrically conducting transparent material, the induction
Line layer is made of metal, and first insulating layer, the second insulating layer and the third insulating layer use inorganic insulation
Material is made.
The embodiment of the present invention also provides a kind of display device, including above-mentioned embedded touch control type array substrate.
The embodiment of the present invention also provides a kind of production method of embedded touch control type array substrate, comprising steps of
Production forms multi-strip scanning line and multiple data lines and multiple thin film transistor (TFT)s, the multi-strip scanning on substrate
Line intersects the multiple pixel units limited in array distribution, the multiple thin film transistor (TFT) difference with multiple data lines insulation
In the multiple pixel unit；
The first insulating layer is deposited on the multiple thin film transistor (TFT), deposits public electrode on the first insulating layer
Layer, deposits second insulating layer in the common electrode layer；
The second insulating layer is etched, correspond to two neighboring public electrode block between open position and
Position corresponding to via hole removes the second insulating layer, and the institute below the removal position of the second insulating layer is exposed
State common electrode layer；
Induction line layer is deposited in the second insulating layer and the common electrode layer of exposing；
Photoresist layer is coated on the induction line layer；
The photoresist layer is exposed using an intermediate tone mask version, is then developed to the photoresist layer, institute
It states photoresist layer and is formed after development and completely remove region, region be fully retained and part removal region, completely removed wherein described
Region corresponds to the open position between the two neighboring public electrode block, and the region that is fully retained is corresponding to every induction
The extended position of route, part removal region correspond to other regions of the photoresist layer；
Using the photoresist layer as mask, wet corrosion is carried out to the induction line layer completely removed below region
It carves, removal completely removes the corresponding induction line layer in region with described, and completely removes below the exposing of region described
The common electrode layer；
The photoresist layer is continued with as mask, the common electrode layer for completely removing region exposing is carried out
Wet etching, removal completely remove the corresponding common electrode layer in region with described, and formation is spaced apart from each other and is arranged in array
Multiple public electrode blocks；
The photoresist layer is ashed, the photoresist layer in part removal region is completely removed and exposes lower section
The induction line layer, but the region that is fully retained still remains with the photoresist layer；
The induction line layer exposed to part removal region carries out wet etching, removal and part removal area
The corresponding induction line layer in domain, formation is spaced apart from each other and multiple induction lines of parallel arrangement；
The remaining photoresist layer is removed, every induction line is two neighboring in their extension direction at this time
It is to disconnect between the public electrode block；
Third insulating layer is deposited on the induction line layer, the third insulating layer covers each induction line, to institute
Third insulating layer is stated to be etched in the both ends of the open position of correspondence every induction line formation bridge joint hole and in correspondence
The drain locations of each thin film transistor (TFT) form contact hole；
The pixel deposition electrode layer on the third insulating layer, is etched the pixel electrode layer to form multiple pixels
Electrode and multiple conductive bars, wherein each conductive bar is inserted in the corresponding bridge joint hole and is connected across two neighboring described
Open position between public electrode block makes every induction line in open position by the conductive bar conductive communication,
Each pixel electrode be located in corresponding pixel unit and in the corresponding contact hole of filling with the corresponding film crystal
The Drain Electrodes Conductive of pipe connects.
Further, deposition is formed after the common electrode layer on the first insulating layer, further includes to the public affairs
Common electrode layer carries out high-temperature baking.
Further, it when carrying out wet etching to the common electrode layer, is specifically completely removed using chloroazotic acid to described
The common electrode layer that region is exposed is etched.
Further, the common electrode layer and the pixel electrode layer are made of electrically conducting transparent material, the induction
Line layer is made of metal, and first insulating layer, the second insulating layer and the third insulating layer use inorganic insulation
Material is made.
Embedded touch control type array substrate and production method provided in an embodiment of the present invention, by utilizing an intermediate tone mask
Version makes common electrode layer and induction line layer, it is possible to reduce and single exposure shortens processing time, reduces production cost, and
Touch-control sensitivity and pixel aperture ratio will not be impacted.
Detailed description of the invention
Fig. 1 is a kind of existing floor map of array substrate.
Fig. 2 is the structural schematic diagram of single pixel unit in the array substrate of Fig. 1.
Fig. 3 is schematic cross-section of the Fig. 2 along line A-A.
Fig. 4 is the structural schematic diagram of single pixel unit in existing another array substrate.
Fig. 5 is schematic cross-section of the Fig. 4 along line B-B.
Fig. 6 is the planar structure schematic diagram of array substrate in one embodiment of the invention.
Fig. 7 is the enlarged plan structural schematic diagram in Fig. 6 at array substrate dotted line frame C.
Fig. 8 is schematic cross-section of the Fig. 7 along line D-D.
Fig. 9 a to Fig. 9 j is array substrate in Fig. 6 along the manufacturing process schematic cross-section of E-E line.
Figure 10 a to Figure 10 l is the manufacturing process floor map in Fig. 6 at array substrate dotted line frame F.
Specific embodiment
It is of the invention to reach the technical approach and effect that predetermined goal of the invention is taken further to illustrate, below in conjunction with
Accompanying drawings and embodiments, to a specific embodiment of the invention, structure, feature and its effect, detailed description is as follows.
Fig. 6 is the planar structure schematic diagram of array substrate in one embodiment of the invention.Fig. 7 is that array substrate is empty in Fig. 6
Enlarged plan structural schematic diagram at wire frame C.Fig. 8 is schematic cross-section of the Fig. 7 along line D-D.As shown in Figure 6 to 8, this hair
The embedded touch control type array substrate that bright embodiment provides includes substrate 11, be formed on substrate 11 by multi-strip scanning line 12 with it is a plurality of
13 mutually insulated of data line intersects the multiple pixel units for limiting and being formed in array distribution, and pixel electricity is equipped in each pixel unit
Pole 141 and thin film transistor (TFT) 15.Thin film transistor (TFT) 15 includes grid 151, semiconductor layer 152, source electrode 153 and drain electrode 154.Scanning
The grid 151 of line 12 and thin film transistor (TFT) 15 is formed on substrate 11, and gate insulating layer 16 forms and be covered on 12 He of scan line
On grid 151, semiconductor layer 152 is formed on gate insulating layer 16,153 He of source electrode of data line 13 and thin film transistor (TFT) 15
Drain electrode 154 is formed on gate insulating layer 16, and source electrode 153 and drain electrode 154 connect with two end in contact of semiconductor layer 152 respectively
It connects.
Wherein, the grid 151 of thin film transistor (TFT) 15 is electrically connected corresponding scan line 12, the grid 151 of thin film transistor (TFT) 15
It can be independently arranged or may be a part of scan line 12, the source electrode 153 of thin film transistor (TFT) 15 is electrically connected corresponding number
According to line 13, the drain electrode 154 of thin film transistor (TFT) 15 is electrically connected corresponding pixel electrode 141.
It is deposited with the first insulating layer 17 on thin film transistor (TFT) 15, common electrode layer 18 is formed on the first insulating layer 17, it is public
It is deposited with second insulating layer 19 in common electrode layer 18, induction line layer 21, induction line layer 21 are formed in second insulating layer 19
On be deposited with third insulating layer 22, pixel electrode layer 14 is formed on third insulating layer 22.
Common electrode layer 18 includes being arranged in array and multiple public electrode blocks 181 of mutually insulated, each public electrode
Block 181 corresponds to multiple pixel units.Induction line layer 21 includes a plurality of induction line 211 of mutually insulated, a plurality of sense
It answers route 211 to overlap with about 13 multiple data lines, touch-control sensitivity and pixel aperture ratio will not be caused in this way
It influences.The a plurality of induction line 211 is corresponded respectively with the multiple public electrode block 181 and is electrically connected, specifically, public
Second insulating layer 19 is equipped between electrode layer 18 and induction line layer 21, in second insulating layer 19 with each public electrode block
181 corresponding positions are equipped with via hole 191, and one end of every induction line 211 passes through via hole 191 in induction line layer 21
Public electrode block 181 corresponding with one in common electrode layer 18 is electrically connected, and the other end and touch-control of every induction line 211 drive
Dynamic integrated chip 50 is electrically connected.
Due to being equipped with second insulating layer 19, every induction line between common electrode layer 18 and induction line layer 21
211 can keep insulating by second insulating layer 19 and other public electrode blocks 181.That is, every induction line 211
It is intermediate except the other end is electrically connected with touch-control driving integrated chip 50 in addition to one end is electrically connected with corresponding public electrode block 181
Mutually insulated between part and other public electrode blocks 181.
In the present embodiment, the induction line 211 of induction line layer 21 and the induction line 211 of common electrode layer 18 are in array
Embedded touch sensor (In-cell touch sensors) is formed in substrate, the embedded touch sensor is from appearance
Formula framework, each public electrode block 181 of common electrode layer 18 are used as from each line of induction in appearance electrode, induction line layer 21
Detectable signal is led to touch-control driving integrated chip 50 as cabling by road 211, by 50 pairs of detection letters of touch-control driving integrated chip
It number is handled.
In the present embodiment, touch-control sensing function, common electrode layer 18 are served as using the common electrode layer 18 in array substrate
Time-sharing multiplex is taken, picture is made to show that with touch-control sensing, alternately, i.e. a frame picture is divided into display period and touch-control time
Section, common electrode layer 18 is in the display period for applying common voltage (Vcom) and forming electric field between pixel electrode 141
It is shown with driving liquid crystal molecule to carry out picture, in the touch-control period for realizing touch-control sensing detection, to the touching on display screen
Signal is touched to be sensed.
Common electrode layer 18 and pixel electrode layer 14 can be made of electrically conducting transparents materials such as tin indium oxide (ITO), be felt
Answer line layer 21 that can be made of the lower metal of the resistivity such as Mo, Al, Au, Ag, Cu.First insulating layer 17, second insulating layer
19 and third insulating layer 22 can be made of inorganic insulating material such as silica, silicon nitride, silicon oxynitride etc..
The embodiment of the present invention also provides a kind of production method of above-mentioned array substrate, includes the following steps:
Production forms multi-strip scanning line 12 and multiple data lines 13 and multiple thin film transistor (TFT)s 15 on substrate 11, described
Multi-strip scanning line 12 intersects the multiple pixel units limited in array distribution with the multiple data lines 13 insulation, the multiple thin
Film transistor 15 is located in the multiple pixel unit；
Wherein, production forms multi-strip scanning line 12 and multiple data lines 13 and multiple thin film transistor (TFT)s on substrate 11
15, it can use but be not limited to following processing procedure and made, such as:
The first metal layer is first deposited on substrate 11, and the first metal layer is patterned using one of etch process,
Production obtains the grid 151 of scan line 12 and thin film transistor (TFT) 15；
Then gate insulating layer 16 is deposited in scan line 12 and grid 151, and one layer is deposited on gate insulating layer 16
Amorphous silicon layer, and amorphous silicon layer is patterned using one of etch process, production obtains corresponding be located above grid 151
Semiconductor layer 152；
Then the depositing second metal layer on semiconductor layer 152 and gate insulating layer 16, and one is utilized to second metal layer
Road etch process is patterned, and production obtains data line 13 and the source electrode 153 being separated from each other and 154, and 153 He of source electrode of draining
Drain electrode 154 is in contact with the both ends of semiconductor layer 152 respectively；
Next, Fig. 9 a to Fig. 9 j and Figure 10 a to Figure 10 l please be join, a 30 (half-tone of intermediate tone mask version is utilized
Mask common electrode layer 18 and induction line layer 21 are made).
As shown in Fig. 9 a and Figure 10 a, the first insulating layer 17 is deposited on the multiple thin film transistor (TFT) 15, in the first insulation
Common electrode layer 18 is deposited on layer 17, and second insulating layer 19 is deposited in common electrode layer 18；Wherein it is preferred to absolutely first
Deposition is formed after common electrode layer 18 in edge layer 17, is further included carrying out high-temperature baking to common electrode layer 18, is improved its stabilization
Property and electric conductivity.
As shown in Fig. 9 b and Figure 10 b, second insulating layer 19 is etched using one of etch process, it is adjacent corresponding to
Open position between two public electrode blocks 181 and the position corresponding to via hole 191 remove second insulating layer 19, the
Expose the common electrode layer 18 of lower section in the removal position of two insulating layers 19.
As shown in Fig. 9 c and Figure 10 c, induction line layer is deposited in second insulating layer 19 and the common electrode layer 18 exposed
21。
As shown in Fig. 9 d and Figure 10 d, photoresist layer 40 is coated on induction line layer 21.In the present embodiment, photoresist layer 40 with
It is illustrated for positivity photoresist.
As shown in Fig. 9 e and Figure 10 e, using 30 pairs of photoresist layers 40 of an intermediate tone mask version (half-tone mask) into
Row exposure, intermediate tone mask version 30 include opaque area 30a, semi-opaque region 30b and transparent area 30c, and intermediate tone mask version 30 is adopted
Processing is exposed to photoresist layer 40 with light transmittance different multiple regions, is then developed to photoresist layer 40, photoresist layer 40
It formed after development and completely removes region 41, region 42 be fully retained and part removal region 43, wherein completely removing region 41
Corresponding to the open position between two neighboring public electrode block 181, region 42 is fully retained corresponding to every induction line 211
Extended position, part remove region 43 correspond to photoresist layer 40 other regions.
As shown in Fig. 9 f and Figure 10 f, using photoresist layer 40 as mask, to the induction line for completely removing 41 lower section of region
Layer 21 carries out wet etching, removes induction line layer 21 corresponding with region 41 is completely removed, and expose completely removing region 41
The common electrode layer 18 of lower section.
As shown in Fig. 9 g and Figure 10 g, photoresist layer 40 is continued with as mask, to completely removing the public of the exposing of region 41
Electrode layer 18 carries out wet etching, removes common electrode layer 18 corresponding with region 41 is completely removed, just completes to common electrical in this way
The patterning of pole layer 18, forms the multiple public electrode blocks 181 for being spaced apart from each other and being arranged in array.Due in above-mentioned steps,
High-temperature baking was carried out to common electrode layer 18, therefore in this step, and can use chloroazotic acid and expose to region 41 is completely removed
Common electrode layer 18 be etched, improve etching efficiency.
As shown in Fig. 9 h and Figure 10 h, photoresist layer 40 is ashed (Ashing), part removes the photoresist layer 40 in region 43
It is completely removed and is exposed the induction line layer 21 of lower section, but region 42 is fully retained and still remains with photoresist layer 40.
As shown in Fig. 9 i and Figure 10 i, to part removal region 43 expose induction line layer 21 carry out wet etching, removal with
The part removal corresponding induction line layer 21 in region 43, just completes the patterning to induction line layer 21 in this way, is formed mutual
Every and parallel arrangement multiple induction lines 211.
As shown in Fig. 9 j and Figure 10 j, remaining photoresist layer 40 is removed, to utilize an intermediate tone mask version 30
It completes to make the patterning of common electrode layer 18 and induction line layer 21.But every induction line 211 is in its extension at this time
It is to disconnect between two neighboring public electrode block 181 on direction (the present embodiment is vertical direction).It is to be appreciated that at other
In embodiment, when the left or right side of array substrate is arranged in touch-control driving integrated chip 50, rather than when the downside of the present embodiment,
The extending direction of every induction line 211 can be horizontally oriented, but production method provided in this embodiment is general.
As shown in Fig. 8 and Figure 10 k, third insulating layer 22 is deposited on induction line layer 21, third insulating layer 22 covers respectively
Induction line 211, and third insulating layer 22 is etched in every induction line of correspondence 211 using one of etch process
The both ends of open position form bridge joint hole 221 and form contact hole in 154 position of drain electrode of each thin film transistor (TFT) 15 of correspondence
222, wherein contact hole 222 also extends through second insulating layer 19 and the first insulating layer 17；
As shown in Fig. 8 and Figure 10 l, the pixel deposition electrode layer 14 on third insulating layer 22, and utilize one of etch process
Pixel electrode layer 14 is etched to form multiple pixel electrodes 141 and multiple conductive bars 142, wherein each conductive bar 142 is filled out
Enter the open position in corresponding bridge joint hole 221 and being connected across between two neighboring public electrode block 181, makes every induction line
211 in open position by 142 conductive communication of conductive bar, each pixel electrode 141 be located in corresponding pixel unit and
It inserts in corresponding contact hole 222 and is conductively connected with the drain electrode 154 of corresponding thin film transistor (TFT) 15.To every induction line
211 one end is electrically connected by the public electrode block 181 corresponding with one in common electrode layer 18 of via hole 191, every induction
The other end of route 211 is electrically connected with touch-control driving integrated chip 50, and the middle section of every induction line 211 passes through conductive bar
142 are connected to and by realizing insulation between second insulating layer 19 and other public electrode blocks 181.
To sum up, embedded touch control type array substrate and production method provided in an embodiment of the present invention, by utilizing a Zhang Banse
Mask plate is adjusted to make common electrode layer and induction line layer, it is possible to reduce single exposure shortens processing time, and reduction is produced into
This, and touch-control sensitivity and pixel aperture ratio will not be impacted.
The embodiment of the present invention also provides a kind of display device, including above-mentioned embedded touch control type array substrate.Wherein, described
Display device can be liquid crystal display device, and further include the components such as color membrane substrates and liquid crystal layer.
The above is only presently preferred embodiments of the present invention, are not intended to limit the present invention in any form, although this
Invention has been disclosed in a preferred embodiment above, and however, it is not intended to limit the invention, any person skilled in the art, In
It does not depart within the scope of technical solution of the present invention, when the technology contents using the disclosure above make a little change or are modified to equivalent
The equivalent embodiment of variation, but without departing from the technical solutions of the present invention, according to the technical essence of the invention to the above reality
Any simple modification, equivalent change and modification made by example are applied, all of which are still within the scope of the technical scheme of the invention.
Claims (9)
1. a kind of embedded touch control type array substrate characterized by comprising
Substrate (11)；
The multi-strip scanning line (12) and multiple data lines (13) that are formed on the substrate (11) and multiple thin film transistor (TFT)s
(15), the multi-strip scanning line (12) intersects the multiple pixel lists limited in array distribution with the multiple data lines (13) insulation
Member, the multiple thin film transistor (TFT) (15) are located in the multiple pixel unit；
First insulating layer (17), first insulating layer (17) are covered on the multiple thin film transistor (TFT) (15)；
Common electrode layer (18), the common electrode layer (18) are formed on first insulating layer (17), the public electrode
Layer (18) includes the multiple public electrode blocks (181) for being spaced apart from each other and being arranged in array；
Second insulating layer (19), the second insulating layer (19) are formed on the common electrode layer (18), second insulation
Layer (19) is equipped in the separated of the adjacent public electrode block (181) and corresponding to each public electrode block (181)
Via hole (191)；
Induction line layer (21), the induction line layer (21) are formed on the second insulating layer (19), the induction line
Layer (21) includes the multiple induction lines (211) for being spaced apart from each other arrangement, the line of induction described in each item in the induction line layer (21)
Road (211) overlaps up and down with the multiple data lines (13), multiple induction lines (211) and multiple common electricals
Pole block (181) corresponds electrical connection respectively and every induction line (211) is two neighboring described in their extension direction
It is to disconnect between public electrode block (181)；
Third insulating layer (22), the third insulating layer (22) are formed on the induction line layer (21), the third insulation
Layer (22) covers induction line (211) described in each item, corresponds to every induction line (211) in the third insulating layer (22)
Bridge joint hole (221), the third insulating layer (22), the second insulating layer (19) and described the are equipped at the both ends of open position
The drain electrode (154) that each thin film transistor (TFT) (15) is corresponded in one insulating layer (17) is equipped with contact hole (222)；
Pixel electrode layer (14), the pixel electrode layer (14) are formed on the third insulating layer (22), the pixel electrode
Layer (14) includes multiple conductive bars (142) and multiple pixel electrodes (141), wherein each conductive bar (142) filling corresponds to
The bridge joint hole (221) in and by the corresponding induction line (211) the two neighboring public electrode block (181) it
Between conductive communication, each pixel electrode (141) is located in corresponding pixel unit and the corresponding contact hole of filling
(222) it is conductively connected in the drain electrode (154) of the corresponding thin film transistor (TFT) (15).
2. embedded touch control type array substrate as described in claim 1, which is characterized in that every in the induction line layer (21)
One end of the induction line (211) passes through the via hole (191) and a corresponding institute in the common electrode layer (18)
State public electrode block (181) electrical connection, the other end and touch-control driving integrated chip (50) electricity of every induction line (211)
Connection.
3. embedded touch control type array substrate as described in claim 1, which is characterized in that each public electrode block (181)
Corresponding to multiple pixel units.
4. embedded touch control type array substrate as described in claim 1, which is characterized in that the common electrode layer (18) and described
Pixel electrode layer (14) is made of electrically conducting transparent material, and the induction line layer (21) is made of metal, and described first absolutely
Edge layer (17), the second insulating layer (19) and the third insulating layer (22) are made of inorganic insulating material.
5. a kind of display device, which is characterized in that including the described in any item embedded touch control type array bases of such as Claims 1-4
Plate.
6. a kind of production method of embedded touch control type array substrate, which is characterized in that comprising steps of
Production forms multi-strip scanning line (12) and multiple data lines (13) and multiple thin film transistor (TFT)s (15) on substrate (11),
The multi-strip scanning line (12) intersects the multiple pixel units limited in array distribution, institute with the multiple data lines (13) insulation
Multiple thin film transistor (TFT)s (15) are stated to be located in the multiple pixel unit；
The first insulating layer (17) are deposited on the multiple thin film transistor (TFT) (15), are deposited on first insulating layer (17) public
Common electrode layer (18) deposits second insulating layer (19) on the common electrode layer (18)；
The second insulating layer (19) is etched, in the disconnection position corresponded between two neighboring public electrode block (181)
The position set and correspond to via hole (191) removes the second insulating layer (19), and in the second insulating layer (19)
Remove the common electrode layer (18) that lower section is exposed in position；
Induction line layer (21) are deposited in the second insulating layer (19) and the common electrode layer (18) exposed；
Photoresist layer (40) are coated on the induction line layer (21)；
The photoresist layer (40) is exposed using an intermediate tone mask version (30), then the photoresist layer (40) are carried out
Development, the photoresist layer (40) form completely remove region (41) after development, region (42) are fully retained and part removal area
Domain (43), wherein described completely remove region (41) are corresponding to the disconnection position between the two neighboring public electrode block (181)
It sets, the extended position that region (42) are fully retained and correspond to every induction line (211), the part removes region (43)
Other regions corresponding to the photoresist layer (40)；
Using the photoresist layer (40) as mask, to the induction line layer (21) completely removed below region (41)
Wet etching is carried out, removal completely removes region (41) corresponding described induction line layer (21) with described, and goes completely described
Except region (41) expose the common electrode layer (18) of lower section；
The photoresist layer (40) are continued with as mask, to the common electrode layer for completely removing region (41) exposing
(18) wet etching is carried out, removal completely removes region (41) corresponding described common electrode layer (18) with described, formed each other
Every and multiple public electrode blocks (181) for being arranged in array；
The photoresist layer (40) is ashed, the photoresist layer (40) of part removal region (43) is completely removed simultaneously
Expose the induction line layer (21) of lower section, but the region (42) that is fully retained still remains with the photoresist layer
(40)；
Wet etching is carried out to the induction line layer (21) that part removal region (43) is exposed, removal is gone with the part
Except region (43) the corresponding induction line layer (21), formation is spaced apart from each other and multiple induction lines of parallel arrangement
(211), the induction line (211) of formation overlaps up and down with the multiple data lines (13)；
The remaining photoresist layer (40) is removed, the induction lines (211) multiple at this time and multiple common electricals
Pole block (181) corresponds electrical connection respectively and every induction line (211) is two neighboring described in their extension direction
It is to disconnect between public electrode block (181)；
Third insulating layer (22) are deposited on the induction line layer (21), the third insulating layer (22) covers each line of induction
Road (211), to the third insulating layer (22) be etched the correspondence every induction line (211) open position two
End forms bridge joint hole (221) and forms contact hole in drain electrode (154) position of each thin film transistor (TFT) (15) of correspondence
(222)；
The pixel deposition electrode layer (14) on the third insulating layer (22), is etched the pixel electrode layer (14) to be formed
Multiple pixel electrodes (141) and multiple conductive bars (142), wherein each conductive bar (142) inserts the corresponding bridge joint
In hole (221) and the open position that is connected across between the two neighboring public electrode block (181), make every induction line
(211) in open position by the conductive bar (142) conductive communication, each pixel electrode (141) is located at corresponding picture
It is led in plain unit and in the corresponding contact hole (222) of filling with the drain electrode (154) of the corresponding thin film transistor (TFT) (15)
Electrical connection.
7. the production method of embedded touch control type array substrate as claimed in claim 6, which is characterized in that in first insulation
It deposits and is formed after the common electrode layer (18) on layer (17), further include that high temperature baking is carried out to the common electrode layer (18)
It is roasting.
8. the production method of embedded touch control type array substrate as claimed in claim 7, which is characterized in that the common electrical
When pole layer (18) carries out wet etching, specifically using chloroazotic acid to the common electrode layer for completely removing region (41) exposing
(18) it is etched.
9. the production method of embedded touch control type array substrate as claimed in claim 6, which is characterized in that the common electrode layer
(18) it being made with the pixel electrode layer (14) of electrically conducting transparent material, the induction line layer (21) is made of metal,
First insulating layer (17), the second insulating layer (19) and the third insulating layer (22) use inorganic insulating material system
At.
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| CN108427517B (en) * | 2018-02-09 | 2021-07-13 | 昆山龙腾光电股份有限公司 | Embedded touch array substrate, manufacturing method and liquid crystal display device |
| CN108446053B (en) * | 2018-03-27 | 2021-03-26 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN109101138A (en) | 2018-08-21 | 2018-12-28 | 武汉华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN110262689B (en) * | 2019-06-10 | 2021-01-01 | 武汉华星光电技术有限公司 | Embedded touch display panel and array substrate thereof |
| CN113113437B (en) * | 2021-03-29 | 2022-09-09 | 武汉华星光电技术有限公司 | Array substrate and preparation method thereof |
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