CN107222268B - Power amplifier module intermodulation automatic debugging and testing system and method - Google Patents
Power amplifier module intermodulation automatic debugging and testing system and method Download PDFInfo
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- CN107222268B CN107222268B CN201710642805.XA CN201710642805A CN107222268B CN 107222268 B CN107222268 B CN 107222268B CN 201710642805 A CN201710642805 A CN 201710642805A CN 107222268 B CN107222268 B CN 107222268B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/0082—Monitoring; Testing using service channels; using auxiliary channels
- H04B17/0085—Monitoring; Testing using service channels; using auxiliary channels using test signal generators
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/10—Monitoring; Testing of transmitters
- H04B17/101—Monitoring; Testing of transmitters for measurement of specific parameters of the transmitter or components thereof
- H04B17/104—Monitoring; Testing of transmitters for measurement of specific parameters of the transmitter or components thereof of other parameters, e.g. DC offset, delay or propagation times
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/10—Monitoring; Testing of transmitters
- H04B17/11—Monitoring; Testing of transmitters for calibration
- H04B17/13—Monitoring; Testing of transmitters for calibration of power amplifiers, e.g. gain or non-linearity
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Abstract
The invention discloses an automatic intermodulation debugging and testing system and method for a power amplifier module. The FPGA chip internal program module comprises an analog-to-digital converter (ADC) interface module, an FFT module, a power detection module, a two-tone signal generation module, an intermodulation calculation module, a intermodulation value comparison and judgment module and a digital-to-analog converter (DAC) interface. The invention can realize the automation of debugging and testing in the production process of the power amplifier module, improve the efficiency and reduce the production cost of the power amplifier module.
Description
Technical Field
The invention relates to the field of automatic debugging and testing of a power amplifier module, in particular to an automatic intermodulation debugging and testing system and method of the power amplifier module.
Background
With the development of social economy, the manufacture of wireless communication equipment needs automation and intellectualization, a power amplifier module is a signal amplification part of the wireless communication equipment, and the third-order and fifth-order intermodulation directly influences the signal quality of the power amplifier. The main factor influencing the third-order and fifth-order intermodulation of the power amplifier module is the grid voltage level of the power amplifier tube. In the power amplifier production debugging, a signal source and a spectrometer are mainly and manually adopted, so that the efficiency is low and the cost is high.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides an automatic power amplifier module intermodulation debugging and testing system and method, which are used for debugging the power amplifier module in an automatic mode, reducing the cost of manpower and instruments and greatly reducing the manufacturing cost of the power amplifier module.
The invention is realized by adopting the following technical scheme:
an automatic intermodulation debugging and testing device for a power amplifier module comprises an input mixer, an analog-to-digital converter (ADC), a first numerical control attenuator, a digital-to-analog converter (DAC), a second numerical control attenuator, an output signal mixing and amplifying device, an FPGA chip, a communication module and a clock generating module; wherein: the input mixer converts the radio frequency signal output by the power amplifier into an intermediate frequency signal and outputs the intermediate frequency signal to the first-stage numerical control attenuator; the first numerical control attenuator adjusts the amplitude of an input signal and outputs the amplitude to an analog-to-digital converter (ADC); the analog-to-digital converter (ADC) converts the analog signal into a digital signal and sends the digital signal into the FPGA chip for processing; the FPGA chip calculates an input signal to generate a digital double-tone signal and outputs the digital double-tone signal to a digital-to-analog converter (DAC); the digital-to-analog converter (DAC) converts the digital diphone signals generated by the FPGA chip into analog signals and outputs the analog signals to the second-stage numerical control attenuator; the second digital control attenuator realizes the adjustment of the size of the output analog signal and outputs the output analog signal to the output signal mixing and amplifying device; the output signal mixing and amplifying device is used for mixing and amplifying the analog signal output by the second-stage numerical control attenuator and outputting the signal to an external power amplifier; the communication module realizes the communication between the device and the power amplifier, the setting of the parameters of the device and the output of the calculation intermodulation value; the clock generation module generates reference clocks required by an analog-to-digital converter (ADC), an FPGA chip and a digital-to-analog converter (DAC).
The frequency of the signal frequency converted and output by the input mixer is in the sampling range of an analog-to-digital converter (ADC).
The amplitude of the signal converted and output by the first numerical control attenuator is in the sampling range of an analog-to-digital converter (ADC).
The output signal after being mixed and processed by the amplifier meets the frequency and amplitude required by the power amplifier input.
The FPGA chip comprises an analog-to-digital converter (ADC) interface module, an FFT module, a power detection module, an intermodulation calculation module, a two-tone signal generation module, a digital-to-analog converter (DAC) interface and an intermodulation value comparison and judgment module; the device comprises an analog-to-digital converter (ADC) interface module, an FFT module, an intermodulation calculation module, a intermodulation value comparison and judgment module, a communication module, a two-tone signal generation module and a digital-to-analog converter (DAC) interface which are sequentially connected, wherein the ADC interface module is connected with a power detection module; the functions realized by the method comprise input signal power calculation, input signal frequency spectrum calculation, output power intermodulation value calculation, judgment of whether the grid voltage level value of the power amplifier module is traversed or not, finding out the grid voltage level value corresponding to the best intermodulation point, writing the grid voltage level value into the power amplifier module, and calculating the power amplifier intermodulation value.
A power amplifier module intermodulation automatic debugging and testing method based on the device comprises the following steps:
step 1: setting parameters of output signals of the system through a communication module, wherein the parameters comprise the frequency of the output signals, the power of the signals and the interval frequency of the double-tone signals;
step 2: the double-tone signal generating module generates digital baseband double-tone signals corresponding to the parameters according to the double-tone signal interval frequency, and the digital baseband double-tone signals are sent to a digital-to-analog converter (DAC) through a DAC interface to convert the digital signals into analog signals; adjusting a second digital controlled attenuator behind a digital-to-analog converter (DAC) according to the set signal power parameter; setting local oscillation frequency of an output signal mixing and amplifier according to the set signal frequency parameter, and generating a required double-tone signal after mixing and amplifying;
and step 3: during debugging and testing, the connection mode is as follows: the output signal mixing and amplifier output port of the system is connected with the input port of the power amplifier module, and the output port of the power amplifier module is connected with the input port of the input mixer of the system after passing through the attenuator; the communication ports are connected through a communication module;
and 4, step 4: inquiring the information of the power amplifier module through the communication module, if the information can be inquired normally, indicating that the power amplifier module works normally, and performing subsequent steps, if the inquiry of the power amplifier module is abnormal or no information is replied, indicating that the power amplifier module works abnormally or is not connected, and not performing subsequent steps;
and 5: setting a grid voltage level value for the power amplification module, then sampling an output signal of the power amplification module by an analog-to-digital converter (ADC), and sending the sampled output signal to an FPGA chip;
step 6: an analog-to-digital converter (ADC) interface module receives sampling data of the ADC and respectively sends the sampling data to a power detection module and an FFT module, the power detection module is used for calculating the power of an input signal, when the power of the input signal is overlarge, a first numerical control attenuator at the front end of the ADC is attenuated, the front end of the ADC is prevented from being overloaded, the power is also used for calculating the output power of a power amplification module, the FFT module is used for calculating the frequency spectrum of the input signal, the calculated output data is sent to an intermodulation calculation module, the intermodulation value of the output power is calculated, and the grid voltage level value and the corresponding intermodulation value are stored;
and 7: the intermodulation value comparison and judgment module judges whether the grid voltage level value of the power amplification module is traversed, if the grid voltage level value is not changed, the grid voltage level value is written into the power amplification module, and the step 6 is repeated; if the traversal is completed, entering step 8;
and 8: the intermodulation value comparison and judgment module finds out the grid voltage level value corresponding to the intermodulation best point, writes the grid voltage level value into the power amplifier module, the intermodulation calculation module calculates the power amplifier intermodulation value, the intermodulation value is output from the communication module, and the debugging is finished.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the invention realizes the production debugging of the power amplifier module, realizes the automatic debugging of the system, greatly improves the efficiency, reduces signal sources and frequency spectrometers required by the debugging and greatly reduces the production cost of the power amplifier module. The intermodulation precision of the test output is compared with that of the test output by adopting a signal source and a frequency spectrograph, the precision is within +/-1 dB, and the error range of the batch production of the power amplifier is met.
Drawings
FIG. 1 is a block diagram of the overall architecture of the system of the present invention;
FIG. 2 is a block diagram of the structure of the internal program modules of the FPGA chip in the system of the present invention;
FIG. 3 is a connection diagram of the power amplifier module during debugging and testing of the system of the present invention;
FIG. 4 is a flow chart of the method of the present invention.
Detailed Description
A power amplifier module intermodulation automatic debugging and testing system and method, the system constitution refers to fig. 1, including input mixer, analog-to-digital converter (ADC), first numerical control attenuator, second numerical control attenuator, digital-to-analog converter (DAC), output signal mixing and amplifier, FPGA chip, communication module, clock generation module; the input mixer, the first numerical control attenuator, the analog-to-digital converter (ADC), the FPGA chip, the digital-to-analog converter (DAC), the second numerical control attenuator and the output signal mixing and amplifier are sequentially connected, the FPGA chip is respectively connected with the first numerical control attenuator, the second numerical control attenuator, the communication module and the clock generation module, and the clock generation module is respectively connected with the analog-to-digital converter (ADC) and the digital-to-analog converter (DAC); the communication module realizes the functions of parameter setting, power amplifier module information inquiry and result output.
Referring to fig. 2, the FPGA chip internal program module includes an analog-to-digital converter (ADC) interface module, an FFT module, a power detection module, an intermodulation calculation module, a two-tone signal generation module, a digital-to-analog converter (DAC) interface, and a intermodulation value comparison and determination module; the device comprises an analog-to-digital converter (ADC) interface module, an FFT module, an intermodulation calculation module, a intermodulation value comparison and judgment module, a communication module, a two-tone signal generation module and a digital-to-analog converter (DAC) interface which are sequentially connected, wherein the ADC interface module is connected with a power detection module.
The system is connected with a power amplifier module in a working state with reference to fig. 3, an output signal mixing and amplifier output port of the system is connected with an input port of the power amplifier module, a communication interface of the power amplifier module is connected with a system communication module, and an output end of the power amplifier module is connected with an input port of an input mixer after passing through an attenuator.
The work flow of the system refers to fig. 4, and specifically includes the following steps:
step 1: setting output signal parameters of the device through a communication module, wherein the parameters comprise the frequency of an output signal, the power of the signal and the interval frequency of a double-tone signal;
step 2: the double-tone signal generating module of the device generates digital baseband double-tone signals corresponding to parameters according to the interval frequency of the double-tone signals, the digital baseband double-tone signals are sent to a digital-to-analog converter (DAC) through a digital-to-analog converter (DAC) interface, the digital signals are converted into analog signals, a numerical control attenuator behind the digital-to-analog converter (DAC) is adjusted according to set signal power parameters, local oscillation frequency of a rear mixing and amplifier is set according to the set signal frequency parameters, and the required double-tone signals are generated after mixing and amplification;
and step 3: during debugging and testing, the connection mode is as follows: the output port of the device is connected with the input port of the power amplifier module, and the output port of the power amplifier module is connected with the input end of the device after passing through the attenuator; the communication port is connected with the communication module;
and 4, step 4: inquiring the information of the power amplifier module through the communication module, if the information can be inquired normally, indicating that the power amplifier module works normally, and performing subsequent steps, if the inquiry of the power amplifier module is abnormal or no information is replied, indicating that the power amplifier module works abnormally or is not connected, and not performing subsequent steps;
and 5: the device sets a grid voltage level value for a power amplification module through a communication module, and a rear analog-to-digital converter (ADC) samples an output signal of the power amplification module and sends the output signal into an FPGA chip;
step 6: an analog-to-digital converter (ADC) interface module receives sampling data of the ADC and respectively sends the sampling data to a power detection module and an FFT module, the power detection module is used for calculating the power of an input signal, when the power of the input signal is overlarge, a front-end digital control attenuator of the ADC is attenuated, the front end of the ADC is prevented from being overloaded, the power is also used for calculating the output power of a power amplification module, the FFT module is used for calculating the frequency spectrum of the input signal, the calculated output data is sent to an intermodulation calculation module, an output power intermodulation value is calculated, and a grid voltage level value and a corresponding intermodulation value are stored;
and 7: the intermodulation value comparison and judgment module judges whether the grid voltage level value of the power amplification module is traversed, if the grid voltage level value is not changed, the grid voltage level value is written into the power amplification module, and the step 6 is repeated; if the traversal is completed, entering step 8;
and 8: the intermodulation value comparison and judgment module finds out the grid voltage level value corresponding to the intermodulation best point, writes the grid voltage level value into the power amplifier module, the intermodulation calculation module calculates the power amplifier intermodulation value, the intermodulation value is output from the communication module, and the debugging is finished.
Claims (2)
1. The utility model provides a power amplifier module intermodulation automatic debugging and testing arrangement which characterized in that: the digital-to-analog converter (ADC) circuit comprises an input mixer, an analog-to-digital converter (ADC), a first digital control attenuator, a digital-to-analog converter (DAC), a second digital control attenuator, an output signal mixing and amplifier, an FPGA chip, a communication module and a clock generation module; wherein: the input mixer converts the radio-frequency signal output by the power amplifier into an intermediate-frequency signal and outputs the intermediate-frequency signal to the first numerical control attenuator; the first numerical control attenuator adjusts the amplitude of an input signal and outputs the amplitude to an analog-to-digital converter (ADC); the analog-to-digital converter (ADC) converts the analog signal into a digital signal and sends the digital signal into the FPGA chip for processing; the FPGA chip calculates an input signal to generate a digital double-tone signal and outputs the digital double-tone signal to a digital-to-analog converter (DAC); the digital-to-analog converter (DAC) converts the digital diphone signals generated by the FPGA chip into analog signals and outputs the analog signals to the second digital control attenuator; the second digital control attenuator realizes the adjustment of the size of the output analog signal and outputs the output analog signal to the output signal mixing and amplifying device; the output signal mixing and amplifying device is used for mixing and amplifying the analog signal output by the second digital control attenuator and outputting the signal to an external power amplifier; the communication module realizes the communication between the device and the power amplifier, the setting of the parameters of the device and the output of the calculation intermodulation value; the clock generation module generates reference clocks required by an analog-to-digital converter (ADC), an FPGA chip and a digital-to-analog converter (DAC);
the frequency of the signal which is output by the frequency conversion of the input mixer is within the sampling range of an analog-to-digital converter (ADC);
the amplitude of the signal converted and output by the first numerical control attenuator is in the sampling range of an analog-to-digital converter (ADC);
the output signal processed by the output signal frequency mixing and amplifier meets the frequency and amplitude required by the power amplifier input;
the FPGA chip comprises an analog-to-digital converter (ADC) interface module, an FFT module, a power detection module, an intermodulation calculation module, a two-tone signal generation module, a digital-to-analog converter (DAC) interface and an intermodulation value comparison and judgment module; the device comprises an analog-to-digital converter (ADC) interface module, an FFT module, an intermodulation calculation module, a intermodulation value comparison and judgment module, a communication module, a two-tone signal generation module and a digital-to-analog converter (DAC) interface which are sequentially connected, wherein the ADC interface module is connected with a power detection module; the realized functions comprise input signal power calculation, input signal frequency spectrum calculation, output power intermodulation value calculation, judgment of whether the grid voltage level value of the power amplification module is traversed or not, finding out the grid voltage level value corresponding to the intermodulation best point, writing the grid voltage level value into the power amplification module, and calculating the power amplification intermodulation value.
2. A power amplifier module intermodulation automatic debugging and testing method based on the device of claim 1, characterized by comprising the following steps:
step 1: setting parameters of output signals of the system through a communication module, wherein the parameters comprise the frequency of the output signals, the power of the signals and the interval frequency of the double-tone signals;
step 2: the double-tone signal generating module generates digital baseband double-tone signals corresponding to the parameters according to the double-tone signal interval frequency, and the digital baseband double-tone signals are sent to a digital-to-analog converter (DAC) through a DAC interface to convert the digital signals into analog signals; adjusting a second digital controlled attenuator behind a digital-to-analog converter (DAC) according to the set signal power parameter; setting local oscillation frequency of an output signal mixing and amplifier according to the set signal frequency parameter, and generating a required double-tone signal after mixing and amplifying;
and step 3: during debugging and testing, the connection mode is as follows: the output signal mixing and amplifier output port of the system is connected with the input port of the power amplifier module, and the output port of the power amplifier module is connected with the input port of the input mixer after passing through the attenuator; the communication ports are connected through a communication module;
and 4, step 4: inquiring the information of the power amplifier module through the communication module, if the information can be inquired normally, indicating that the power amplifier module works normally, and performing subsequent steps, if the inquiry of the power amplifier module is abnormal or no information is replied, indicating that the power amplifier module works abnormally or is not connected, and not performing subsequent steps;
and 5: setting a grid voltage level value for the power amplification module, then sampling an output signal of the power amplification module by an analog-to-digital converter (ADC), and sending the sampled output signal to an FPGA chip;
step 6: an analog-to-digital converter (ADC) interface module receives sampling data of the ADC and respectively sends the sampling data to a power detection module and an FFT module, the power detection module is used for calculating the power of an input signal, when the power of the input signal is overlarge, a first numerical control attenuator at the front end of the ADC is attenuated, the front end of the ADC is prevented from being overloaded, the power is also used for calculating the output power of a power amplification module, the FFT module is used for calculating the frequency spectrum of the input signal, the calculated output data is sent to an intermodulation calculation module, the intermodulation value of the output power is calculated, and the grid voltage level value and the corresponding intermodulation value are stored;
and 7: the intermodulation value comparison and judgment module judges whether the grid voltage level value of the power amplification module is traversed, if not, the grid voltage level value is changed and written into the power amplification module, and the step 6 is repeated; if the traversal is completed, entering step 8;
and 8: the intermodulation value comparison and judgment module finds out a grid voltage level value corresponding to the intermodulation best point, writes the grid voltage level value into the power amplifier module, the intermodulation calculation module calculates the power amplifier intermodulation value, the power amplifier intermodulation value is output from the communication module, and the debugging is finished.
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| CN110620554A (en) * | 2018-06-19 | 2019-12-27 | 广东技术师范学院 | 200Mhz bandwidth input frequency converter |
| CN111314835B (en) * | 2018-12-11 | 2022-07-26 | 华润微集成电路(无锡)有限公司 | Debugging system and method based on digital power amplifier chip |
| CN109743030B (en) * | 2018-12-28 | 2023-08-08 | 京信网络系统股份有限公司 | Power amplifier debugging system and method |
| US11476863B2 (en) | 2019-11-08 | 2022-10-18 | Analog Devices International Unlimited Company | Signal dependent reconfigurable data acquisition system |
| CN112995880A (en) * | 2021-01-18 | 2021-06-18 | 讯喆微电子(合肥)有限公司 | Automatic testing system and method for audio module |
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| CN102904652A (en) * | 2012-10-23 | 2013-01-30 | 三维通信股份有限公司 | Nonlinear detecting method of repeater power amplifier |
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| JP6448022B2 (en) * | 2014-09-12 | 2019-01-09 | 富士通コネクテッドテクノロジーズ株式会社 | Wireless communication apparatus, communication control method, and communication control program |
| US10103693B2 (en) * | 2015-09-30 | 2018-10-16 | Skyworks Solutions, Inc. | Power amplifier linearization system and method |
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| CN102904652A (en) * | 2012-10-23 | 2013-01-30 | 三维通信股份有限公司 | Nonlinear detecting method of repeater power amplifier |
| CN103957179A (en) * | 2014-04-04 | 2014-07-30 | 京信通信系统（中国）有限公司 | DPD achieving method and system |
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