CN107203676B

CN107203676B - Method for improving time sequence performance of integrated circuit design and data processing system

Info

Publication number: CN107203676B
Application number: CN201710482037.6A
Authority: CN
Inventors: 耿保林; 林哲民; 李翊; 李冰
Original assignee: Glenfly Tech Co Ltd
Current assignee: Glenfly Tech Co Ltd
Priority date: 2017-06-22
Filing date: 2017-06-22
Publication date: 2022-02-25
Anticipated expiration: 2037-06-22
Also published as: CN107203676A

Abstract

A method and data processing system for improving timing performance of an integrated circuit design, the method for improving timing performance of an integrated circuit design comprising: setting a plurality of established parameters related to time sequence performance and corresponding reference indexes; obtaining a timing analysis report related to an integrated circuit design, wherein the integrated circuit design comprises a plurality of paths and the timing analysis report comprises timing information of each path; determining at least one critical path from the paths according to the time sequence information; capturing a plurality of parameter values of the established parameters of at least one key path, and determining a plurality of abnormal parameters according to the parameter values and the corresponding reference indexes; generating a diagnosis result according to the abnormal parameters; and generating optimization suggestion information according to the diagnosis result, so that the time sequence performance of at least one critical path is improved according to the optimization suggestion information.

Description

Method for improving time sequence performance of integrated circuit design and data processing system

Technical Field

The present invention relates to timing analysis and diagnosis, and more particularly, to a method for improving timing performance of an integrated circuit design.

Background

Electronic design automation synthesis tools (EDA tools) are important aids in the development of today's semiconductor designs. Today, electronic design automation synthesis tools, in addition to assisting chip designers in handling over a million transistors, need to introduce appropriate algorithms to enhance circuit performance and reduce product development cost as semiconductor process technology and manufacturing flow progress.

In the design implementation process, after mapping, timing analysis needs to be performed on the delay of an actual functional block of a design and the estimated wiring delay, and after wiring is laid out, timing analysis needs to be performed on the delay of the functional block of the actual wiring and the actual wiring delay. Conventional EDA tools may provide timing reports of critical paths.

However, the conventional EDA tool can only provide a timing report of the critical path for a designer to refer to, cannot provide reasons why the timing performance cannot be improved, and cannot provide optimization suggestions.

Therefore, a method for automatically analyzing the reason why the timing cannot be promoted and giving optimization suggestion is needed.

Disclosure of Invention

In view of the foregoing, the present invention provides a method for improving timing performance of an integrated circuit design and a related data processing system.

An embodiment of the present invention provides a method for improving timing performance of an integrated circuit design, the method comprising: setting a plurality of established parameters related to time sequence performance and corresponding reference indexes; obtaining a timing analysis report related to the integrated circuit design, wherein the integrated circuit design includes a plurality of paths and the timing analysis report includes timing information for each of the paths; determining at least one critical path from the paths according to the timing information; capturing a plurality of parameter values of the predetermined parameters of the at least one critical path, and determining a plurality of abnormal parameters according to the parameter values and the corresponding reference indexes; generating a diagnosis result according to the abnormal parameters; and generating optimization suggestion information according to the diagnosis result, so that the time sequence performance of the at least one critical path is improved according to the optimization suggestion information.

Another embodiment of the present invention provides a data processing system, which at least includes a storage unit and a processor. The storage unit is used for storing a plurality of predetermined parameters related to the time sequence performance and corresponding reference indexes. The processor is coupled to the storage unit and configured to obtain a timing analysis report related to an integrated circuit design, wherein the integrated circuit design includes a plurality of paths and the timing analysis report includes timing information of each of the paths, determine at least one critical path from the paths according to the timing information, retrieve a plurality of parameter values of the predetermined parameters of the at least one critical path, determine a plurality of abnormal parameters according to the parameter values and the corresponding reference indicators, and generate a diagnosis result according to the abnormal parameters; and generating optimization suggestion information according to the diagnosis result, so that the time sequence performance of the at least one critical path is improved according to the optimization suggestion information.

The method of the present invention can be implemented by a device or system of the present invention, which is hardware or firmware for performing specific functions, or can be embodied in a recording medium by program code and implemented in combination with specific hardware. When the program code is loaded into and executed by an electronic device, processor, computer, or machine, the electronic device, processor, computer, or machine becomes an apparatus or system for practicing the invention.

Drawings

FIG. 1 is a diagram of a hardware architecture of a data processing system according to an embodiment of the present invention.

FIG. 2 is a diagram of a software architecture of a data processing system according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating a method for improving timing performance of an integrated circuit design according to an embodiment of the present invention.

FIG. 4 is a flowchart illustrating a method for improving timing performance of an integrated circuit design according to another embodiment of the present invention.

FIG. 5A is a diagram illustrating extraction of analysis parameters of an optimization tool according to an embodiment of the present invention.

FIG. 5B is a schematic diagram of analysis data of analysis parameters and reference indicators of the optimization tool according to the embodiment of the present invention.

FIG. 5C is a schematic diagram of analysis data of analysis parameters of an optimization tool according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating analysis data for analysis parameters of a logic design according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of analysis parameters of an optimization tool according to another embodiment of the present invention.

Wherein the symbols in the drawings are briefly described as follows:

100-a data processing system; 110 to a storage device; 120-processor; 130-display device; 210-a critical path capturing module; 220-parameter picking module; 230-optimization suggestion information generation module; s302, S304, S306, S308, S310; s402, S404, S406, S408, S410, S412, S414, S416; and 502, 504, 512, 514, 602, 604, 606 to parameter data.

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is noted that the embodiments described in this section are for illustrative purposes only and are not intended to limit the scope of the present disclosure, and that various modifications and changes may be made by those skilled in the art without departing from the spirit and scope of the present disclosure. It should be understood that the following embodiments may be implemented via software, hardware, firmware, or any combination of the preceding.

The embodiment of the invention provides an automatic method for extracting the time sequence performance parameters of a key path, diagnosing reasons and optimizing suggestions in the design of a digital integrated circuit, which can automatically extract required parameters from a time sequence report and a database, further automatically diagnose the reasons that the time sequence performance of the key path cannot be improved, find out the bottleneck of improving the time sequence performance and automatically give the optimizing suggestions.

FIG. 1 is a block diagram of a hardware architecture of a data processing system 100 according to an embodiment of the present disclosure. In some embodiments, the data processing system 100 may be a desktop computer, an All-In-One (AIO) computer, a tablet computer, a Mobile phone, a Mobile Internet Device (MID), a notebook computer, a car computer, a digital camera, a digital media player, a game Device or any other type of Mobile computing Device.

As shown in fig. 1, the hardware architecture of the data processing system 100 may at least include a storage device 110, a processor 120 and a display device 130. The storage device 110 is a non-transitory (non-transitory) computer readable storage medium, which may be a non-volatile storage medium (e.g., a Read-Only Memory (ROM), a Flash Memory (Flash Memory), a hard disk, an optical disk, etc.), a volatile storage medium (e.g., a Random Access Memory (RAM)), or any combination thereof, and is used to store related data, such as intermediate data and execution result data during operation. Storage device 110 may also be used to store a set of instructions and/or program code modules that may be executed by processor 120. Generally, program modules include routines, programs, objects, components, and the like. The storage device 110 may also store various items of data as needed, such as: parameters and their reference indexes, and a knowledge base including various reference optimization suggestions, and the like. The parameters are a set of parameters that may affect the timing performance, and the knowledge base includes a set of reference optimization suggestions corresponding to various abnormal reasons. In the invention, a plurality of parameters which may affect the time-series performance can be counted in advance according to experience, and a feasible scheme for solving the abnormal reason is provided as a reference optimization suggestion according to the past design experience or machine learning according to the abnormal reason represented by each parameter so as to construct and generate the knowledge base. For details of specific parameters and their reference indices, and reference optimization suggestions, refer to the following description of embodiments.

The processor 120 is coupled to the storage device 110 and the display device 130, and can load and execute the instruction set and/or the program code from the storage device 110 to control the operations of the storage device 110 and the display device 130 to perform the method for improving the timing performance according to the present invention. The Processor 120 may be a general purpose Processor, a Micro-Control Unit (MCU), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), or the like, and is configured to provide data analysis, Processing, and operation functions. The method for improving the time sequence performance comprises the following steps: a time sequence analysis report of a circuit design is obtained, corresponding abnormal parameters of each critical path in the time sequence analysis report are sequentially captured, and corresponding optimization suggestion information is generated according to abnormal reasons corresponding to the abnormal parameters, so that the time sequence performance of each critical path is improved through the optimization suggestion information, and the details of the optimization suggestion information are explained later.

It will be appreciated by those skilled in the art that the circuit logic within the processor 120 may generally include a plurality of transistors for controlling the operation of the circuit logic to provide the desired functionality and operation. Furthermore, the specific structure of the transistors and the connection relationship between the transistors are usually determined by a compiler, such as: a Register Transfer Language (RTL) compiler may be operated by the processor to compile instruction files (scripts) like combinatorial Language code into a form suitable for the design or fabrication of the circuit logic.

The display device 130 can display related data, such as text, graphics, interfaces, and/or various information such as displaying or presenting results. Display device 130 may be used to present screens of results, such as: liquid Crystal Displays (LCDs). It should be understood that, in some embodiments, the display device 130 is combined with a screen of a touch sensing device (not shown). The touch sensing device has a touch surface including at least one dimension of sensor to detect contact and motion on its surface of an input tool, such as a finger or stylus, near or on the touch surface. Therefore, the user can perform a touch input command or signal through the display device 130.

It should be understood that the components shown in fig. 1 are only used to provide an illustrative example and are not used to limit the scope of the present invention. For example, although not shown, the data processing system 100 may further include other functional units, such as: one or more buttons, a keyboard, a mouse, a touch pad, a video lens, a microphone, and/or a speaker, etc. for interacting with a user as a man-machine interface, and the invention is not limited thereto.

FIG. 2 shows a software architecture diagram of data processing system 100 according to an embodiment of the present invention. The software architecture of the data processing system 100 includes a critical path extraction module 210, a parameter extraction module 220, and an optimization suggestion information generation module 230. The critical path extraction module 210, the parameter extraction module 220, and the optimization suggestion information generation module 230 may be stored in a storage device 110 (e.g., a memory) of the data processing system 100, and may be loaded and executed by the processor 120 of the data processing system 100 at an appropriate time to perform the method for improving timing performance of the present invention.

Specifically, the processor 120 may control the operations of the critical path extraction module 210, the parameter extraction module 220, and the optimization suggestion information generation module 230 to perform the method for improving the timing performance according to the present invention. Specifically, the processor 120 may receive a timing analysis report related to a circuit design through the critical path retrieving module 210, determine one or more critical paths according to timing related information of a plurality of paths in the timing analysis report, retrieve all parameters of each critical path through the parameter retrieving module 220, compare parameter values of all parameters with corresponding reference indexes one by one, determine abnormal parameters with abnormality, regard the abnormal parameters as reasons hindering the improvement of timing performance through the optimization suggestion information generating module 230, and generate corresponding optimization suggestion information one by one according to the reasons, thereby improving the timing performance of each critical path. The parameter retrieving module 220 may first determine various parameters that may affect the timing sequence as the predetermined parameters according to experience and modeling, and then use the reasonable value range of each predetermined parameter as the corresponding reference index of the parameter value. For example, as it is known from experience that the timing performance may not be further improved due to the long length of the path, the bus length data indicating the actual bus length of a path may be used as one of the predetermined parameters, and a reasonable value range of the bus length may be used as its reference index, for example, the shortest routing length between a start point and an end point of the path may be set as a reference line length, and the ratio of the actual line length to the reference line length is used as the reference index. The optimization suggestion information generation module 230 may find a corresponding set of reference optimization suggestions from the knowledge base of the storage device 110 according to the anomaly cause corresponding to each anomaly parameter, and generate the optimization suggestion information by using the reference optimization suggestions.

It should be understood that each of the above-mentioned components or modules is a device having corresponding functions, and may have appropriate hardware circuits or components to perform the corresponding functions, however, the device is not limited to having entities, and may also be a virtual program or software having corresponding functions, or a device having the capability of processing and running the program or software. The operation of the above elements can be further described with reference to the following corresponding methods.

FIG. 3 is a flowchart illustrating a method for improving timing performance of an integrated circuit design according to an embodiment of the present invention. Please refer to fig. 1, fig. 2 and fig. 3. The method for improving timing performance of an integrated circuit design according to an embodiment of the present invention may be applied to a data processing system, for example, the data processing system 100 of FIG. 1, and executed by the processor 120. In this embodiment, it is assumed that the storage device 110 has preset a plurality of predetermined parameters related to the timing performance and their corresponding reference indicators.

First, in step S302, the processor 120 obtains a timing analysis report related to an integrated circuit design to be analyzed, wherein the integrated circuit design includes a plurality of paths and the timing analysis report includes a timing information of each path. In one embodiment, the timing analysis report may be provided by an EDA tool, and the processor 120 may receive the timing analysis report generated by the EDA tool. In another embodiment, the processor 120 may further include the EDA tool, so that the processor 120 may generate the timing analysis report.

After obtaining the timing analysis report, in step S304, the processor 120 determines at least one critical path from all paths according to the timing information of each path. Specifically, the timing analysis report includes timing information of a plurality of paths, and the processor 120 may compare the timing information of all paths in the timing analysis report with a predetermined standard timing information including a predetermined timing target, and determine a critical path according to a comparison result and a determination criterion. In one embodiment, a path may be considered as a critical path when the timing information of the path does not satisfy the predetermined timing target. In another embodiment, a path is considered as a critical path only when the timing information of the path does not satisfy the predetermined timing target and exceeds a predetermined range, but the invention is not limited thereto.

Next, in step S306, the processor 120 retrieves parameter values of a plurality of predetermined parameters of at least one critical path, and determines a plurality of abnormal parameters according to the parameter values and the corresponding reference indicators. In one embodiment, the predetermined parameter may include a first parameter, and the step of determining the abnormal parameter by the processor 120 according to a parameter value of the predetermined parameter and the corresponding reference indicator further includes: and comparing whether a first parameter value of the first parameter exceeds a first corresponding reference index of the first parameter, and if so, determining the first parameter as an abnormal parameter. Conversely, if the first parameter value of the first parameter does not exceed the first corresponding reference index of the first parameter, the first parameter may be considered as a normal parameter and may therefore be excluded.

Specifically, the processor 120 may determine a plurality of parameters that may affect the timing sequence according to experience and modeling, and use a reasonable value range of each parameter as a corresponding reference index of the parameter value, and compare the parameter value of each parameter with the corresponding reference index one by one to determine whether each parameter is abnormal, so as to obtain the abnormal parameter. Such parameters include, but are not limited to, at least one of: the circuit comprises a bus length data, a front-stage and rear-stage logic stage difference data, a transition time data, a unit density data, a wiring blocking degree data, a clock deviation data, an on-chip fluctuation data, a crosstalk delay data, a maximum driving capability unit proportion data and the like. For example, as experience shows that the timing performance may not be further improved due to the long length of the path, the bus length of the path may be used as one of the parameters, and the reasonable value range of the bus length is used as the reference index.

In one embodiment, the parameters may include a process library analysis parameter associated with a feature of a process library used for the integrated circuit design, a logic design analysis parameter associated with the logic design of the integrated circuit design, and an optimization tool analysis parameter associated with an EDA tool. For example, the process library analysis parameter may be maximum driving capability cell ratio data, the logic design analysis parameter may be a difference between the previous and next logic levels, and the optimization tool analysis parameter may be bus length data, transition time data, etc., but is not limited thereto. The excessive proportion of the maximum driving capability cells in the critical path indicates that the process library is not complete enough and cells with larger driving capability are lacked.

After determining all possible abnormal parameters, in step S308, the processor 120 generates a diagnosis result according to the possible abnormal parameters, and then, in step S310, the processor 120 generates an optimization suggestion message according to the diagnosis result. In some embodiments, the abnormal parameter includes a first parameter (e.g., bus length data) and a plurality of second parameters (e.g., cell density data, wiring blockage degree data, etc.) associated with the first parameter, and the step of generating the diagnosis result by the processor 120 according to the abnormal parameter further includes the step of generating a plurality of analysis information corresponding to the second parameter by the processor 120 and generating the diagnosis result corresponding to the first parameter according to the analysis information. In one embodiment, the abnormal parameter may be a process library analysis parameter and the processor 120 may generate optimization suggestion information for process library optimization based on the integrated circuit design according to the process library analysis parameter. In another embodiment, the exception parameter may be a logic design analysis parameter and the processor 120 may generate optimization suggestion information for logic design optimization based on the integrated circuit design according to the logic design analysis parameter. In another embodiment, the abnormal parameter may be an optimization tool analysis parameter and the processor 120 may generate the EDA tool angle-based optimization recommendation information according to the optimization tool analysis parameter.

Specifically, in steps S308 and S310, the processor 120 may further analyze various parameters related to the abnormal parameter, determine a reason for hindering the improvement of the timing performance, and find out a corresponding or similar set of reference optimization suggestions from the knowledge base according to the found reason to generate optimization suggestion information, so as to automatically provide corresponding optimization suggestions from various aspects such as optimization design, improvement of the process library, guidance of tool optimization, and the like, and a designer may adjust the design of each critical path according to the optimization suggestion information to make it conform to the reference index, thereby improving the timing performance of the entire integrated circuit design.

FIG. 4 is a flowchart illustrating a method for improving timing performance of an integrated circuit design according to another embodiment of the present invention. Please refer to fig. 1, fig. 2 and fig. 4. The method for improving timing performance of an integrated circuit design according to an embodiment of the present invention may be applied to a data processing system, for example, the data processing system 100 of FIG. 1, and executed by the processor 120. In this embodiment, it is assumed that the processor 120 has determined a plurality of critical paths from all paths in the timing analysis report according to the timing information of each path in the timing analysis report. For example, assuming that 10 paths out of 100 paths are shown in the timing analysis report, which do not satisfy the predetermined timing target, the 10 paths may be regarded as critical paths.

First, the processor 120 selects a critical path (step S402). Next, the processor 120 captures a parameter of the selected critical path (step S404), and compares whether the parameter exceeds the corresponding index (step S406), if so, it indicates that the parameter is abnormal, records the parameter as an abnormal parameter (step S408), and then executes step S410.

If the parameter does not exceed the corresponding index (No in step S406), which indicates that the parameter is normal, the processor 120 then executes step S410. In step S410, the processor 120 determines whether all the parameters have been checked. If the parameters are not checked (no in step S410), the aforementioned steps S404 to S408 are repeated to capture another parameter of the selected critical path and compare whether the parameter exceeds the corresponding index, if so, the parameter is recorded as an abnormal parameter until all the parameters are checked.

When all the parameters have been checked (yes at step S410), the processor 120 then lists all the abnormal parameters of the selected critical path (step S412) and lists the optimization suggestions of the selected critical path (step S414). Specifically, the processor 120 may find all possible abnormal parameters, generate a diagnosis result according to the possible abnormal parameters, generate an optimization suggestion information according to the diagnosis result, list all the abnormal parameters and list the optimization suggestion information as the optimization suggestion of the selected critical path through the display device 130, so as to provide the optimization suggestion for the relevant designer for reference and subsequent optimization.

Next, the processor 120 determines whether all critical paths have been checked (step S416). If there are still undetected critical paths (no in step S416), the processor 120 repeats the steps S402 to S414, selects the next critical path, then captures each parameter of the selected critical path one by one and compares with its corresponding index, records all abnormal parameters, lists all abnormal parameters of each selected critical path one by one and lists the optimization suggestion of the selected critical path until all critical paths are selected and the inspection is completed. When all the critical paths have been checked (yes in step S416), the whole flow ends.

The following is a detailed description of an embodiment of applying the method of the present invention to diagnose the performance improvement bottleneck of the CPU core timing sequence, which is used for performing diagnostic analysis such as parameter extraction, reason diagnosis and optimization suggestion on the timing sequence path. In this embodiment, the time sequence path is mainly diagnosed and analyzed by taking three parameters, i.e., the bus length, the difference between the logic levels of the previous stage and the next stage, and the transition time, as the example of the analysis parameter of the optimization tool and the analysis parameter of the logic design. The method mainly comprises three steps, namely parameter extraction, reason diagnosis and optimization suggestion.

In the first embodiment, the parameters are analysis parameters of an optimization tool, such as bus length data and corresponding cell density data, and wiring blockage level data. Because the timing performance cannot be further improved due to the fact that the line length is too long, whether the timing performance is affected by the line length can be judged according to the bus length data. First, the processor 120 extracts the actual bus length of path 1 from the design to obtain the parameter value of the bus length data, as indicated by the segment 502 in FIG. 5A. For convenience of illustration, it is assumed that the timing path of the critical path has a start point a and an end point B, and the position coordinates of the start point a are represented as (X1, Y1) and the position coordinates of the end point B are represented as (X2, Y2). Next, the reference line length is calculated from the starting point a and the ending point B of the timing path, as indicated by the line segment 504 in fig. 5A. Specifically, as shown in fig. 5A, since the shortest trace length from the start point a to the end point B of the timing path is | X2-X1| + | Y2-Y1|, the shortest trace length can be selected as the reference line length (the reference index of the bus length data). When the actual line length is longer than the reference line length (for example, the actual line length is longer than 1.5 times of the reference line length), it indicates that there may be a winding detour (detour) phenomenon, which may result in that the timing performance cannot be further improved, and needs to be corrected by a designer. For example, a route 1 is selected, and the position coordinates of the start point a are (853,342), and the position coordinates of the end point B are (1168,547). The calculated reference line length is 520 micrometers (um) and the actual line length of path 1 extracted from the design is 1205 micrometers (um). Fig. 5B is a schematic diagram of analysis data of analysis parameters and reference indicators of the optimization tool according to the embodiment of the invention, in which the horizontal axis represents time sequence (slack) and the vertical axis represents path line length. In this example, since the actual line length (512 in fig. 5B) is greater than 1.5 times the reference line length (514 in fig. 5B), i.e. the bus length parameter is greater than the reference index, it is known that the bus length data of path 1 is one of the abnormal parameters. Conversely, in another embodiment, if the actual line length is not greater than 1.5 times the reference line length, the bus length data of path 1 is considered as the normal parameter.

Then, the processor 120 performs a cause diagnosis according to the abnormal parameter to generate a diagnosis result. In this example, for route 1, it can be determined that the winding detour is one of the reasons that the timing performance of the route cannot be further improved, and then the reason for the winding detour is further analyzed. The parameters corresponding to the exception parameter "bus length data" include a standard density (STD density) data and a wiring congestion degree (congestion) data. The standard density data represents the standard density in a rectangular frame surrounded by A, B points, and if the value of the standard density data is larger, the standard density at the position is represented to be larger, so that the winding detour phenomenon is caused if the standard density data is too large; the wiring blockage parameter indicates the density of the wiring between A, B points, and if the value of the wiring blockage parameter is larger, the local blockage is serious, and the winding detour phenomenon is caused. Fig. 5C is a diagram of analysis data of analysis parameters of an optimization tool according to an embodiment of the present invention, wherein the horizontal axis represents time sequence (slack) and the vertical axis represents standard density. In this example, by grabbing the standard density (STD density) in a rectangular box surrounded by point A, B, the standard density in the rectangular box was found to be 93% higher than 80% of the reference value (empirically chosen reference value). That is, the standard density of the positions of the paths is too high, which causes the winding detour phenomenon. Thus, the processor 120 generates a diagnosis result with the corresponding exception parameter "bus length data" that the local standard density at path 1 is too high, reaching 93%, causing winding detour ".

The processor 120 may then generate optimization suggestion information for path 1 for reference by the designer based on the diagnostic results. In this example, the optimization suggestion information may include the following optimization suggestion information based on EDA tool angles: "suggest: (1) adjusting the floorplan around the region to reduce the local standard density (853,342) (1168,547); and/or (2) { (853,342) (1168,547) } areas set the maximum standard density constraint ". Therefore, the designer can simply refer to the optimization suggestion information, reduce the local standard density near the region { (853,342) (1168,547) } and/or set the maximum standard density constraint and other design modes to solve the abnormality caused by the problem of too long line length of the path 1, thereby improving the time sequence performance of the path 1.

In the second embodiment, the parameter is a logic design analysis parameter such as a previous and subsequent logic level difference data. Because the logic stage number is too long, the time sequence performance can not be further improved, and therefore whether the time sequence performance is influenced by the imbalance of the logic stage numbers of the front and rear stages can be judged according to the difference data of the logic stage numbers of the front and rear stages. Fig. 6 is a diagram illustrating analysis data of analysis parameters of a logic design according to an embodiment of the present invention, wherein the horizontal axis represents timing (slack) and the vertical axis represents logic progression. As shown in fig. 6, to obtain the difference data of the logical levels of the previous and subsequent stages, the logical levels of the previous stage (N-1) (shown as a curve 602 in fig. 6), the current stage (N) (shown as a curve 604 in fig. 6), and the subsequent stage (N +1) (shown as a curve 606 in fig. 6) of the selected time-series path are extracted respectively. For example, for the path 2, the level (N-1) of the previous stage is 16, the level (N) of the current stage is 30, and the level (N +1) of the next stage is 22. In this example, the level (N) -level (N-1) ═ 30-16 ═ 14 and the level (N) -level (N +1) ═ 30-22 ═ 8 of the route 2, and therefore, the difference between the logical stage numbers of the preceding and following stages is the largest difference between the two, i.e., 14 stages. Since the difference between the logical levels of the previous and subsequent stages of the path 2 exceeds the reference index 10 stage, it can be known that the difference data between the logical levels of the previous and subsequent stages of the path 2 is one of the abnormal parameters.

Then, the processor 120 performs a cause diagnosis according to the abnormal parameter to generate a diagnosis result. In this example, for path 2, the processor 120 may determine that the imbalance in the number of logic stages is one of the reasons for the inability of the timing performance of the path to be further improved. Then, a diagnosis result that the corresponding abnormality parameter regarding the path 2 is "difference data of logical stage numbers of preceding and following stages" is "imbalance of the path 2 with the logical stage numbers of the preceding and following stages", 16/30/22 ".

The processor 120 may then generate optimization suggestion information for path 2 for the designer's reference based on the diagnostic results. In this example, the optimization suggestion information may include the following information for logic design optimization based on the integrated circuit design: "suggest: please redesign the pipeline at path 2 to equalize the logic order ".

In a third embodiment, the parameter is another optimization tool analysis parameter such as transition time (transition time) data. Similarly, the time delay is too large due to too long transition time, so that the timing performance cannot be further improved, and therefore, whether the timing performance is affected by too long transition time can be determined according to the transition time data. Fig. 7 is a diagram illustrating analysis parameters of an optimization tool according to an embodiment of the present invention, wherein the horizontal axis represents timing (slack) and the vertical axis represents transition time. In order to obtain the transition time data, transition time values at each pin in the path to be analyzed are respectively extracted, and 80ps is empirically selected as a reference transition time (reference index). For example, assuming that for Path 3, the transition time at pin u509/i0 is 116ps, which is greater than the reference transition time 80ps, the transition time data for Path 3 can be considered one of the exception parameters.

For path 3, processor 120 may determine one of the reasons why the transition time is too long to further improve the timing performance of the path, and then generate a diagnosis result regarding the abnormal parameter including path 3 as "transition time at u509/i0 is too large, 116 ps" in path 3. Processor 120 may then generate the following EDA tool angle-based optimization recommendation information for path 3 based on the above diagnostic results for the designer's reference: "suggest: (1) check the maximum transition time constraint at u509/i 0; (2) the wire length at u509/i0 is reduced; (3) the driving capacity of the driving unit of u509/i0 is increased; (4) add drive unit before u509/i0 ".

Therefore, according to the method for improving the time sequence performance of the integrated circuit design and the related data processing system thereof, the parameter extraction of the critical path can be automatically carried out according to the time sequence analysis report of the integrated circuit design, the reason for hindering the improvement of the time sequence performance of the critical path can be quickly and automatically diagnosed, the optimization suggestion is given from the aspects of the design, the process library, the tool optimization capability and the like, and the user is guided to quickly and efficiently carry out the correction optimization, so that the time and the labor are obviously saved.

The method of the present invention, or a specific form or part thereof, may be in the form of program code. The program code may be embodied in tangible media, such as floppy diskettes, cd-roms, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine thereby becomes an apparatus for practicing the invention. The program code may also be transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented in a general-purpose image processor, the program code combines with the image processor to provide a unique apparatus that operates analogously to application specific logic circuits.

The above description is only for the preferred embodiment of the present invention, and it is not intended to limit the scope of the present invention, and any person skilled in the art can make further modifications and variations without departing from the spirit and scope of the present invention, therefore, the scope of the present invention should be determined by the claims of the present application.

Claims

1. A method for improving timing performance of an integrated circuit design, the method comprising:

setting a plurality of established parameters related to time sequence performance and corresponding reference indexes;

obtaining a timing analysis report for the integrated circuit design, wherein the integrated circuit design includes a plurality of paths and the timing analysis report includes timing information for each of the paths;

automatically determining at least one critical path from the paths according to the timing information;

automatically capturing a plurality of parameter values of the predetermined parameter of the at least one critical path, and determining a plurality of abnormal parameters of the at least one critical path according to the parameter values and the corresponding reference indexes;

generating a diagnosis result of the at least one critical path according to the abnormal parameters; and

generating optimization suggestion information for the at least one critical path according to the diagnosis result, so as to improve the timing performance of the at least one critical path according to the optimization suggestion information, wherein the optimization suggestion information is composed of at least one operation step, and comprises the optimization suggestion information based on EDA tool angle or the optimization suggestion information based on logic design optimization of the integrated circuit design;

wherein the abnormal parameter comprises a first parameter, the predetermined parameter comprises the first parameter and a plurality of second parameters related to the first parameter, and the step of generating the diagnosis result of the at least one critical path according to the abnormal parameter further comprises:

generating a plurality of analysis information corresponding to the second parameter; and

generating the diagnosis result corresponding to the first parameter according to the analysis information.

2. The method of claim 1, wherein the anomaly parameters include process library analysis parameters related to characteristics of a process library used for the integrated circuit design, logic design analysis parameters related to a logic design of the integrated circuit design, and optimization tool analysis parameters related to an EDA tool.

3. The method of claim 2, further comprising:

and generating the optimization suggestion information based on the optimization of the process library of the integrated circuit design according to the process library analysis parameters.

4. The method of claim 2, further comprising:

and generating the optimization suggestion information based on the logic design optimization of the integrated circuit design according to the logic design analysis parameters.

5. The method of claim 2, further comprising:

generating the optimization suggestion information based on the EDA tool angle according to the optimization tool analysis parameters.

6. The method of claim 1, wherein the predetermined parameter comprises at least one of: the circuit comprises bus long data, front-stage and rear-stage logic stage difference data, transition time data, unit density data, wiring blocking degree data, clock deviation data, on-chip fluctuation data, crosstalk delay data and maximum driving capability unit proportion data.

7. The method of claim 1, wherein the predetermined parameter comprises a first parameter, and the step of determining the abnormal parameter of the at least one critical path according to the parameter value and the corresponding reference index further comprises:

comparing whether a first parameter value of the first parameter exceeds a first corresponding reference index of the first parameter; and

if so, the first parameter is determined to be the abnormal parameter.

8. A data processing system, characterized by comprising at least:

the storage unit is used for storing a plurality of established parameters related to the time sequence performance and corresponding reference indexes; and

a processor, coupled to the storage unit, for obtaining a timing analysis report related to an integrated circuit design, wherein the integrated circuit design includes a plurality of paths and the timing analysis report includes timing information of each of the paths, determining at least one critical path from the paths according to the timing information, retrieving a plurality of parameter values of the predetermined parameters of the at least one critical path, determining a plurality of abnormal parameters of the at least one critical path according to the parameter values and the corresponding reference indicators, and generating a diagnosis result of the at least one critical path according to the abnormal parameters; and generating optimization suggestion information for the at least one critical path according to the diagnosis result, thereby improving the timing performance of the at least one critical path according to the optimization suggestion information, wherein the optimization suggestion information is composed of at least one operation step including the optimization suggestion information based on EDA tool angle or the optimization suggestion information based on logic design optimization of the integrated circuit design,

the abnormal parameter includes a first parameter, the predetermined parameter includes the first parameter and a plurality of second parameters related to the first parameter, and the processor further generates a plurality of analysis information corresponding to the second parameter and generates the diagnosis result corresponding to the first parameter according to the analysis information.

9. The data processing system of claim 8, further comprising a display device coupled to the processor for displaying the diagnosis result including the abnormal parameter and the optimization suggestion information.

10. The data processing system of claim 8, wherein the exception parameters include process library analysis parameters related to used process library characteristics of the integrated circuit design, logic design analysis parameters related to a logic design of the integrated circuit design, and optimization tool analysis parameters related to EDA tools.

11. The data processing system of claim 10, wherein the exception parameter is a library analysis parameter, and the processor further generates the optimization suggestion information based on library optimization of the integrated circuit design based on the library analysis parameter.

12. The data processing system of claim 10, wherein the exception parameter is the logic design analysis parameter, and the processor further generates the optimization suggestion information based on a logic design optimization of the integrated circuit design based on the logic design analysis parameter.

13. The data processing system of claim 10, wherein the anomaly parameters are optimization tool analysis parameters, and the processor further generates the optimization recommendation information based on the EDA tool angle based on the optimization tool analysis parameters.

14. The data processing system of claim 8, wherein the predetermined parameter comprises at least one of: the circuit comprises bus long data, front-stage and rear-stage logic stage difference data, transition time data, unit density data, wiring blocking degree data, clock deviation data, on-chip fluctuation data, crosstalk delay data and maximum driving capability unit proportion data.