CN107154788B - L-shaped impedance matching system and method in radio frequency energy acquisition circuit - Google Patents
L-shaped impedance matching system and method in radio frequency energy acquisition circuit Download PDFInfo
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Abstract
The invention relates to an L-shaped impedance matching system and method in a radio frequency energy acquisition circuit, wherein the system comprises a sampling comparison module, a logic algorithm control module and an adjustable impedance matching network; the sampling comparison module is used for continuously sampling the voltage output by the voltage doubling rectifying circuit twice under the control of the logic control module and comparing the voltages sampled twice continuously; the logic algorithm control module is used for gradually adjusting the number of the L-shaped adjustable capacitor arrays merged into the adjustable impedance matching network according to the comparison result of the voltages sampled for two times; the adjustable impedance matching network is used for matching the impedance between the antenna and the voltage-multiplying rectifying circuit according to the number of the incorporated L-shaped adjustable capacitor arrays. The invention obtains the current impedance matching effect by judging the output voltage of the voltage doubling rectifying circuit, avoids a complex ADC sampling or signal processing unit, has simple circuit and extremely low power consumption, consumes energy only in the switching process and is suitable for a weak energy acquisition environment.
Description
Technical Field
The invention relates to a system and a method for impedance matching in an energy acquisition circuit, in particular to a system and a method for matching L-shaped impedance in a radio frequency energy acquisition circuit.
Background
Due to the rapid development of Wireless Sensor Networks (WSNs), Body Area Networks (BANs), and internet of things (IoT), wireless sensor nodes are widely utilized. In order to realize uninterrupted measurement, the sensing node needs to have longer standby time, but the service life of the sensing node is limited by the bottleneck of battery technology. In order to solve the problem of power supply of the sensing node, a wireless energy collection technology is widely developed, and the wireless energy collection technology collects wireless energy to provide a power supply for the sensing node so as to achieve the purpose of prolonging the working time of a circuit or passively working.
The energy collecting circuit generally consists of four parts, as shown in fig. 1, the energy collecting circuit comprises an antenna, an impedance matching circuit, a voltage doubling rectifying circuit and an energy storage capacitor. The antenna is used as a radio frequency energy source in the system and is responsible for inducing electromagnetic waves, and the impedance of the antenna does not change after the antenna is designed. The voltage doubling rectifying circuit has the function of rectifying and boosting weak electromagnetic waves sensed by the antenna, and the impedance of the voltage doubling rectifying circuit is related to the signal frequency and the input power. Since the input end of the voltage-doubling rectifying circuit is usually connected with a capacitor in parallel or in series, the impedance of the voltage-doubling rectifying circuit is related to the frequency; when the output power of the voltage-doubling rectifying circuit is changed, the voltage output by the voltage-doubling rectifying circuit is changed, and the working state of an MOSFET in the voltage-doubling rectifying circuit is also changed, so that the impedance is changed.
In the field of radio frequency energy transmission, the following formula is obtained according to energy transmission: the energy transfer efficiency is maximum when the source impedance is equal to the real part of the load impedance and the imaginary part is opposite. However, in practical use, the impedance of the voltage-doubling rectifying circuit is not matched with the impedance of the antenna, which causes energy reflection and reduces the conversion efficiency, so that an impedance matching circuit is required to match the antenna with the voltage-doubling rectifying circuit, thereby improving the energy collection efficiency.
The conventional impedance matching circuit has a plurality of structures, such as a pi-type structure shown in fig. 2-1 and an L-type structure shown in fig. 2-2, which are common, and perform impedance matching for a specific frequency signal, and can only achieve single-point matching, generally matching at the lowest energy point. The energy collecting circuit does not aim at a specific frequency signal, and the energy collecting circuit needs to have higher energy collecting efficiency in a wider frequency band, so that the traditional impedance matching circuit does not meet the use requirement of the energy collecting circuit.
In addition, some automatic impedance matching systems currently exist, but these methods are also not applicable to energy harvesting circuits due to the following problems.
The photovoltaic power generation field utilizes dynamic impedance equivalent matching to realize maximum power point tracking control (MPPT) (see specifically photovoltaic power generation maximum power point tracking control based on dynamic equivalent impedance matching, Zheng Ying, Wang Ping, Zhangxia, China Motor engineering newspaper, vol. 31, No. 2, 15/1/2011). The system is shown in fig. 3: dynamic equivalent impedance measurement of the photovoltaic cell panel is realized through the current detection circuit, the voltage detection circuit and the signal processing circuit, and the power converter is controlled to realize maximum power tracking. The problems that exist if it is applied to a wireless energy harvesting circuit are:
1. the source end impedance of the wireless energy collecting circuit, namely the antenna impedance, is not changed, and the current system state cannot be determined by measuring the internal resistance of the antenna;
the MPPT system achieves the purpose of impedance matching by regulating and controlling a power converter, and a voltage-multiplying rectifying circuit in an energy collecting circuit cannot be dynamically regulated generally.
The MPPT system is not suitable for use in an energy harvesting circuit.
The field of wireless power transmission utilizes radio to transmit power energy, which also requires impedance matching circuits for maximum energy transmission (see in particular: an automatic impedance matching control device for high power wireless power transmission devices, application No. 201410326172.8, application No. 2014.07.10). The system is shown in fig. 4: the power monitoring system comprises a processor unit, a power monitoring unit, a switch array unit and a matching network unit. The power monitoring unit of the system comprises a coupler and two detectors, wherein the forward power and the reflected power passing through the coupler are respectively detected by the two detectors, and a voltage signal which is in direct proportion to the power is output. The two detector voltages are sampled by the ADC and the current transmission efficiency is calculated by the calculation unit, after which the matching network parameters are changed by an algorithm to change the impedance. But this system is not suitable for energy harvesting circuits for the following reasons:
1. the system needs a coupler for detecting the forward power signal and the reflected power signal, however, the component can not be integrated by using a CMOS (complementary metal oxide semiconductor) process, and the complexity of the system is increased;
2. the system is too complex, firstly, an ADC (analog to digital converter) is required to sample a voltage signal, then, a processor unit is used for calculating the current transmission efficiency, and then, the matching network is controlled to change until the efficiency meets the program requirement, so that the method has higher power consumption and cannot be applied to a weak energy collection system;
3. the system uses a relay as a control unit, suitable for high power transmission, but in the energy harvesting circuit, the harvested energy is not sufficient to control the relay and the like.
The automatic impedance matching system for transmission lines mentioned in the automatic impedance matching system for transmission lines (application No. 201110353777.2, application No. 2011.11.09) is also not applicable to the present system. The system utilizes the amplitude phase detector, the mutual inductor and the A/D converter to detect the voltage value and the current value of the radio frequency signal, then sends the sampling result to the control module for calculation, and then controls the motor to change the matching network. The method also faces the problems of complex system, incapability of integrating and large power consumption, and cannot be applied to weak energy collection circuits.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an L-shaped impedance matching system and method in a radio frequency energy acquisition circuit, which can dynamically adjust the impedance of a weak energy collection circuit when a larger frequency range and a circuit working state change, so that the load impedance and the internal impedance of an antenna are matched with each other, and the maximum power collection is realized.
The technical scheme for solving the technical problems is as follows: the invention relates to an L-shaped impedance matching system in a radio frequency energy acquisition circuit, wherein the radio frequency energy acquisition circuit comprises an antenna for receiving radio frequency signals and a voltage doubling rectifying circuit for rectifying and boosting the radio frequency signals received by the antenna;
the sampling comparison module is used for continuously sampling the voltage output by the voltage doubling rectifying circuit twice under the control of the logic control module and comparing the voltages sampled twice continuously;
the logic algorithm control module is used for gradually adjusting the number of the L-shaped adjustable capacitor arrays merged into the adjustable impedance matching network according to the comparison result of the voltages sampled for two times;
the adjustable impedance matching network is used for matching impedance between the antenna and the voltage-multiplying rectification circuit according to the number of the incorporated L-shaped adjustable capacitor arrays.
The invention has the beneficial effects that: the L-shaped impedance matching system in the radio frequency energy acquisition circuit has the following beneficial effects,
1. the current impedance matching effect is obtained by judging the output voltage of the voltage doubling rectifying circuit, a complex ADC sampling or signal processing unit is avoided, the circuit is simple, the power consumption is extremely low, the energy is consumed only in the switching process, and the method is particularly suitable for a weak energy acquisition environment;
2. the sampling comparison module does not need high-gain elements such as an operational amplifier and the like, so that the power consumption is reduced, and the complexity of system design is reduced;
3. the logic algorithm control module adjusts the adjustable impedance matching network successively according to the feedback of the sampling comparison module and the thought of successive approximation, so that the matching effect is improved, and automatic regulation and control are realized;
4. the invention can use standard CMOS process, realize full integration, and reduce production cost.
On the basis of the technical scheme, the invention can be further improved as follows.
The system further comprises a low starting voltage oscillator, an energy storage capacitor is connected to the output end of the voltage doubling rectifying circuit, a clock signal input end is arranged on the logic algorithm control module, the input end of the low starting voltage oscillator is connected to the common end between the voltage doubling rectifying circuit and the energy storage capacitor, and the output end of the low starting voltage oscillator is connected to the clock signal input end of the logic algorithm control module and used for providing a clock signal for the logic algorithm control module.
The beneficial effect of adopting the further scheme is that: and the low starting voltage oscillator provides a clock signal for the logic algorithm control module to ensure the logic algorithm control module to work normally.
Furthermore, the adjustable impedance matching network further comprises a fixed inductor L and a fixed capacitor CfixOne end of the fixed inductor L is electrically connected with the antenna, and the other end of the fixed inductor L is electrically connected with the fixed capacitor CfixIs electrically connected at one end thereof, toThe fixed capacitor CfixThe other end of the L-shaped adjustable capacitor array is electrically connected with the input end of the voltage doubling rectifying circuit, and the L-shaped adjustable capacitor array is electrically connected with the fixed capacitor CfixParallel connection;
the L-shaped adjustable capacitor array comprises n adjustable capacitors connected in parallel, and the size of each of the n adjustable capacitors connected in parallel is 2n-1C to C, each adjustable capacitor is respectively connected with an adjustable switch in series, and n adjustable switches are respectively switches bn-1To switch b0；
And the logic algorithm control module is provided with n-bit switch control output ends, and the n-bit switch control output ends are correspondingly associated with the n adjustable switches and used for controlling the on-off of the n adjustable switches.
The beneficial effect of adopting the further scheme is that: the adjustable capacitor in the adjustable impedance matching network adopts binary weighting, and the large-range impedance regulation and control can be realized by using the capacitor with a small number of digits.
Further, the sampling comparison module comprises a sampling hold unit and a comparator, the sampling hold unit comprises a negative input end sampling hold circuit and a positive input end sampling hold circuit, a sampling comparison signal input end is arranged on the logic algorithm control module, the input end of the negative input end sampling hold circuit and the input end of the positive input end sampling hold circuit are connected on the output end of the voltage-multiplying rectification module, the output end of the negative input end sampling hold circuit is connected on the negative input end of the comparator, the output end of the positive input end sampling hold circuit is connected on the positive input end of the comparator, and the output end of the comparator is connected with the sampling comparison signal input end of the logic algorithm control module.
The beneficial effect of adopting the further scheme is that: because the invention is used for weak energy acquisition circuits, the overall power consumption of the system must be in a lower level, so that a circuit with direct current power consumption cannot be adopted in the system, wherein the comparator has high comparison speed because of the strong positive feedback contained in the comparator, and only has little direct current power consumption in the switching process, thereby being particularly suitable for the system of the invention.
Furthermore, the negative input end sample-and-hold circuit and the positive input end sample-and-hold circuit are symmetrical,
the negative input end sample-and-hold circuit comprises a switch S1, a capacitor C1, a switch S3, a capacitor C3 and a switch Sdivide1One end of the switch S1 is connected to the output end of the voltage-doubling rectifying circuit, the other end of the switch S1 is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, one end of the switch S3 is grounded, the other end of the switch S3 is connected to the negative input end of the comparator, one end of the capacitor C3 is grounded, the other end of the capacitor C3 is connected to the negative input end of the comparator, and the switch S3 is connected to the negative input end of the comparatordivide1Is connected to the common terminal between the switch S1 and the capacitor C1, the switch Sdivide1The other end of the comparator is connected with the negative input end of the comparator;
the positive input sample-and-hold circuit comprises a switch S2, a capacitor C2, a switch S4, a capacitor C4 and a switch Sdivide2One end of the switch S2 is connected to the output end of the voltage-doubling rectifying circuit, the other end of the switch S2 is connected to one end of the capacitor C2, the other end of the capacitor C2 is grounded, one end of the switch S4 is grounded, the other end of the switch S4 is connected to the positive input end of the comparator, one end of the capacitor C4 is grounded, the other end of the capacitor C4 is connected to the positive input end of the comparator, and the switch S4 is connected to the positive input end of the comparatordivide2Is connected to the common terminal between the switch S2 and the capacitor C2, the switch Sdivide2And the other end of the same is connected with the positive input end of the comparator.
The beneficial effect of adopting the further scheme is that: the negative input end sample-and-hold circuit and the positive input end sample-and-hold circuit can collect voltage values output by the voltage-multiplying rectification circuit, and can convey the voltage values after voltage division to the comparator, so that the situation that the voltage obtained by sampling is too high to exceed the input range of the comparator is prevented.
Furthermore, the system of the invention also comprises a delay module, wherein the delay module comprises a first signal delay buffer and a second signal delay buffer, and the logic algorithm control module is provided with an En _ div signal output end and an onA switch S1 control signal output end and a switch S2 control signal output end, wherein the input end of the first signal delay buffer is connected with the En _ div signal output end of the logic algorithm control module, and the output end of the first signal delay buffer is connected with the switch S of the sample hold unitdivide1And switch Sdivide2Associated for controlling said switch Sdivide1And switch Sdivide2The output end of the first signal delay buffer is further connected to the input end of the second signal delay buffer, the output end of the second signal delay buffer is connected to the enable end of the comparator, the switch S1 of the logic algorithm control module controls the signal output end to be associated with the switch S1 of the sample and hold unit for controlling the on/off of the switch S1, and the switch S2 of the logic algorithm control module controls the signal output end to be associated with the switch S2 of the sample and hold unit for controlling the on/off of the switch S2.
The beneficial effect of adopting the further scheme is that: the delay module is composed of two cascaded delay buffers and is used for delaying control signals and preventing the comparator from judging errors due to jitter noise of the signals generated at the moment of closing the switch.
Based on the L-shaped impedance matching system in the radio frequency energy acquisition circuit, the invention also provides an impedance matching method in the radio frequency energy acquisition circuit.
A method for matching L-shaped impedance in a radio frequency energy acquisition circuit, which utilizes the L-shaped impedance matching system in the radio frequency energy acquisition circuit to match the impedance in the radio frequency energy acquisition circuit, comprises the following steps,
and 3, matching the impedance between the antenna and the voltage-multiplying rectification circuit by the adjustable impedance matching network according to the number of the incorporated L-shaped adjustable capacitor arrays.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the step 1 is specifically that,
step 11, the sampling comparison module performs primary sampling on the voltage output by the voltage doubling rectifying circuit under the control of the logic control module;
step 12, the logic control module controls to turn on one bit of the adjustable switch in the adjustable impedance matching network, and adjusts the number of the L-shaped adjustable capacitor arrays incorporated in the adjustable impedance matching network;
step 13, the sampling comparison module carries out secondary sampling on the voltage output by the voltage doubling rectifying circuit under the control of the logic control module;
and 14, the sampling comparison module compares the voltage sampled for the first time with the voltage sampled for the second time under the control of the logic control module to obtain a comparison result of the voltages sampled for two times continuously.
Further, the step 2 is specifically that the logic control module performs algorithm judgment according to a comparison result of voltages sampled twice continuously, and judges whether to reserve the one-bit adjustable switch controlled to be turned on in the step 12.
Further, the judgment criterion of whether to reserve the adjustable switch which is controlled to be turned on in the step 12 is that,
if the voltage sampled for the second time is greater than the voltage sampled for the first time, the operation of the adjustable switch which is controlled to be opened in the step 12 is reserved;
and if the voltage sampled for the second time is less than the voltage sampled for the first time, the operation of the adjustable switch which controls the opening of the bit in the step 12 is cancelled.
Drawings
FIG. 1 is a block diagram of a prior art energy harvesting circuit;
FIG. 2-1 is a diagram of a prior art pi impedance matching circuit;
FIG. 2-2 is a diagram of a prior art T-impedance matching circuit;
FIG. 3 is a block diagram of a dynamic impedance equivalent matching structure in the field of photovoltaic power generation in the prior art;
FIG. 4 is a block diagram of a prior art wireless power transmission system utilizing wireless power to transmit power energy;
FIG. 5 is a block diagram of an L-shaped impedance matching system in an RF energy harvesting circuit according to the present invention;
FIG. 6 is a schematic diagram of the overall circuit structure of an L-shaped impedance matching system in the RF energy harvesting circuit according to the present invention;
FIG. 7 is a schematic diagram of an adjustable impedance matching network in an L-shaped impedance matching system of a radio frequency energy harvesting circuit according to the present invention;
FIG. 8 is a block diagram of a sample-and-hold unit of an L-impedance matching system in an RF energy harvesting circuit according to the present invention;
FIG. 9 is a timing diagram illustrating the operation of the logic algorithm control module in the L-impedance matching system of the RF energy harvesting circuit according to the present invention;
FIG. 10 is a general flowchart of an L-impedance matching method in an RF energy harvesting circuit according to the present invention;
fig. 11 is a specific schematic diagram of an L-type impedance matching method in the rf energy harvesting circuit according to the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 5, an L-shaped impedance matching system in a radio frequency energy harvesting circuit: the radio frequency energy acquisition circuit comprises an antenna for receiving radio frequency signals and a voltage doubling rectifying circuit for rectifying and boosting the radio frequency signals received by the antenna; the system comprises a sampling comparison module, a logic algorithm control module and an adjustable impedance matching network, wherein the adjustable impedance matching network comprises an L-shaped adjustable capacitor array; the sampling comparison module is used for continuously sampling the voltage output by the voltage doubling rectifying circuit twice under the control of the logic control module and comparing the voltages sampled twice continuously; the logic algorithm control module is used for gradually adjusting the number of the L-shaped adjustable capacitor arrays merged into the adjustable impedance matching network according to the comparison result of the voltages sampled for two times; the adjustable impedance matching network is used for matching impedance between the antenna and the voltage-multiplying rectification circuit according to the number of the incorporated L-shaped adjustable capacitor arrays.
In this embodiment, as shown in fig. 6, the system of the present invention further includes a low start-up voltage oscillator, an output end of the voltage doubling rectifying circuit is connected to an energy storage capacitor, the logic algorithm control module is provided with a clock signal input end, an input end of the low start-up voltage oscillator is connected to a common end between the voltage doubling rectifying circuit and the energy storage capacitor, an output end of the low start-up voltage oscillator module is connected to the clock signal input end of the logic algorithm control module, and the low start-up voltage oscillator outputs a clock signal clk for providing a clock signal to the logic algorithm control module. Low start-up voltage oscillator
In this embodiment, as shown in fig. 7, the adjustable impedance matching network further includes a fixed inductor L and a fixed capacitor CfixOne end of the fixed inductor L is electrically connected with the antenna, and the other end of the fixed inductor L is electrically connected with the fixed capacitor CfixIs electrically connected to the fixed capacitor CfixThe other end of the L-shaped adjustable capacitor array is electrically connected with the input end of the voltage doubling rectifying circuit, and the L-shaped adjustable capacitor array is electrically connected with the fixed capacitor CfixParallel connection; specifically, the L-shaped adjustable capacitor array includes n adjustable capacitors connected in parallel, and the size of each of the n adjustable capacitors connected in parallel is 2n-1C to C, each adjustable capacitor is respectively connected with an adjustable switch in series, and n adjustable switches are respectively switches bn-1To switch b0(ii) a The logic algorithm control module is provided with n-bit switch control output ends, and the n-bit switch control output ends are correspondingly associated with the n adjustable switches and are used for controlling the on-off of the n adjustable switches。
In the system of the present invention, the operation principle of the adjustable impedance matching network is as follows: adjustable switch bi(i-0, 1, … … n-1) is off by default, and at initial power-up, the fixed inductor L and the fixed capacitor C are both offfixThe traditional L-shaped impedance matching circuit is formed to match the antenna with the voltage doubling rectifying circuit, and at the moment, the fixed inductor L or the fixed capacitor CfixThe size of the (D) can be measured by using an experimental network analyzer; the L-shaped impedance matching circuit performs primary matching on the antenna and the voltage-multiplying rectifying circuit, and parameters are not necessarily the optimal matching in the current environment; when other modules of the system work normally, the logic algorithm control module can sequentially adjust the adjustable switches b corresponding to the L-shaped adjustable capacitor array in the adjustable impedance matching networkn-1～b0The value of the adjustable impedance matching network is changed by adjusting the size of the parallel capacitor in the L-shaped matching network. And the adjustable switches corresponding to the L-shaped adjustable capacitor array are sequentially switched on under the control of an algorithm, and the optimal value of the voltage-multiplying rectification output under the using condition is searched.
In the adjustable impedance matching network, a fixed inductor L and a fixed capacitor CfixAnd forming a basic L-shaped impedance matching circuit for performing primary matching on the antenna and the voltage doubling rectifying circuit. The capacitors in the L-shaped adjustable capacitor array are formed by binary weighting, and are combined under the control of the logic algorithm control module on the adjustable switch, and the number of the capacitors connected in parallel in the L-shaped impedance matching circuit is adjusted, so that the matching point of the adjustable impedance matching network is changed, and large-range adjustment can be realized through a small number of digits.
In this embodiment, as shown in fig. 6, the sampling comparison module includes a sampling hold unit and a comparator, the sampling hold unit includes a negative input sampling hold circuit and a positive input sampling hold circuit, the logic algorithm control module is provided with a sampling comparison signal input end, an input end of the negative input sampling hold circuit and an input end of the positive input sampling hold circuit are connected to the output end of the voltage-multiplying rectification module, an output end of the negative input sampling hold circuit is connected to the negative input end of the comparator, an output end of the positive input sampling hold circuit is connected to the positive input end of the comparator, and an output end of the comparator is connected to the sampling comparison signal input end of the logic algorithm control module.
Specifically, as shown in fig. 8, the negative input sample-and-hold circuit and the positive input sample-and-hold circuit are symmetrical: the negative input end sample-and-hold circuit comprises a switch S1, a capacitor C1, a switch S3, a capacitor C3 and a switch Sdivide1One end of the switch S1 is connected to the output end of the voltage-doubling rectifying circuit, the other end of the switch S1 is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, one end of the switch S3 is grounded, the other end of the switch S3 is connected to the negative input end of the comparator, one end of the capacitor C3 is grounded, the other end of the capacitor C3 is connected to the negative input end of the comparator, and the switch S3 is connected to the negative input end of the comparatordivide1Is connected to the common terminal between the switch S1 and the capacitor C1, the switch Sdivide1The other end of the comparator is connected with the negative input end of the comparator; the positive input sample-and-hold circuit comprises a switch S2, a capacitor C2, a switch S4, a capacitor C4 and a switch Sdivide2One end of the switch S2 is connected to the output end of the voltage-doubling rectifying circuit, the other end of the switch S2 is connected to one end of the capacitor C2, the other end of the capacitor C2 is grounded, one end of the switch S4 is grounded, the other end of the switch S4 is connected to the positive input end of the comparator, one end of the capacitor C4 is grounded, the other end of the capacitor C4 is connected to the positive input end of the comparator, and the switch S4 is connected to the positive input end of the comparatordivide2Is connected to the common terminal between the switch S2 and the capacitor C2, the switch Sdivide2And the other end of the same is connected with the positive input end of the comparator.
In the sampling comparison module, because the sampling and holding unit has a network at each of the positive input end and the negative input end of the comparator, the negative input end sampling and holding circuit and the positive input end sampling and holding circuit in the sampling and holding unit are completely symmetrical (the switch S1 is symmetrical to the switch S2, the capacitor C1 is symmetrical to the capacitor C2, the switch S3 is symmetrical to the switch S4, and the capacitor C3 is symmetrical to the capacitor C3538)C4 is symmetrical, and two S are arranged in a dotted line framedivideSwitches, respectively switch Sdivide1And switch Sdivide2) Therefore, in this embodiment, only the negative input sample-and-hold circuit is taken as an example for explanation, and the specific explanation is as follows: one end of the switch S1 is connected with the output of the voltage-doubling rectifying circuit, the other end is connected with the capacitor C1, and the capacitor C1 is used for storing the voltage output by the voltage-doubling rectifying circuit; one end of the capacitor C3 is grounded, and the other end is connected with the negative input end of the comparator and is used for dividing the voltage stored on the capacitor C1 to prevent the voltage sampled by the C1 from being too high to exceed the input range of the comparator; one end of the switch S3 is grounded, the other end is connected with the negative input end of the comparator, the switch S3 is used for discharging the capacitor C3 in the sampling period, and the control signal of the switch S3 is the same as that of the switch S1; switch Sdivide1One end of the constant-volume capacitor is connected with the common end of the switch S1 and the capacitor C1, the other end of the constant-volume capacitor is connected with the negative input end of the comparator, the negative input end is used for disconnecting the capacitor C1 and the capacitor C3 in a sampling period and connecting the constant-volume capacitor C1 and the capacitor C3 in a voltage division period to carry out voltage division.
In the sampling comparison module, a clock-controlled latching comparator is used as a comparator, and the comparator has three input ports and one output port; the positive and negative inputs of the comparator are used for inputting comparison signals, the enable end (comp) is used for controlling when the comparison operation is initiated, and the output end outputs the comparison result.
In the system of the invention, the working principle of the comparator is as follows: because the system of the invention is used for a weak energy acquisition circuit, the whole power consumption of the system must be in a lower level, so the system of the invention cannot adopt a circuit with direct current power consumption, wherein a clock-controlled reproducible comparator has strong positive feedback inside so that the comparison speed is high, and only a small amount of direct current power consumption exists in the switching process, thereby being particularly suitable for the invention.
In this embodiment, as shown in fig. 6, the system of the present invention further includes a delay module, where the delay module includes a first signal delay buffer and a second signal delay buffer, the logic algorithm control module is provided with an En _ div signal output terminal, a switch S1 control signal output terminal, and a switch S2 control signal output terminal, and the second signal delay buffer is provided with a second signal delay buffer, and the second signal delay buffer is connected to the second signal delay bufferThe input end of a signal delay buffer is connected with the En _ div signal output end of the logic algorithm control module, and the output end of the first signal delay buffer is connected with the switch S of the sampling and holding unitdivide1And switch Sdivide2Associated for controlling said switch Sdivide1And switch Sdivide2The output end of the first signal delay buffer is further connected to the input end of the second signal delay buffer, the output end of the second signal delay buffer is connected to the enable end of the comparator, the switch S1 of the logic algorithm control module controls the signal output end to be associated with the switch S1 of the sample and hold unit for controlling the on/off of the switch S1, and the switch S2 of the logic algorithm control module controls the signal output end to be associated with the switch S2 of the sample and hold unit for controlling the on/off of the switch S2. The first signal delay buffer and the second signal delay buffer are used for generating signal delay and preventing signal burrs caused by on-off of a switch in the comparator from influencing a comparison result.
In the system of the present invention, the operation principle of the delay module is as follows: the main purpose of delaying is to consider the reliability, and En _ div signal output by the logic algorithm control module passes through the first signal delay buffer and then is used as a control signal to control the switch Sdivide1And switch Sdivide2And then the voltage is used as a control signal to control the comparator to judge the sampling values of the two voltages before and after passing through the second signal delay buffer, wherein the part shown in the dashed line frame of FIG. 9 is the time sequence of the control signal, if the switch S2 is turned on and the switch S is turned offdivide2The two switches may be turned on simultaneously, and the VDD _ RECT output from the voltage-doubler rectification circuit is directly turned on to the ground, which causes a great waste of energy, so that the system of the present invention turns on the switch S after the switch S2 is turned on and a time delay is provideddivide2And carrying out partial pressure operation. In the same way, when the switch Sdivide1And switch Sdivide2After the switch-on, the capacitor C1 shares charges with the capacitor C3, the capacitor C2 and the capacitor C4, and the voltage is in the conversion stage, the output voltage is unstable, and if the comparator judgment operation is performed at this time, an error may occurJudging the phenomenon, therefore, at the switch Sdivide1And switch Sdivide2After the switch-on, the comparator is controlled to carry out judgment operation after a period of time is delayed, so that the reliability of the judgment result of the comparator is ensured; but the total time of delay can not exceed one clock cycle, thus preventing the system from judging wrongly.
In the system, the logic algorithm control module is mainly used for realizing the functions of controlling the working state jump, controlling the switch time sequence of the sampling comparison module and selecting the adjustable impedance matching network switch according to the voltage comparison result fed back; the algorithm idea is as follows: the output of the primary voltage doubling rectifying circuit is sampled by the sampling and holding unit before the adjustable impedance matching network is adjusted, then the one-bit adjustable switch is adjusted, the output voltage of the primary voltage doubling rectifying circuit is stably controlled and controlled by the sampling and holding unit, and then the output of the primary voltage doubling rectifying circuit is sampled by the sampling and holding unit, and then the logic algorithm control module judges according to the sampling results of two times: if the output voltage of the voltage doubling rectifying circuit rises, the attempt is proved to be an effective attempt, and the adjustment of the matching network switch is reserved; if the output voltage of the voltage doubling rectifying circuit drops, the attempt is proved to be an invalid attempt, and the adjustment of the matching network switch is cancelled.
In the system of the present invention, the working principle of the logic algorithm control module is as follows: (the operation of the logic algorithm control module is explained below with reference to FIG. 9)
As shown in fig. 9, the logic algorithm control module mainly implements functions of controlling working state skip, controlling a sampling and holding unit switch timing sequence, and selecting an adjustable switch in the adjustable impedance matching network according to a voltage comparison result fed back;
before dashed line ①, the system of the present invention is in a reset state, all control signals are set to zero, and all switches are in an open state;
on the first clock rising edge after reset, the logic algorithm control module sets the switch S1 control signal high, and controls the switch S1 to be switched on;
on the second rising edge of the clock, the logic algorithm control module sets the control signal of the high switch S2 and controls the n-bit switchControl signal, control switch S2 and switch biSwitching on;
on the third clock rising edge, the logic algorithm control module sets the En _ div signal high to control the switch Sdivide1And switch Sdivide2Switching on;
on the fourth clock rising edge, the logic algorithm control module judges b according to the comp output level of the comparatoriIf it is valid, if the terminal comp of the comparator is 1, b is maintainediLet b be 1 if the output comp of the comparator is 0i0; the operation is a cycle, a one-bit adjustable switch in the adjustable impedance matching network is determined after the cycle, the work is repeated, the rest adjustable switches in the adjustable impedance matching network are sequentially determined by utilizing the algorithm idea of successive approximation, and after the working states of all the adjustable switches are determined, the impedance matching network achieves the optimal matching and the energy transmission efficiency is highest.
The system mainly solves the defects that the traditional impedance matching circuit can only realize single-point matching or the traditional automatic matching circuit has complex structure, high power consumption, no integration and the like. The system utilizes feedback to realize automatic control, and the sampling and holding unit is used for sampling the output voltage of the voltage-multiplying rectifying circuit to obtain a voltage signal which is in direct proportion to the impedance matching degree; the comparator is used for comparing the two sampling voltages; the logic algorithm control module is used for determining the number of the L-shaped adjustable capacitor arrays in the adjustable impedance matching network according to the result of the comparator.
Based on the L-shaped impedance matching system in the radio frequency energy acquisition circuit, the invention also provides an L-shaped impedance matching method in the radio frequency energy acquisition circuit.
As shown in fig. 10, a method for matching L-type impedance in a rf energy harvesting circuit, which matches impedance in the rf energy harvesting circuit by using the L-type impedance matching system in the rf energy harvesting circuit, includes the following steps,
and 3, matching the impedance between the antenna and the voltage-multiplying rectification circuit by the adjustable impedance matching network according to the number of the incorporated L-shaped adjustable capacitor arrays.
In particular, the method comprises the following steps of,
the step 1 is specifically that the step of the method is carried out,
step 11, the sampling comparison module performs primary sampling on the voltage output by the voltage doubling rectifying circuit under the control of the logic control module;
step 12, the logic control module controls to turn on one bit of the adjustable switch in the adjustable impedance matching network, and adjusts the number of the L-shaped adjustable capacitor arrays incorporated in the adjustable impedance matching network;
step 13, the sampling comparison module carries out secondary sampling on the voltage output by the voltage doubling rectifying circuit under the control of the logic control module;
and 14, the sampling comparison module compares the voltage sampled for the first time with the voltage sampled for the second time under the control of the logic control module to obtain a comparison result of the voltages sampled for two times continuously.
Specifically, in the step 2, the logic control module performs algorithm judgment according to a comparison result of voltages sampled twice continuously, and judges whether to reserve the one-bit adjustable switch controlled to be turned on in the step 12. Wherein, the judgment standard of whether to reserve the adjustable switch which is controlled to be opened in the step 12 is as follows,
if the voltage sampled for the second time is greater than the voltage sampled for the first time, the operation of the adjustable switch which is controlled to be opened in the step 12 is reserved;
and if the voltage sampled for the second time is less than the voltage sampled for the first time, the operation of the adjustable switch which controls the opening of the bit in the step 12 is cancelled.
The specific operation of the method of the present invention will be described with reference to FIG. 11.
As shown in fig. 11, the antenna receives the electromagnetic wave energy in the air, and after the electromagnetic wave energy is primarily matched by the adjustable impedance matching network, the electromagnetic wave energy is input into the voltage-doubling rectifying circuit (which is not necessarily matched to an optimal state at this time), the voltage-doubling rectifying circuit obtains a voltage on the energy-storage capacitor after working for a period of time, when the voltage on the energy-storage capacitor is higher than the start threshold of the low start-up voltage oscillator, the low start-up voltage oscillator starts working 80, a clock signal clk is output to the logic algorithm control module, and the logic algorithm control module starts working formally; after the logic algorithm control module is powered on, all registers are cleared, all switches are disconnected, and then a formal adjustment process is started, wherein the specific adjustment process is as follows (described with reference to fig. 9):
when the first clock active edge is on, the logic algorithm control module controls the sample-and-hold unit to perform the first sampling operation (specifically, refer to fig. 8), the logic algorithm control module controls the switch S1 to be turned on, the capacitor C1 is charged, and the capacitor C3 is discharged; after a clock period is stable, the voltage of the capacitor C1 is the same as the output VDD _ RECT of the voltage doubling rectifying circuit, and the voltage of the capacitor C3 is discharged to zero potential;
the logic algorithm control module temporarily adjusts a one-bit adjustable switch in the adjustable impedance matching network when the effective edge of the second clock comes, changes the matching point in the adjustable impedance matching network, and then the output of the voltage-multiplying rectifying circuit is changed;
the logic algorithm control module performs the second sampling operation while adjusting the one-bit adjustable switch (specifically, referring to fig. 8), and the logic algorithm control module controls the switch S1 to be turned off, controls the switch S2 to be turned on, and enables the one-bit adjustable switch b in the adjustable impedance matching network to be turned oniMatching attempt is performed with the voltage value equal to 1 (the output of the voltage-doubling rectifying circuit is changed due to the change of the value of the matching network, and after a period of time stabilization, the voltage on the capacitor C2 is the same as the voltage value output by the voltage-doubling rectifying circuit after the adjustment of the adjustable impedance matching network, and the voltage of the capacitor C4 is discharged to zero potential);
the logic algorithm control module performs voltage division and comparison operations when a third clock effective edge comes: specifically, the logic algorithm control module controls the switch S2 to be switched off, the En _ div signal is set high, and the switch S is controlled after the En _ div signal is delayed by the first signal delay bufferdivide1And switch Sdivide2When the capacitor C3 and the capacitor C4 are turned on, because they are discharged to zero potential, the voltages stored in the capacitor C1 and the capacitor C2 are divided to an appropriate value and then sent to the input end of the comparator for comparison; in addition, after the En _ div signal is delayed by the first signal delay buffer and is also delayed by the second signal delay buffer, an enable is given to the comparator, the comparator is controlled to compare the voltages sampled twice before and after, and a comp comparison signal is output;
the logic algorithm control module judges the logic algorithm when the effective edge of the fourth clock comes: if the output end comp of the comparator is equal to 1, the adjustable switch b of the adjustable impedance matching network is switched oniThen the output voltage of the voltage doubling rectifying circuit rises, and the attempt is proved to be favorable for matching and is reserved; if the output terminal comp of the comparator is equal to 0, the attempt is proved to be not favorable for impedance matching, and the switch biIs set to zero. And at the moment, after the adjustment of one adjustable switch in the matching network is finished, the logic control module repeats the operation under the control of the clock to adjust the next adjustable switch, and the process is circulated until all the adjustable switches are adjusted.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (6)
1. An L-shaped impedance matching system in a radio frequency energy acquisition circuit, wherein the radio frequency energy acquisition circuit comprises an antenna for receiving radio frequency signals and a voltage doubling rectifying circuit for rectifying and boosting the radio frequency signals received by the antenna, and the L-shaped impedance matching system is characterized in that: the device comprises a sampling comparison module, a logic algorithm control module and an adjustable impedance matching network, wherein the adjustable impedance matching network comprises an L-shaped adjustable capacitor array;
the sampling comparison module is used for continuously sampling the voltage output by the voltage doubling rectifying circuit twice under the control of the logic control module and comparing the voltages sampled twice continuously;
the logic algorithm control module is used for gradually adjusting the number of the L-shaped adjustable capacitor arrays merged into the adjustable impedance matching network according to the comparison result of the voltages sampled for two times;
the adjustable impedance matching network is used for matching the impedance between the antenna and the voltage-multiplying rectifying circuit according to the number of the incorporated L-shaped adjustable capacitor arrays;
the adjustable impedance matching network also comprises a fixed inductor L and a fixed capacitor CfixOne end of the fixed inductor L is electrically connected with the antenna, and the other end of the fixed inductor L is electrically connected with the fixed capacitor CfixIs electrically connected to the fixed capacitor CfixThe other end of the L-shaped adjustable capacitor array is electrically connected with the input end of the voltage doubling rectifying circuit, and the L-shaped adjustable capacitor array is electrically connected with the fixed capacitor CfixParallel connection;
the L-shaped adjustable capacitor array comprises n adjustable capacitors connected in parallel, and the size of each of the n adjustable capacitors connected in parallel is 2n- 1C to C, each adjustable capacitor is respectively connected with an adjustable switch in series, and n adjustable switches are respectively switches bn-1To switch b0；
The logic algorithm control module is provided with n-bit switch control output ends, and the n-bit switch control output ends are correspondingly associated with the n adjustable switches and used for controlling the on-off of the n adjustable switches;
the L-shaped impedance matching system in the radio frequency energy acquisition circuit matches the impedance in the radio frequency energy acquisition circuit, and the method comprises the following steps:
step 1, the sampling comparison module continuously samples the voltage output by the voltage doubling rectifying circuit twice under the control of the logic control module and compares the voltages sampled twice continuously;
the step 1 is specifically that the step of the method is carried out,
step 11, the sampling comparison module performs primary sampling on the voltage output by the voltage doubling rectifying circuit under the control of the logic control module;
step 12, the logic control module controls to turn on one bit of the adjustable switch in the adjustable impedance matching network, and adjusts the number of the L-shaped adjustable capacitor arrays incorporated in the adjustable impedance matching network;
step 13, the sampling comparison module carries out secondary sampling on the voltage output by the voltage doubling rectifying circuit under the control of the logic control module;
step 14, the sampling comparison module compares the voltage sampled for the first time with the voltage sampled for the second time under the control of the logic control module to obtain a comparison result of the voltages sampled for the two consecutive times;
step 2, the logic algorithm control module gradually adjusts the number of the L-shaped adjustable capacitor arrays merged into the adjustable impedance matching network according to the comparison result of the voltages sampled for two times;
specifically, in the step 2, the logic control module performs algorithm judgment according to a comparison result of voltages sampled twice continuously, and judges whether to reserve the one-bit adjustable switch controlled to be turned on in the step 12;
the judgment criterion of whether to keep the adjustable switch which is controlled to be opened in the step 12 is that,
if the voltage sampled for the second time is greater than the voltage sampled for the first time, the operation of the adjustable switch which is controlled to be opened in the step 12 is reserved;
if the voltage sampled for the second time is less than the voltage sampled for the first time, the operation of controlling the opened one bit of the adjustable switch in the step 12 is cancelled;
after a cycle, determining a one-bit adjustable switch in the adjustable impedance matching network, then repeating the work, sequentially determining the rest adjustable switches in the adjustable impedance matching network by utilizing the algorithm idea of successive approximation, and after the working states of all the adjustable switches are determined, the impedance matching network achieves the optimal matching at the moment, so that the energy transmission efficiency is highest;
and 3, matching the impedance between the antenna and the voltage-multiplying rectification circuit by the adjustable impedance matching network according to the number of the incorporated L-shaped adjustable capacitor arrays.
2. The L-impedance matching system in a radio frequency energy harvesting circuit of claim 1, wherein: the low-start-up voltage oscillator is connected with an energy storage capacitor on the output end of the voltage doubling rectifying circuit, a clock signal input end is arranged on the logic algorithm control module, the input end of the low-start-up voltage oscillator is connected with the voltage doubling rectifying circuit and the public end between the energy storage capacitors, and the output end of the low-start-up voltage oscillator is connected on the clock signal input end of the logic algorithm control module and used for providing a clock signal for the logic algorithm control module.
3. An L-impedance matching system in a radio frequency energy harvesting circuit according to claim 1 or 2, wherein: the sampling comparison module comprises a sampling holding unit and a comparator, the sampling holding unit comprises a positive input end sampling holding circuit and a negative input end sampling holding circuit, a sampling comparison signal input end is arranged on the logic algorithm control module, the input end of the negative input end sampling holding circuit and the input end of the positive input end sampling holding circuit are connected on the output end of the voltage-multiplying rectification module, the output end of the negative input end sampling holding circuit is connected on the negative input end of the comparator, the output end of the positive input end sampling holding circuit is connected on the positive input end of the comparator, and the output end of the comparator is connected with the sampling comparison signal input end of the logic algorithm control module.
4. An L-impedance matching system in a radio frequency energy harvesting circuit according to claim 3, wherein: the negative input end sample-and-hold circuit and the positive input end sample-and-hold circuit are symmetrical,
the negative input end sample-and-hold circuit comprises a switch S1, a capacitor C1, a switch S3, a capacitor C3 and a switch Sdivide1One end of the switch S1 is connected to the output end of the voltage-doubling rectifying circuit, the other end of the switch S1 is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, one end of the switch S3 is grounded, the other end of the switch S3 is connected to the negative input end of the comparator, one end of the capacitor C3 is grounded, the other end of the capacitor C3 is connected to the negative input end of the comparator, and the switch S3 is connected to the negative input end of the comparatordivide1Is connected to the common terminal between the switch S1 and the capacitor C1, the switch Sdivide1The other end of the comparator is connected with the negative input end of the comparator;
the positive input sample-and-hold circuit comprises a switch S2, a capacitor C2, a switch S4, a capacitor C4 and a switch Sdivide2One end of the switch S2 is connected to the output end of the voltage-doubling rectifying circuit, the other end of the switch S2 is connected to one end of the capacitor C2, the other end of the capacitor C2 is grounded, one end of the switch S4 is grounded, the other end of the switch S4 is connected to the positive input end of the comparator, one end of the capacitor C4 is grounded, the other end of the capacitor C4 is connected to the positive input end of the comparator, and the switch S4 is connected to the positive input end of the comparatordivide2Is connected to the common terminal between the switch S2 and the capacitor C2, the switch Sdivide2And the other end of the same is connected with the positive input end of the comparator.
5. The L-impedance matching system in a radio frequency energy harvesting circuit of claim 4, wherein: still include the time delay module, the time delay module includes first signal time delay buffer and second signal time delay buffer, be equipped with En _ div signal output part, switch S1 control signal output part and switch S2 control signal output part on the logic algorithm control module, the input of first signal time delay buffer with En _ div signal output part of logic algorithm control module links to each other, the output of first signal time delay buffer with the switch S of sample hold unitdivide1And switch Sdivide2Is connected to control theSwitch Sdivide1And switch Sdivide2The output end of the first signal delay buffer is further connected to the input end of the second signal delay buffer, the output end of the second signal delay buffer is connected to the enable end of the comparator, the switch S1 of the logic algorithm control module controls the signal output end to be associated with the switch S1 of the sample and hold unit for controlling the on/off of the switch S1, and the switch S2 of the logic algorithm control module controls the signal output end to be associated with the switch S2 of the sample and hold unit for controlling the on/off of the switch S2.
6. An L-shaped impedance matching method in a radio frequency energy acquisition circuit is characterized in that: matching the impedance of a radio frequency energy harvesting circuit using the L-impedance matching system of the radio frequency energy harvesting circuit of any one of claims 1 to 5, comprising the steps of,
step 1, the sampling comparison module continuously samples the voltage output by the voltage doubling rectifying circuit twice under the control of the logic control module and compares the voltages sampled twice continuously;
the step 1 is specifically that the step of the method is carried out,
step 11, the sampling comparison module performs primary sampling on the voltage output by the voltage doubling rectifying circuit under the control of the logic control module;
step 12, the logic control module controls to turn on one bit of the adjustable switch in the adjustable impedance matching network, and adjusts the number of the L-shaped adjustable capacitor arrays incorporated in the adjustable impedance matching network;
step 13, the sampling comparison module carries out secondary sampling on the voltage output by the voltage doubling rectifying circuit under the control of the logic control module;
step 14, the sampling comparison module compares the voltage sampled for the first time with the voltage sampled for the second time under the control of the logic control module to obtain a comparison result of the voltages sampled for the two consecutive times;
step 2, the logic algorithm control module gradually adjusts the number of the L-shaped adjustable capacitor arrays merged into the adjustable impedance matching network according to the comparison result of the voltages sampled for two times;
specifically, in the step 2, the logic control module performs algorithm judgment according to a comparison result of voltages sampled twice continuously, and judges whether to reserve the one-bit adjustable switch controlled to be turned on in the step 12;
the judgment criterion of whether to keep the adjustable switch which is controlled to be opened in the step 12 is that,
if the voltage sampled for the second time is greater than the voltage sampled for the first time, the operation of the adjustable switch which is controlled to be opened in the step 12 is reserved;
if the voltage sampled for the second time is less than the voltage sampled for the first time, the operation of controlling the opened one bit of the adjustable switch in the step 12 is cancelled;
after a cycle, determining a one-bit adjustable switch in the adjustable impedance matching network, then repeating the work, sequentially determining the rest adjustable switches in the adjustable impedance matching network by utilizing the algorithm idea of successive approximation, and after the working states of all the adjustable switches are determined, the impedance matching network achieves the optimal matching at the moment, so that the energy transmission efficiency is highest;
and 3, matching the impedance between the antenna and the voltage-multiplying rectification circuit by the adjustable impedance matching network according to the number of the incorporated L-shaped adjustable capacitor arrays.
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| CN113408685B (en) * | 2021-06-02 | 2023-02-03 | 西安电子科技大学 | Radio frequency energy acquisition system based on energy management and passive radio frequency tag |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101854151A (en) * | 2010-05-31 | 2010-10-06 | 广州市广晟微电子有限公司 | Frequency tuning method and system for transconductance-capacitance filter |
| CN101874347A (en) * | 2007-11-27 | 2010-10-27 | 高通股份有限公司 | Methods and apparatuses for inductor tuning in radio frequency integrated circuits |
| CN103166595A (en) * | 2011-12-09 | 2013-06-19 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Impedance matcher, semiconductor equipment and impedance matching method |
| CN104242481A (en) * | 2014-07-10 | 2014-12-24 | 丁文萍 | Automatic impedance matching control device for high-power wireless power transmission device |
| CN104577328A (en) * | 2015-01-22 | 2015-04-29 | 山东大学 | RFID antenna and automatic matching method thereof |
| CN105577138A (en) * | 2015-12-08 | 2016-05-11 | 天津津航计算技术研究所 | Self-adaptive dynamic impedance matching method |
| CN105826994A (en) * | 2016-03-19 | 2016-08-03 | 复旦大学 | Radio frequency energy acquisition system based on dynamic impedance matching technology |
| CN106411272A (en) * | 2011-12-29 | 2017-02-15 | Mks仪器有限公司 | Power Distortion-Based Servo Control Systems for Frequency Tuning RF Power Sources |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101831871B1 (en) * | 2010-12-22 | 2018-02-27 | 인텔렉추얼디스커버리 주식회사 | Wireless energy collection apparatus and wireless electronic label adopting the same |
-
2017
- 2017-04-21 CN CN201710266417.6A patent/CN107154788B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101874347A (en) * | 2007-11-27 | 2010-10-27 | 高通股份有限公司 | Methods and apparatuses for inductor tuning in radio frequency integrated circuits |
| CN101854151A (en) * | 2010-05-31 | 2010-10-06 | 广州市广晟微电子有限公司 | Frequency tuning method and system for transconductance-capacitance filter |
| CN103166595A (en) * | 2011-12-09 | 2013-06-19 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Impedance matcher, semiconductor equipment and impedance matching method |
| CN106411272A (en) * | 2011-12-29 | 2017-02-15 | Mks仪器有限公司 | Power Distortion-Based Servo Control Systems for Frequency Tuning RF Power Sources |
| CN104242481A (en) * | 2014-07-10 | 2014-12-24 | 丁文萍 | Automatic impedance matching control device for high-power wireless power transmission device |
| CN104577328A (en) * | 2015-01-22 | 2015-04-29 | 山东大学 | RFID antenna and automatic matching method thereof |
| CN105577138A (en) * | 2015-12-08 | 2016-05-11 | 天津津航计算技术研究所 | Self-adaptive dynamic impedance matching method |
| CN105826994A (en) * | 2016-03-19 | 2016-08-03 | 复旦大学 | Radio frequency energy acquisition system based on dynamic impedance matching technology |
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