CN107154405B - Via etch method of the metal from appearance touch base plate - Google Patents
Via etch method of the metal from appearance touch base plate Download PDFInfo
- Publication number
- CN107154405B CN107154405B CN201710322780.5A CN201710322780A CN107154405B CN 107154405 B CN107154405 B CN 107154405B CN 201710322780 A CN201710322780 A CN 201710322780A CN 107154405 B CN107154405 B CN 107154405B
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- Prior art keywords
- touch
- via hole
- metal
- control
- grid line
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- 239000002184 metal Substances 0.000 title claims abstract description 67
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 238000000465 moulding Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 4
- 230000008859 change Effects 0.000 abstract description 9
- 230000008569 process Effects 0.000 abstract description 7
- 239000010409 thin film Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Position Input By Displaying (AREA)
Abstract
The invention discloses the via etch methods that metal holds touch base plate certainly, under the premise of not increasing additional technique process, by change mask structure or change TFT (thin film transistor) structure, improves metal from touch base plate touch-control via hole is held and overlap bad problem.Scheme is first is that the structure for passing through change mask plate, for processing the photoresist of setting setting thickness between the figure of touch-control via hole and touch-control binding metal i.e. on mask plate, make grid line via hole and touch-control via hole while the molding that is etched, so as to will cause hole forming bad for the difference in thickness for avoiding two types via hole excessive.Another scheme be by touch-control bind metal back layer place data wire metal buffer layer, improve existing touch-control via hole cross quarter cause to overlap bad phenomenon.
Description
Technical field
The present invention relates to a kind of via etch methods, and in particular to a kind of via etch for holding touch base plate certainly for metal
Method.
Background technique
TFT-LCD (thin film transistor LCD) is established from technical products, structure is held in existing horizontal electricity
On the basis of field driving LCD.Horizontal component of electric field is formed by pixel electrode and the public electrode of top layer, liquid crystal in box is driven to carry out partially
Turn, realizes display function.With the development of display technology, FIC, that is, embedded touch control technology becomes mainstream, by placing in TFT
Touch-control metal routing detects the capacitance variations between cabling, touch function can be realized.
Touch-control metal routing is placed in TFT, and main function is to detect the capacitance variations after finger touch, detects change
After change, signal is drawn out to touch-control IC from touch-control binding metal, touch-control IC determines the position that touch action occurs.The technology it is excellent
Point is that structure is simple, can be directly integrated in TFT technique.But the introducing of touch-control metal routing, especially touch-control binding gold
Dry etching is needed to form via hole on category.And dry etching depth is different, and touch-control via hole is be easy to cause to overlap bad situation.
Metal holds the structure of touch base plate as indicated with 1 certainly, which is that seven exposure mask cases (are completed to make using seven exposure masks
Make technique), comprising: 12 → source-drain layer of grid line 2 → active layer, 11 → pixel electrode (i.e. source electrode 5 and drain electrode 6 in Fig. 1) → touch-control
8 → via layer of routing layer (including grid line via hole 13 and touch-control via hole 14) → public electrode 16.Wherein, in via layer, shape is needed
At touch-control via hole 14 and grid line via hole 13, touch-control via hole 14 is processed with a thickness of 3000A in second insulating layer 10.Grid line via hole 13
Overall thickness is greater than 10000A, and processing grid line via hole 13 need to penetrate through gate insulation layer 4, the first insulating layer 7 of 3 top of grid line binding metal
With second insulating layer 10.Since via hole is that primary etching is formed, the excessive difference in thickness of two types via hole will cause via hole at
Type is bad, and the process time required for terminating due to the etching of grid line via hole 13 is 100 seconds, and touch-control via hole 14 needs 20 seconds to be
Achievable, i.e., after the completion of touch-control via hole 14 etches, grid line via hole 13, which does not still etch, to be come；Thus it will cause touch-control via hole 14
The touch-control of bottom binds metal over etching.Caused bad phenomenon as shown in fig. 2, only a small part at touch-control via hole 14
Touch-control binding metal sidewall and ITO (electro-conductive glass) overlap, overlapping area is too small, it is easy to cause to overlap bad.
Summary of the invention
In view of this, the present invention provides one kind to solve metal from the etching problem for holding touch base plate different location via hole
Metal, can be under the premise of not increasing additional technique process, simply by change from the via etch method for holding touch base plate
Mask structure or change TFT (thin film transistor) structure, improve touch-control via hole and overlap bad phenomenon.
The metal from hold touch base plate on via hole include grid line via hole and touch-control via hole；The grid line via hole will etch
Film layer be gate insulation layer, the first insulating layer and second insulating layer, the touch-control via hole film layer to be etched be second insulating layer.
A kind of scheme of the invention are as follows: for processing the figure of grid line via hole using 100% light transmission on mask plate；In exposure mask
The thickness of the photoresist for being internally provided with setting thickness for processing the figure of touch-control via hole in version, the photoresist meets in phase
Under the premise of with etching speed, the grid line via hole and touch-control via hole etch molding simultaneously.
A kind of scheme of the invention are as follows: below touch-control binding metal, the first insulating layer inside and the touch-control via hole pair
The position setting data wire metal buffer layer answered；The thickness of the data wire metal buffer layer guarantees to work as the grid line via etch
When molding, the touch-control binding metal is etched completely in thickness direction, and the data wire metal buffer layer does not have in thickness direction
Have and is etched completely；After forming the touch-control via hole to touch-control via hole progress ITO pattern technique, the touch-control via hole is in side
Face is contacted with ITO, bottom and the data wire metal buffer layer contacts.The width of the data wire metal buffer layer is greater than touch-control
Bind the width of metal, the highly height less than the first insulating layer.
The utility model has the advantages that
(1) touch-control via hole overlap joint it is undesirable can be improved under the premise of not increasing additional technique process by this method
Phenomenon.
(2) by placing gray level mask figure on mask plate, the thickness of gray level mask exposure area photoresist is controlled, is made
Obtain grid line via hole and touch-control via hole while be etched molding, while it is also ensured that the lower over etching rate of touch-control via hole.
(3) buffer metal is set below touch-control via hole, so that ITO is directly contacted with buffer metal, reduces the resistance of ITO
Value, while ITO is laterally contacted with touch-control via hole, the combination of lesser ITO and data wire metal are contacted with ITO, Neng Gouyou
Effect reduces the incidence of touch-control via hole poor contact.
Detailed description of the invention
Fig. 1 is structural schematic diagram of the metal from appearance touch base plate；
Fig. 2 is structural schematic diagram of the metal after actual process production in the prior art from appearance touch base plate；
Fig. 3 is the schematic diagram for processing touch-control via hole in embodiment 1 from appearance touch base plate in metal using gray level mask plate；
Structural schematic diagram when Fig. 4 is setting data wire metal buffer layer, not yet progress via etch；
Fig. 5 is setting data wire metal buffer layer, the structural schematic diagram after etching grid line via hole and touch-control via hole；
Fig. 6 is the structural schematic diagram after ITO is contacted with touch-control metal, data wire metal.
Wherein: 1- glass substrate, 2- grid line, 3- grid line bind metal, 4- gate insulation layer, 5- source electrode, 6- drain electrode, 7- first
Insulating layer, 8- touch-control metal routing, 9- touch-control bind metal, 10- second insulating layer, 11- active layer, 12- pixel electrode, 13-
Grid line via hole, 14- touch-control via hole, 15- data wire metal buffer layer, 16- public electrode
Specific embodiment
The present invention will now be described in detail with reference to the accompanying drawings and examples.
Embodiment 1:
The present embodiment by change mask plate 16 structure come improve existing touch-control via hole cross cause at quarter to overlap it is undesirable existing
As this method makes grid line via hole 13 and touch-control via hole 14 while the molding that is etched, to keep away by the structure of change mask plate 16
Exempting from the excessive difference in thickness of two types via hole, to will cause hole forming bad.
As shown in figure 3, mask plate 16 uses gray level mask plate, i.e. figure on mask plate is gray-scale graphical, by mask plate
On figure be arranged to the region of 100% light transmission and partial light permeability.Specifically: it is separately provided for processing on mask plate 16
The figure of grid line via hole 13 and touch-control via hole 14 uses 100% light transmission for the figure for processing grid line via hole 13, to carve
The film layer of erosion is gate insulation layer 4, the first insulating layer 7 and second insulating layer 10, and thickness is greater than 10000A, required process time
100s.For touch-control via hole 14, the film layer to be etched is second insulating layer 10, depth 3000A, process time 20s.In order to subtract
The etch period difference of slow 80s binds the influence of metal 9 to touch-control, is being to the etching speed of photoresist in view of dry etching
It is residual between the figure of touch-control via hole 14 and touch-control binding metal 9 for processing on mask plate 16 under the premise of 10000A/60s
The photoresist thickness (thus the partial graphical is partially transparent area) for staying 1.3um~1.6um, in the photoresist thickness range
It is interior, conducting while two via holes may be implemented.
Embodiment 2:
In view of in the prior art, touch-control via hole 14 only has lateral small area and ITO (electro-conductive glass) in electrical contact, ITO
Resistance value itself is bigger than normal, be easy to cause contact resistance excessive.The present embodiment, which is used, places data line gold in touch-control binding 9 bottom of metal
The scheme for belonging to buffer layer 15, improving existing touch-control via hole 14 quarter excessively causes to overlap bad phenomenon.As shown in figure 4, being tied up in touch-control
Deposit belongs to placement data wire metal buffer layer 15, the width of data wire metal buffer layer 15 in the first insulating layer 7 of 9 lower sections and is greater than
Touch-control binds the width of metal 9, the height of the height of data wire metal buffer layer 15 less than the first insulating layer 7.Subsequently form light
Photoresist via hole simultaneously carries out dry etching, since metal etch speed is slow, while having the first insulation on data wire metal buffer layer 15
Layer 7 and second insulating layer 10, so, when via hole (the i.e. grid line via hole 13) formation on grid line binding metal 3, data wire metal
Buffer layer 15 still has part residual, and touch-control binding metal 9 is then vertically being etched completely away, as shown in Figure 5.It then carries out public
Common electrode graphics art, formed figure are as shown in Figure 6.Although touch-control binding metal 9 is vertically being etched away, laterally still
It can so be electrically connected, and be conducting on data wire metal buffer layer 15 with public electrode, to realize safe electric connection.
In conclusion the above is merely preferred embodiments of the present invention, being not intended to limit the scope of the present invention.
All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should be included in of the invention
Within protection scope.
Claims (2)
1. metal from hold touch base plate via etch method, the metal from appearance touch base plate on via hole include grid line via hole
(13) and touch-control via hole (14)；Grid line via hole (13) film layer to be etched be gate insulation layer (4), the first insulating layer (7) and
Second insulating layer (10), touch-control via hole (14) film layer to be etched are second insulating layer (10)；It is characterized by: mask plate
(16) for processing the figure of grid line via hole (13) using 100% light transmission on；For processing touch-control via hole on mask plate (16)
(14) figure is internally provided with the photoresist of setting thickness, and the thickness of the photoresist meets the premise in identical etching speed
Under, the grid line via hole (13) and touch-control via hole (14) etch molding simultaneously；The mask plate (16) uses gray level mask plate.
2. metal from hold touch base plate via etch method, the metal from appearance touch base plate on via hole include grid line via hole
(13) and touch-control via hole (14)；It is characterized by: below touch-control binding metal (9), the first insulating layer (7) inside and the touching
Control via hole (14) corresponding position setting data wire metal buffer layer (15)；The thickness of the data wire metal buffer layer (15) is protected
When the grid line via hole (13) etches and forms, touch-control binding metal (9) is etched card completely in thickness direction, the number
It is not etched completely according to line metal buffer layer (15) in thickness direction；ITO pattern technique is carried out to the touch-control via hole (14)
After forming the touch-control via hole (14), the touch-control via hole (14) is contacted in side with ITO, and bottom and the data wire metal are slow
Rush layer (15) contact；The width of the data wire metal buffer layer (15) is greater than the width of touch-control binding metal (9), is highly less than
The height of first insulating layer (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710322780.5A CN107154405B (en) | 2017-05-09 | 2017-05-09 | Via etch method of the metal from appearance touch base plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710322780.5A CN107154405B (en) | 2017-05-09 | 2017-05-09 | Via etch method of the metal from appearance touch base plate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107154405A CN107154405A (en) | 2017-09-12 |
| CN107154405B true CN107154405B (en) | 2019-10-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710322780.5A Expired - Fee Related CN107154405B (en) | 2017-05-09 | 2017-05-09 | Via etch method of the metal from appearance touch base plate |
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| CN (1) | CN107154405B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112285996A (en) * | 2020-10-28 | 2021-01-29 | 京东方科技集团股份有限公司 | Mask, display panel and display device |
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|---|---|---|---|---|
| CN103943061A (en) * | 2013-12-11 | 2014-07-23 | 上海天马微电子有限公司 | OLED display device with built-in touch control structure |
| CN104576657A (en) * | 2014-12-23 | 2015-04-29 | 上海天马微电子有限公司 | Array substrate and manufacturing method thereof |
| CN104576527A (en) * | 2014-12-31 | 2015-04-29 | 深圳市华星光电技术有限公司 | Method for preparing array substrate |
| CN104915052A (en) * | 2015-04-24 | 2015-09-16 | 武汉华星光电技术有限公司 | Touch control display device, manufacturing method thereof and electronic equipment |
| CN106129066A (en) * | 2016-07-18 | 2016-11-16 | 京东方科技集团股份有限公司 | A kind of array base palte, display floater and array base palte preparation method |
| CN106200077A (en) * | 2016-08-31 | 2016-12-07 | 深圳市华星光电技术有限公司 | A kind of contact panel and preparation method thereof |
-
2017
- 2017-05-09 CN CN201710322780.5A patent/CN107154405B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943061A (en) * | 2013-12-11 | 2014-07-23 | 上海天马微电子有限公司 | OLED display device with built-in touch control structure |
| CN104576657A (en) * | 2014-12-23 | 2015-04-29 | 上海天马微电子有限公司 | Array substrate and manufacturing method thereof |
| CN104576527A (en) * | 2014-12-31 | 2015-04-29 | 深圳市华星光电技术有限公司 | Method for preparing array substrate |
| CN104915052A (en) * | 2015-04-24 | 2015-09-16 | 武汉华星光电技术有限公司 | Touch control display device, manufacturing method thereof and electronic equipment |
| CN106129066A (en) * | 2016-07-18 | 2016-11-16 | 京东方科技集团股份有限公司 | A kind of array base palte, display floater and array base palte preparation method |
| CN106200077A (en) * | 2016-08-31 | 2016-12-07 | 深圳市华星光电技术有限公司 | A kind of contact panel and preparation method thereof |
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| Publication number | Publication date |
|---|---|
| CN107154405A (en) | 2017-09-12 |
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