CN107102961A - Accelerate the method and system of arm processor concurrent working - Google Patents
Accelerate the method and system of arm processor concurrent working Download PDFInfo
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- CN107102961A CN107102961A CN201710282610.9A CN201710282610A CN107102961A CN 107102961 A CN107102961 A CN 107102961A CN 201710282610 A CN201710282610 A CN 201710282610A CN 107102961 A CN107102961 A CN 107102961A
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- rapidio
- pcie
- arm processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- General Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bus Control (AREA)
Abstract
The invention discloses the method and system for accelerating arm processor concurrent working, belong to processor concurrent working field, the technical problem to be solved is that arm processor passes through inefficiency when Ethernet or PCIE bus interconnections；Its method is：It is that row data communication is entered by RapidIO buses between RapidIO buses, arm processor by the PCIE general line systems of each arm processor.Its structure turns RapidIO bridges including RapidIO exchange chips, multiple arm processors and multiple PCIE, one PCIE of each arm processor correspondence turns RapidIO bridges, and each arm processor turns RapidIO bridgings by PCIE buses and corresponding PCIE and connect, each PCIE turns RapidIO bridges and is connected by RapidIO buses with RapidIO exchange chips.
Description
Technical field
The present invention relates to big data search field, specifically accelerate the method and system of arm processor concurrent working.
Background technology
Current arm processor development is maked rapid progress, and performance is more and more powerful, and single arm processor can reach 2.0Ghz
Interior check figure more than dominant frequency above and 10 cores, as a result of the framework and instruction set different from X86, by arm processor
The system of composition is easy to cut, simple in construction, and power consumption is very low.ARM（English full name is Advanced RISC
Machines, is the first item risc microcontroller of the low-power consumption cost of Acorn Co., Ltds of Britain design）Processor is had
Various data/address bus reached unanimity in X86 processor, conventional PCIE（English full name is Peripheral
Component Interconnect Express, translator of Chinese is high speed serialization computer expansion bus standard）、USB（English
Full name is Universal Serial Bus, and translator of Chinese is USB）、VGA（English full name is Video
Graphics Array, translator of Chinese is Video Graphics Array）、HDMI（English full name is High Definition
Multimedia Interface, translator of Chinese is HDMI）、SATA（English full name is Serial
Advanced Technology Attachment, translator of Chinese is Serial Advanced Technology Attachment）All it is integrated Deng signal bus
In arm processor, it is not necessary to the support of independent bridge piece.
It is still the world of X 86 processor in high-performance server and computer realm, multiple CPU can work parallel
Make, load sharing, improve operating efficiency.High-performance server and the computer first meeting for being currently based on arm processor are young
Shape, but the country is also in the blank phase, in addition it is also necessary to do many technology explorations.
Ethernet, PCIE and RapidIO are the major techniques that present multisystem carries out data transmission, but Ethernet due to
Limited by load and communications protocol, the shortcomings of there is big network delay, easy packet loss, PCI-E then is not completely free of
The agreement limitation of pci bus afterwards.
RapidIO be take the lead in advocating by companies such as Motorola and Mercury a kind of high-performance, low pin count, base
It is that one kind to meet and following high performance embedded system demand is designed is open in the interconnection architecture of packet-switching
Formula interconnection technique standard.RapidIO is mainly used in embedded system intraconnection, supports chip to chip, plate between plate
Communication, can as embedded device backboard（Backplane）Connection.
RapidIO agreements are made up of logical layer, transport layer and physical layer.Logical layer defines all agreements and bag form,
This is the necessary information for terminal being initialized and being completed transmission；Transport layer is packet from a terminal to another
The necessary information of individual terminal passageway；Physical layer describes interface protocol between equipment, and such as bag passes device, and flow control, electricity is special
Property and lower level error management etc..IO points of Rapid is parallel Rapid I/O standards and serial Rapid I/O standards, serial RapidIO
Refer to that physical layer uses the RapidIO standards of serial differential analog signal transmission.
How to be realized using RapidIO and accelerate arm processor concurrent working, be the technical issues that need to address.
The content of the invention
The technical assignment of the present invention be it is not enough there is provided the method and system for accelerating arm processor concurrent working for more than,
To solve arm processor by when Ethernet or PCIE bus interconnections the problem of inefficiency.
The technical assignment of the present invention is realized in the following manner：
Accelerate the method for arm processor concurrent working, be RapidIO buses by the PCIE general line systems of each arm processor,
Row data communication is entered by RapidIO buses between arm processor.
Further, comprise the following steps：
S1, it is all connected with PCIE on each arm processor and turns RapidIO bridges, by RapidIO bridge by the PCIE of arm processor
General line system is RapidIO buses；
S2, between PCIE turns RapidIO bridges set RapidIO exchange chips, each PCIE turn RapidIO bridges with
RapidIO exchange chips are connected, and turn RapidIO bridges by PCIE and RapidIO exchange chips coordinate, lead between arm processor
Cross RapidIO buses and enter row data communication.
Accelerate the system of arm processor concurrent working, including RapidIO exchange chips, multiple arm processors and multiple
PCIE turns RapidIO bridges, and one PCIE of each arm processor correspondence turns RapidIO bridges, and each arm processor passes through
PCIE buses and corresponding PCIE turn RapidIO bridgings and connect, and each PCIE turns RapidIO bridges by RapidIO buses
It is connected with RapidIO exchange chips.
Further, network interface, USB interface and display interface are provided with each arm processor.
The method and system of the acceleration arm processor concurrent working of the present invention have advantages below：
1st, it is to pass through RapidIO buses between RapidIO buses, RAM processors by the PCIE general line systems of each RAM processors
Enter row data communication, it is possible to achieve the concurrent working of multiple RAM processors, effective load sharing improves operating efficiency；
2nd, RapidIO buses have the function similar with Ethernet to PCIE buses, and can not be replicated with other interconnection techniques
Function, such as：Low time delay, the system event distribution of low jitter, combined type link layer and Internet flow control mechanism, can configure
Error detection and fuzzy topology route efficient backup, high reliability and availability can be achieved, read/write and interprocess communication disappear
The semantic hardware of breath realizes that these functions permission System Architect establishment performance is higher, power consumption is lower and is easier what is extended
System.
Brief description of the drawings
The present invention is further described below in conjunction with the accompanying drawings.
Accompanying drawing 1 is the operation principle block diagram for the method that embodiment 1 accelerates arm processor concurrent working.
Embodiment
With reference to Figure of description and specific embodiment to the arm processor concurrent working side based on RapidIO of the invention
Method and system are described in detail below.
Embodiment 1：
As shown in Figure 1, the arm processor concurrent working method of the invention based on RapidIO, by each arm processor
PCIE general line systems are to enter row data communication by RapidIO buses between RapidIO buses, arm processor.
Specifically include following steps：
（1）, be all connected with PCIE on each arm processor and turn RapidIO bridges, RapidIO bridges are turned by arm processor by PCIE
PCIE general line systems be RapidIO buses；
（2）, between PCIE turns RapidIO bridges set RapidIO exchange chips, each PCIE turn RapidIO bridges with
RapidIO exchange chips are connected, and turn RapidIO bridges by PCIE and RapidIO exchange chips coordinate, lead between arm processor
Cross RapidIO buses and enter row data communication.
Wherein, PCIE, which turns RapidIO bridges, is used to the PCIE general line systems of arm processor be RapidIO buses, conventional
PCIE turns the TSI620 and TSI721 that RapidIO bridges such as Integrated Device Technology, Inc. provides.
RapidIO exchange chips are used for the interconnection for realizing RapidIO, and developing the manufacturer of RapidIO exchange chips mainly has
Tundra companies, Integrated Device Technology, Inc. and Redswitch companies etc..The product of Redswitch companies and application are all less, and Tundra is public
Integrated Device Technology, Inc. is incorporated to after department.Integrated Device Technology, Inc. provides a variety of high-performance, and the RapidIO exchange chips of low-power consumption, several applications are more
RapidIO exchange chips it is as follows：
1) CPS-1848
CPS-1848 chips be based on the specifications of RapidIO 2.1, have 48 road serial-ports, can using flexible configuration as 12 × 4,18 ×
2,18 × 1 port working mode, port number is at most configurable to 18, and chip internal exchanges bandwidth and reaches 240Gbps, carries
For clog-free full-duplex switching capacity.High performance SerDes passages can realize single channel 1.25,2.5,3.125,5.0 or
6.25Gbaud transmission rate.
2） CPS-1432
CPS-1432 chips be based on the specifications of RapidIO 2.1, have 32 road serial-ports, can using flexible configuration as 8 × 4,14 ×
2,14 × 1 port working mode, port number is at most configurable to 14, and chip internal exchanges bandwidth and reaches 160Gbps,
(ibid）.
3） CPS-1616
CPS-1616 chips be based on the specifications of RapidIO 2.1, have 16 road serial-ports, can using flexible configuration as 4 × 4,8 × 2,
16 × 1 port working mode, port number is at most configurable to 16, and chip internal exchanges bandwidth and reaches 80Gbps, (same
On).
4）Tsi578
Tsi578 chips be Tundra companies release RapidIO trade-to products, after be incorporated to Integrated Device Technology, Inc., the chip is based on
The specifications of RapidIO 1.3, have 16 road serial-ports, can be (same using port working mode of the flexible configuration as 8 × 4 or 16 × 1
On）2.5 or 3.125Gbaud transmission rate.
Embodiment 2：
The present invention acceleration arm processor concurrent working system, including RapidIO exchange chips, multiple arm processors and
Multiple PCIE turn RapidIO bridges, and one PCIE of each arm processor correspondence turns RapidIO bridges, and each arm processor leads to
Cross PCIE buses and corresponding PCIE turns RapidIO bridgings and connect, it is total by RapidIO that each PCIE turns RapidIO bridges
Line is connected with RapidIO exchange chips.
Wherein, PCIE, which turns RapidIO bridges, is used to the PCIE general line systems of corresponding arm processor be RapidIO
Bus, each PCIE turns RapidIO bridges and is connected with RapidIO exchange chips, and RapidIO exchange chips are multiple for realizing
PCIE turns the interconnection of RapidIO bridges, so that under the cooperation that PCIE turns RapidIO bridges and RapidIO exchange chips, multiple processing
Row data communication can be entered by RapidIO buses between device.Conventional PCIE turns RapidIO bridges as Integrated Device Technology, Inc. provides
TSI620 and TSI721, CPS-1848, CPS-1432, CPS-1616 that conventional RapidIO exchange chips such as Integrated Device Technology, Inc. provides
And Tsi578, in actual applications, for that can select as needed, suitable PCIE turns RapidIO bridges and RapidIO exchanges core
Piece.
Network interface, USB interface and display interface are provided with each arm processor, network interface passes through network
Signal bus receives external network signal, and USB interface receives external USB signal by usb signal bus, and display interface passes through aobvious
Show that signal bus receives outside display signal.
The system of the acceleration arm processor concurrent working of the present invention can realize acceleration arm processor in embodiment 1 simultaneously
The method of row work.
By embodiment above, the those skilled in the art can readily realize the present invention.But should
Work as understanding, the present invention is not limited to embodiment disclosed above.On the basis of disclosed embodiment, the technology
The technical staff in field can be combined different technical characteristics, so as to realize different technical schemes.
It is the known technology of those skilled in the art in addition to the technical characteristic described in specification.
Claims (4)
1. accelerate the method for arm processor concurrent working, it is characterised in that be by the PCIE general line systems of each arm processor
Row data communication is entered by RapidIO buses between RapidIO buses, arm processor.
2. the method for acceleration arm processor concurrent working according to claim 1, it is characterised in that comprise the following steps：
S1, it is all connected with PCIE on each arm processor and turns RapidIO bridges, by RapidIO bridge by the PCIE of arm processor
General line system is RapidIO buses；
S2, between PCIE turns RapidIO bridges set RapidIO exchange chips, each PCIE turn RapidIO bridges with
RapidIO exchange chips are connected, and turn RapidIO bridges by PCIE and RapidIO exchange chips coordinate, lead between arm processor
Cross RapidIO buses and enter row data communication.
3. accelerate the system of arm processor concurrent working, it is characterised in that including RapidIO exchange chips, multiple arm processors
And multiple PCIE turn RapidIO bridges, one PCIE of each arm processor correspondence turns RapidIO bridges, and each arm processor
Turn RapidIO bridgings by PCIE buses and corresponding PCIE to connect, each PCIE turns RapidIO bridges and passed through
RapidIO buses are connected with RapidIO exchange chips.
4. the system of acceleration arm processor concurrent working according to claim 3, it is characterised in that each arm processor
On be provided with network interface, USB interface and display interface.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710282610.9A CN107102961A (en) | 2017-04-26 | 2017-04-26 | Accelerate the method and system of arm processor concurrent working |
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| CN201710282610.9A CN107102961A (en) | 2017-04-26 | 2017-04-26 | Accelerate the method and system of arm processor concurrent working |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109510761A (en) * | 2018-12-07 | 2019-03-22 | 天津津航计算技术研究所 | A kind of one-to-many bus gateway apparatus based on SRIO |
| CN115344522A (en) * | 2022-10-14 | 2022-11-15 | 井芯微电子技术(天津)有限公司 | Message conversion channel, message conversion device, electronic equipment and switching equipment |
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| CN104579786A (en) * | 2015-01-20 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | Server design method based on fusion and 2D Torus network topology framework |
| CN105488566A (en) * | 2015-12-10 | 2016-04-13 | 浙江大学 | VPX bus based brain neural signal real-time parallel processing system |
| CN106027424A (en) * | 2016-05-23 | 2016-10-12 | 上海电控研究所 | Ethernet exchange device based on RapidIO exchange technology |
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Patent Citations (4)
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| CN102508516A (en) * | 2011-10-24 | 2012-06-20 | 苏州新海宜通信科技股份有限公司 | AMC (advanced mezzanine card) board card structure based on MicroTCA (telecom and computing architecture) standard and connection type thereof |
| CN104579786A (en) * | 2015-01-20 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | Server design method based on fusion and 2D Torus network topology framework |
| CN105488566A (en) * | 2015-12-10 | 2016-04-13 | 浙江大学 | VPX bus based brain neural signal real-time parallel processing system |
| CN106027424A (en) * | 2016-05-23 | 2016-10-12 | 上海电控研究所 | Ethernet exchange device based on RapidIO exchange technology |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109510761A (en) * | 2018-12-07 | 2019-03-22 | 天津津航计算技术研究所 | A kind of one-to-many bus gateway apparatus based on SRIO |
| CN115344522A (en) * | 2022-10-14 | 2022-11-15 | 井芯微电子技术(天津)有限公司 | Message conversion channel, message conversion device, electronic equipment and switching equipment |
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Application publication date: 20170829 |