CN107070593A - Relay based on multichannel communication reception system starts method - Google Patents
Relay based on multichannel communication reception system starts method Download PDFInfo
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- CN107070593A CN107070593A CN201710070609.XA CN201710070609A CN107070593A CN 107070593 A CN107070593 A CN 107070593A CN 201710070609 A CN201710070609 A CN 201710070609A CN 107070593 A CN107070593 A CN 107070593A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
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Abstract
Start method the invention discloses a kind of relay based on multichannel communication reception system, including multichannel communication reception system carries out the steps such as power-up initializing.The present invention enters sampling using DMA channel control ADC, ADC, when carrying out data sampling, can directly access internal memory by DMA channel, realize on the premise of processor resource is not accounted for, data signal is gathered, and is saved in the internal memory of processor, ADC directly obtains sampled data from internal memory, computing resource can be saved, also there is good adaptive characteristic, strong antijamming capability during detection, with good receptivity.
Description
Technical field
The invention belongs to wireless communication technology field.Specifically related to a kind of relay based on multichannel communication reception system
Startup method.
Background technology
It is the bridge of the interrupt processing between microprocessor and peripheral hardware, the interrupt requests sent by peripheral hardware need to interrupt control
Device is handled.But in multichannel communication reception system, relay startup is unsuccessful, test has found each submodule
Relay is given to through the correct interrupt signal that produces, but interruption routine is not carried out in software；And use processor
Read sampled data, although real-time decoding can be realized, but cause decoded result easily by extraneous noise jamming because sample rate is low,
Decoding effect is not good, if the decoding effect to have pursued, can only abandon real-time, first carry out signal sampling, be put in caching,
Then the sampled data in caching is decoded again, because DMA moves down coversion base band data in batches, new data is periodically
Covering legacy data, cause same frame signal be cut off, respectively at new and old two data blocks, be easily lost information.
The content of the invention
The invention aims to overcome a kind of above-mentioned not enough relay based on multichannel communication reception system of offer
Startup method.
A kind of relay based on multichannel communication reception system starts method, comprises the following steps:
Multichannel communication reception system carries out power-up initializing；
Start ADC_DMA；
Judge whether to complete data-moving, moved next time if it is not, then returning to previous step and starting；If it is, interrupting
DMA goes to next step；
Carry out the judgement and restructuring of frame information；
Start Sync_DMA after the judgement and restructuring that complete effective frame information；
Carry out Sync synchronization process；
Judge whether Sync completes synchronization process, if it is not, then returning to previous step proceeds Sync synchronization process；If
It is then to go to next step；
Whether judge synchronization is last frame data, if it is not, then being back to the judgement and restructuring for carrying out frame information；Such as
Fruit is then to go to the step of judging whether to complete data-moving.
Further, the step of startup ADC_DMA is specially：
Start processor DMA channel, driving ADC directly accesses internal memory, ADC input analog signal outputs by DMA channel
The digital signal data that processor can be used；
ADC obtains sampled data by DMA channel, is directly stored in internal memory；
Detect that buffer area whether there is sampled data, such as there is sampled data, then it is every by increasing direct memory access
The secondary data volume moved.
Further, it is described carry out frame information judgement and restructuring the step of be specially：
Processor is interrupted by DMA and obtains sampled data, and the sampled data is cached；
Detect that buffer area whether there is sampled data, such as there is sampled data, then send signal to node, node receives letter
After number, enter a judgement, if only receiving the signal of single information source node, its correspondence is sent to after directly amplifying to signal next
The node of topology；Otherwise, carry out after network code and the scattered restructuring of data frame, be sent to a node.
Further, the step of startup Sync_DMA is specially：
Host main frames send write order；
Sync receives write order and parses the order, and then Sync fills in data by DMA channel in internal memory；
Interrupted by DMA and receive Host data, and be written in buffering area, after the completion of, continue to repeat above-mentioned action.
Further, the process of progress Sync synchronization process is specially：
Time synchronized Sync messages are sent from clock node to master clock node, and record transmission Sync；
The Sync messages sent from clock node to master clock node are transmitted to master clock node；
When from clock node receive master clock node return Sync messages when, record receive the Sync messages when
Between；
Master clock node receives the Sync messages of master-salve clock node transmission, can record reception and send out Sync from clock node
The time of message.
The present invention enters sampling using DMA channel control ADC, and ADC, can be direct when carrying out data sampling by DMA channel
Internal memory is accessed, is realized on the premise of processor resource is not accounted for, data signal is gathered, and be saved in the internal memory of processor, ADC
Sampled data is directly obtained from internal memory, computing resource can be saved, it is anti-interference during detection also with good adaptive characteristic
Ability is strong, with good receptivity.
Brief description of the drawings
Fig. 1 is the inventive method schematic flow sheet.
Embodiment
Below in conjunction with specific embodiment, the present invention is further illustrated：
A kind of relay based on multichannel communication reception system starts method, comprises the following steps:
Multichannel communication reception system carries out power-up initializing；
Start ADC_DMA；
Judge whether to complete data-moving, moved next time if it is not, then returning to previous step and starting；If it is, interrupting
DMA goes to next step；
Carry out the judgement and restructuring of frame information；
Start Sync_DMA after the judgement and restructuring that complete effective frame information；
Carry out Sync synchronization process；
Judge whether Sync completes synchronization process, if it is not, then returning to previous step proceeds Sync synchronization process；If
It is then to go to next step；
Whether judge synchronization is last frame data, if it is not, then being back to the judgement and restructuring for carrying out frame information；Such as
Fruit is then to go to the step of judging whether to complete data-moving.
The step of startup ADC_DMA is specially：
Start processor DMA channel, driving ADC directly accesses internal memory, ADC input analog signal outputs by DMA channel
The digital signal data that processor can be used；
ADC obtains sampled data by DMA channel, is directly stored in internal memory；
Detect that buffer area whether there is sampled data, such as there is sampled data, then it is every by increasing direct memory access
The secondary data volume moved.
It is described carry out frame information judgement and restructuring the step of be specially：
Processor is interrupted by DMA and obtains sampled data, and the sampled data is cached；
Detect that buffer area whether there is sampled data, such as there is sampled data, then send signal to node, node receives letter
After number, enter a judgement, if only receiving the signal of single information source node, its correspondence is sent to after directly amplifying to signal next
The node of topology；Otherwise, carry out after network code and the scattered restructuring of data frame, be sent to a node.
The step of startup Sync_DMA is specially：
Host main frames send write order；
Sync receives write order and parses the order, and then Sync fills in data by DMA channel in internal memory；
Interrupted by DMA and receive Host data, and be written in buffering area, after the completion of, continue to repeat above-mentioned action.
Carry out Sync synchronization process process be specially：
Time synchronized Sync messages are sent from clock node to master clock node, and record transmission Sync；
The Sync messages sent from clock node to master clock node are transmitted to master clock node；
When from clock node receive master clock node return Sync messages when, record receive the Sync messages when
Between；
Master clock node receives the Sync messages of master-salve clock node transmission, can record reception and send out Sync from clock node
The time of message.
Claims (5)
1. a kind of relay based on multichannel communication reception system starts method, it is characterised in that comprise the following steps:
Multichannel communication reception system carries out power-up initializing；
Start ADC_DMA；
Judge whether to complete data-moving, moved next time if it is not, then returning to previous step and starting；Turn if it is, interrupting DMA
To next step；
Carry out the judgement and restructuring of frame information；
Start Sync_DMA after the judgement and restructuring that complete effective frame information；
Carry out Sync synchronization process；
Judge whether Sync completes synchronization process, if it is not, then returning to previous step proceeds Sync synchronization process；If it is,
Then go to next step；
Whether judge synchronization is last frame data, if it is not, then being back to the judgement and restructuring for carrying out frame information；If
It is then to go to the step of judging whether to complete data-moving.
2. the relay according to claim 1 based on multichannel communication reception system starts method, it is characterised in that institute
Stating the step of starting ADC_DMA is specially：
Start processor DMA channel, driving ADC directly accesses internal memory, ADC input analog signal output processing by DMA channel
The digital signal data that device can be used；
ADC obtains sampled data by DMA channel, is directly stored in internal memory；
Detect that buffer area whether there is sampled data, such as there is sampled data, then removed every time by increasing direct memory access
The data volume of shifting.
3. the relay according to claim 2 based on multichannel communication reception system starts method, it is characterised in that institute
State carry out frame information judgement and restructuring the step of be specially：
Processor is interrupted by DMA and obtains sampled data, and the sampled data is cached；
Detect that buffer area whether there is sampled data, such as there is sampled data, then send signal to node, node receives signal
Afterwards, enter a judgement, if only receiving the signal of single information source node, it is sent to after directly amplifying to signal and corresponds to next open up
The node flutterred；Otherwise, carry out after network code and the scattered restructuring of data frame, be sent to a node.
4. the relay according to claim 3 based on multichannel communication reception system starts method, it is characterised in that institute
Stating the step of starting Sync_DMA is specially：
Host main frames send write order；
Sync receives write order and parses the order, and then Sync fills in data by DMA channel in internal memory；
Interrupted by DMA and receive Host data, and be written in buffering area, after the completion of, continue to repeat above-mentioned action.
5. the relay according to claim 4 based on multichannel communication reception system starts method, it is characterised in that enter
The process of row Sync synchronization process is specially：
Time synchronized Sync messages are sent from clock node to master clock node, and record transmission Sync；
The Sync messages sent from clock node to master clock node are transmitted to master clock node；
When receiving the Sync messages of master clock node return from clock node, record receives the time of the Sync messages；
Master clock node receives the Sync messages of master-salve clock node transmission, can record reception and send out Sync messages from clock node
Time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710070609.XA CN107070593B (en) | 2017-02-09 | 2017-02-09 | Interrupt starting method based on multi-channel communication receiving system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710070609.XA CN107070593B (en) | 2017-02-09 | 2017-02-09 | Interrupt starting method based on multi-channel communication receiving system |
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| Publication Number | Publication Date |
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| CN107070593A true CN107070593A (en) | 2017-08-18 |
| CN107070593B CN107070593B (en) | 2020-08-28 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1892569A (en) * | 2005-07-08 | 2007-01-10 | 科诚股份有限公司 | Multi-way series transmission and control apparatus and method |
| US20090055713A1 (en) * | 2007-08-21 | 2009-02-26 | Samsung Electronics Co., Ltd. | Ecc control circuits, multi-channel memory systems including the same, and related methods of operation |
| CN102567256A (en) * | 2011-12-16 | 2012-07-11 | 龙芯中科技术有限公司 | Processor system, as well as multi-channel memory copying DMA accelerator and method thereof |
| CN103793342A (en) * | 2012-11-02 | 2014-05-14 | 中兴通讯股份有限公司 | Multichannel direct memory access (DMA) controller |
-
2017
- 2017-02-09 CN CN201710070609.XA patent/CN107070593B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1892569A (en) * | 2005-07-08 | 2007-01-10 | 科诚股份有限公司 | Multi-way series transmission and control apparatus and method |
| US20090055713A1 (en) * | 2007-08-21 | 2009-02-26 | Samsung Electronics Co., Ltd. | Ecc control circuits, multi-channel memory systems including the same, and related methods of operation |
| CN102567256A (en) * | 2011-12-16 | 2012-07-11 | 龙芯中科技术有限公司 | Processor system, as well as multi-channel memory copying DMA accelerator and method thereof |
| CN103793342A (en) * | 2012-11-02 | 2014-05-14 | 中兴通讯股份有限公司 | Multichannel direct memory access (DMA) controller |
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| CN107070593B (en) | 2020-08-28 |
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Effective date of registration: 20201218 Address after: No.368 Keyun Road, high tech Zone, Chengdu, Sichuan 610000 Patentee after: Chengdu Mifeng perception Technology Co.,Ltd. Address before: 430223 No.2, Wuda Science Park Road, Donghu high tech Development Zone, Wuhan City, Hubei Province Patentee before: WUHAN MIFENG COMMUNICATION TECHNOLOGY Co.,Ltd. |
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