CN107038134A - A kind of SRIO interface solid hard disks system and its implementation based on FPGA - Google Patents
A kind of SRIO interface solid hard disks system and its implementation based on FPGA Download PDFInfo
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- CN107038134A CN107038134A CN201610993707.6A CN201610993707A CN107038134A CN 107038134 A CN107038134 A CN 107038134A CN 201610993707 A CN201610993707 A CN 201610993707A CN 107038134 A CN107038134 A CN 107038134A
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- fpga
- fpga chip
- master control
- srio
- nand flash
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/21—Employing a record carrier using a specific recording technology
- G06F2212/214—Solid state disk
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/22—Employing cache memory using specific memory technology
- G06F2212/221—Static RAM
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- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The present invention relates to the solid state hard disc technical field of embedded system, more particularly to a kind of SRIO interface solid hard disks system and its implementation based on FPGA.Its system includes master control fpga chip, master control fpga chip is simultaneously connected to four auxiliary fpga chips, described master control fpga chip is mounted with first order DDR3 SRAMs, and four described auxiliary fpga chips are mounted with a second level DDR3 SRAM and a NAND Flash storage array respectively.A kind of the SRIO interface solid hard disks system and its implementation based on FPGA of the present invention, it manages NAND Flash storage arrays by fpga chip, reaches the SRIO interface solid hard disks of High rate and large capacity.
Description
Technical field
The present invention relates to the solid state hard disc technical field of embedded system, more particularly to a kind of SRIO interfaces based on FPGA
Solid state hard disk system and its implementation.
Background technology
FPGA（Field-Programmable Gate Array）, i.e. field programmable gate array, it be PAL,
The product further developed on the basis of the programming devices such as GAL, CPLD.It is as application specific integrated circuit（ASIC）In field
A kind of semi-custom circuit and occur, both solved the deficiency of custom circuit, original programming device gate circuit overcome again
The limited shortcoming of number.
SRIO（Serial Rapid I/O）It is the highly reliable of embedded system exploitation proposition, high-performance, based on bag
The high speed interconnection technique of new generation of exchange, in 2004 by International Organization for standardization (ISO) and International Power association (IEC) batch
Standard is the standards of ISO/IECDIS 18372.SRIO is then to connect to apply towards serial backplane, DSP and associated serial datum plane
Serial RapidIO interfaces.
Serial RapidIO includes the agreement of a 3-tier architecture, i.e. physical layer, transport layer, logical layer.Physical layer definition electricity
Gas characteristic, link control, lower level error management, bottom flow control data；Transport layer defines packet switch, route and addressing mechanism；
Logical layer defines total protocol and bag form.Minimum pin number can be realized, using DMA transfer, the expansible of complexity is supported
Topology, multicast communication；Optional 1.25 Gbps, 2.5 Gbps, tetra- kinds of speed of 3.125 Gbps and 5Gbps can meet different answer
It is one of optimal selection of embedded system interconnection in the following more than ten years with demand.
Interconnected with continuing to develop for high performance embedded system, between chip chamber and plate to bandwidth, cost, flexibility and can
By the requirement more and more higher of property, traditional interconnection mode, such as processor bus, pci bus and Ethernet are all difficult to meet newly
Demand.The limitation of demand and traditional interconnection mode for embedded system, RapidIO standards are made by following target
It is fixed：
1st, designed for high speed interconnection applications in embedded system machine frame.
2nd, agreement and flow-control mechanism, restricted software complexity so that error correction retransmission mechanism or even whole protocol stack are easy are simplified
Realized in hardware.
3rd, packing efficiency is improved, reduces propagation delay time.
4th, pin is reduced, cost is reduced.
5th, the realization of exchange chip is simplified, it is to avoid the Packet type parsing in exchange chip.
6th, layered protocol structure, supports a variety of transmission modes, supports multiple physical layers technology, flexibly and is easy to extension.
These features based on SRIO, SRIO interfaces are designed as by SSD, in the system for being conveniently mounted to SRIO interfaces
Go.
The content of the invention
In order to solve problem of the prior art, the embodiments of the invention provide a kind of SRIO interface solids based on FPGA are hard
Disc system and its implementation, it manages NAND Flash storage arrays by fpga chip, reaches High rate and large capacity
SRIO interface solid hard disks.
The technical solution adopted in the present invention is as follows：
A kind of SRIO interface solid hard disk systems based on FPGA, including master control fpga chip, master control fpga chip are simultaneously connected to four
Individual auxiliary fpga chip, described master control fpga chip is mounted with first order DDR3 SRAMs, and described four are auxiliary
Fpga chip is mounted with a second level DDR3 SRAM and a NAND Flash storage array respectively.
Communication between master control fpga chip and auxiliary fpga chip is realized by GTX/GTP high-speed transceivers.
NAND Flash storage arrays are made up of the NAND Flash arrays of 4 parallel 4 grades of flowing water.
A kind of implementation method of the SRIO interface solid hard disk systems based on FPGA, comprises the following steps：
A, the signal come from SRIO interfaces, first pass around master control fpga chip and parse data storage, and pass through direct internal memory
Access, by the first order DDR3 SRAMs of data-moving to master control fpga chip；
Data are moved other 4 by B and then again by direct memory access in the way of LVDS interface by GTX/GTP interfaces
In the auxiliary fpga chip of block；
C, by parsing parallel data is obtained, by the direct memory access of auxiliary fpga chip by the of data-moving to its carry
Two grades of DDR3 SRAMs,；
D, finally by near field communication (NFC), write data into NAND Flash storage arrays.
The present invention a kind of SRIO interface solid hard disks system based on FPGA by 5 pieces of fpga chips, 4 groups 4 parallel 4 grades
The NAND Flash storage arrays and two-stage DDR3 SRAM of flowing water（SRAM）Composition.In 5 pieces of fpga chips
FPGA5 is as master control FPGA, fpga chip, the communication between master control fpga chip and auxiliary fpga chip supplemented by other 4 FPGA
Realized by GTX/GTP high-speed transceivers.NAND Flash storage arrays by 4 groups 4 parallel 4 grades of flowing water Flash gusts of NAND
Row composition.Data storage employs L2 cache.The present invention is scheduled using Microblaze CUP IP to system,
NFC (Nand Flash Controller, storage array controllers) and NAND FTL (Flash is realized inside FPGA
Translation Layer, flash translation layer (FTL)) function.
The beneficial effect that the technical scheme that the present invention is provided is brought is：
The present invention realizes the management to NAND Flash storage arrays with 5 pieces of fpga chips, reduces the IO quantity to single FPGA
High request, reduce cost.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, makes required in being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is constituted for the system of a kind of the SRIO interface solid hard disks system and its implementation based on FPGA of the present invention
Figure；
Fig. 2 is 4 grades of flowing water NAND of a kind of the SRIO interface solid hard disks system and its implementation based on FPGA of the present invention
Flash storage array schematic diagrames.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
Embodiment one
A kind of SRIO interface solid hard disk systems based on FPGA of the present embodiment, by 5 pieces of fpga chips, 4 groups 4 parallel 4 grades
The NAND Flash storage arrays of flowing water and two grades of DDR3 SRAMs compositions, as shown in Figure 1.The NAND of 4 grades of flowing water
Flash storage array schematic diagrames are as shown in Figure 2.In 5 pieces of fpga chips, FPGA5 is master control fpga chip, the DDR3 of institute's carry
SRAM is cached as the first order of data, and other 4 fpga chips are each responsible for and 1 group 4 parallel 4 grades of flowing water
The interaction of NAND Flash storage arrays, each fpga chip has carry DDR3 SRAMs, is used as the second series
According to caching.FPGA5 is as master control FPGA in 5 pieces of fpga chips, fpga chip supplemented by other 4 pieces of FPGA, master control fpga chip and
Communication between auxiliary fpga chip is realized by GTX/GTP high-speed transceivers.
A kind of SRIO interface solid hard disks system based on FPGA of the present embodiment utilizes FPGA Microblaze CUP
IP is scheduled to system, realized inside FPGA NFC (Nand Flash Controller, storage array controllers) and
NAND FTL (Flash Translation Layer, flash translation layer (FTL)) function.
Embodiment two
In a kind of implementation method of SRIO interface solid hard disk systems based on FPGA of the present embodiment, come from SRIO interfaces
Signal, first passes around FPGA5 SRIO IP and parses data storage, pass through DMA（Direct memory access）, data-moving is arrived
In FPGA5 DDR3 SRAM, data are then moved other 4 with LVDS form by GTX/GTP interfaces by DMA again
Block FPGA（FPGA1~4）, then obtain parallel data by parsing, by the DMA of FPGA1~4 by data-moving to FPGA1~
4 DDR3 SRAM, that is, second level DDR3 SRAM, finally by the NFC of FPGA1~4, write data into NAND Flash and deposit
Store up array.This is the process for writing SRIO SSD, reads SRIO SSD process in contrast.
FPGA can also realize FTL function, including bad block management, abrasion equilibrium, Mapping, garbage reclamation and mistake control
System.By estimation, our NAND Flash storage arrays, 16 parallel 4 grades of flowing water can reach 3GB/S writing rate,
2.7GB/S all speed.64 NAND Flash storage arrays reach 4TB memory capacity.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent substitution and improvements made etc. should be included in the scope of the protection.
Claims (4)
1. a kind of SRIO interface solid hard disk systems based on FPGA, including master control fpga chip, it is characterised in that described master
Control fpga chip is simultaneously connected to four auxiliary fpga chips, and described master control fpga chip is mounted with the storage of first order DDR3 static randoms
Device, four described auxiliary fpga chips are mounted with a second level DDR3 SRAM and a NAND Flash respectively
Storage array.
2. a kind of SRIO interface solid hard disk systems based on FPGA according to claim 1, it is characterised in that described
Communication between master control fpga chip and auxiliary fpga chip is realized by GTX/GTP high-speed transceivers.
3. a kind of SRIO interface solid hard disk systems based on FPGA according to claim 1, it is characterised in that described
NAND Flash storage arrays are made up of the NAND Flash arrays of 4 parallel 4 grades of flowing water.
4. a kind of implementation method of the SRIO interface solid hard disk systems based on FPGA, comprises the following steps：
A, the signal come from SRIO interfaces, first pass around master control fpga chip and parse data storage, and pass through direct internal memory
Access, by the first order DDR3 SRAMs of data-moving to master control fpga chip；
Data are moved other 4 by B and then again by direct memory access in the way of LVDS interface by GTX/GTP interfaces
In the auxiliary fpga chip of block；
C, by parsing parallel data is obtained, by the direct memory access of auxiliary fpga chip by the of data-moving to its carry
Two grades of DDR3 SRAMs,；
D, finally by near field communication (NFC), write data into NAND Flash storage arrays.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610993707.6A CN107038134A (en) | 2016-11-11 | 2016-11-11 | A kind of SRIO interface solid hard disks system and its implementation based on FPGA |
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| CN201610993707.6A CN107038134A (en) | 2016-11-11 | 2016-11-11 | A kind of SRIO interface solid hard disks system and its implementation based on FPGA |
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Cited By (6)
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|---|---|---|---|---|
| CN108107827A (en) * | 2017-12-13 | 2018-06-01 | 天津津航计算技术研究所 | A kind of SRIO control methods based on the soft core of ZYNQ platforms |
| CN109344109A (en) * | 2018-10-23 | 2019-02-15 | 江苏华存电子科技有限公司 | The system and method for accelerating artificial intelligence to calculate in big data based on solid state hard disk |
| CN109814888A (en) * | 2019-01-25 | 2019-05-28 | 深圳忆联信息系统有限公司 | NandFlash controller EFUSE replaces method and device |
| CN110059049A (en) * | 2019-03-27 | 2019-07-26 | 中国计量大学上虞高等研究院有限公司 | A kind of real-time storage device |
| CN112667529A (en) * | 2019-10-16 | 2021-04-16 | 戴尔产品有限公司 | Network fabric storage system |
| WO2021125262A1 (en) * | 2019-12-17 | 2021-06-24 | ヤマハ発動機株式会社 | Automatic control board |
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| CN108107827A (en) * | 2017-12-13 | 2018-06-01 | 天津津航计算技术研究所 | A kind of SRIO control methods based on the soft core of ZYNQ platforms |
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| CN112667529A (en) * | 2019-10-16 | 2021-04-16 | 戴尔产品有限公司 | Network fabric storage system |
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