CN107025092A - A kind of random number extracting method based on latch structure real random number generators - Google Patents
A kind of random number extracting method based on latch structure real random number generators Download PDFInfo
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- CN107025092A CN107025092A CN201710458323.9A CN201710458323A CN107025092A CN 107025092 A CN107025092 A CN 107025092A CN 201710458323 A CN201710458323 A CN 201710458323A CN 107025092 A CN107025092 A CN 107025092A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
Abstract
The present invention provides a kind of random number extracting method based on latch structure real random number generators, specifically includes following steps：Latch structure real random number generators are realized on FPGA；True random number is occurred module and is started vibration using metastable state phenomenon, the cycle of oscillation of module occurs by counter records true random number, while recording duration of oscillation using FPGA system clock；The MUX configuration true random number in module occurs using true random number to occur the different path of module to adjust cycle of oscillation, cycle of oscillation is more than 70；Extract minimum 2 of counter to export as random number, produce latch structures real random number generator using metastable state phenomenon and meet the true random number of quantity demand.The beneficial effects of the present invention are：Substantially increase the speed of random number generation；There is higher robustness for the change of temperature, voltage and technique, the data produced at different conditions can pass through NIST Randomness tests.
Description
Technical field
The invention belongs to information security and technical field of integrated circuits, and in particular to one kind is truly random based on latch structures
The random number extracting method of number generator.
Background technology
With the extensive use of cloud computing, Internet of Things and big data, communication size rapidly increases between person to person, people and thing
Long, information security issue becomes more and more important.Data encryption is the main method ensured information security even unique method,
And random number is the basis of data encryption, the application of random number, which is included in cryptographic algorithm, generates safe key, secure internet
Session id, generation mobile internet device ID and various operating system agreements etc. are produced in agreement.Randomizer have it is true with
Point of machine and pseudorandom, short random train is extended to " stochastic searching " by pseudorandom number generator (PRNG) using deterministic algorithm
Bit stream, and with periodically, produced random number can not meet the high encryption system of Random demand.And true random number occurs
Device (TRNG) is to harvest entropy from physical noise source, no periodic, it is unpredictable, with real-time randomness, be high reliability plus
Close system, which is provided, to be ensured.
The research on TRNG has many types both at home and abroad, and main research concentrates on three aspects：Based on resistance heat
The randomizer of noise, the randomizer based on oscillator and based on metastable randomizer.Early stage adopts
The method for extracting random number is directly amplified with Resistance Thermal Noise, but this kind of method shortcoming shows two aspects, it is on the one hand electric
The coupled noise of source and substrate is difficult to eliminate, or other non-ideal factors also influence the random sequence of generation to a certain extent
Randomness.On the other hand use analog device this kind of method so that this kind of board design is difficult to apply in system on chip more
In terms of technology transplant.Method based on oscillator sample is a kind of digital method, the method phase with directly amplifying noise
Than the method for full-digital circuit has the advantages that high robust for the change of technique, voltage and temperature and is easily integrated.Its with
The quality of machine depends on low-frequency oscillator phase jitter size, and low-frequency oscillator phase jitter relative to high frequency vibrating
Swing the size in device cycle, it is therefore desirable to which multiple oscillators also increase hardware spending to increase phase jitter.Based on metastable state
Method can also completely using digital technology realize, produce random number using the metastable state phenomenon in bistable device.So
And, traditional metastable state method is more sensitive to environmental change, due to the influence of process deviation, it usually needs substantial amounts of design comes school
Standard is with system in cancellation element and the mismatch of sequential.It can be seen that all kinds of methods all have weak point, also have many to be studied
Place.Such as throughput and power consumption always are the emphasis of this aspect research, and efficiency is provided for demand that is existing or will appear from
Ensure.
The content of the invention
In order to solve above-mentioned technological deficiency present in prior art, the present invention provide it is a kind of based on latch structures it is true with
The random number extracting method of machine number generator, on the basis of high robust is ensured, speed is produced with very big for random number
Lifting, to improve application efficiency of the true random number on information security field.
The present invention is achieved by the following technical solutions：
A kind of random number extracting method based on latch structure real random number generators, wherein, latch structures are truly random
Number generator includes the soft cores of Microblaze being sequentially connected, and module, counter, finite state machine occur for true random number；
The soft cores of Microblaze are connected with counter and finite state machine respectively；It is using even number door that module, which occurs, for true random number
Latch structures.Random number extracting method comprises the following steps：
Initialization step：
Latch structure real random number generators are realized on FPGA；
Starting of oscillation step：
True random number is occurred module and is started vibration using metastable state phenomenon, occur by counter records true random number
The cycle of oscillation of module, while recording duration of oscillation using FPGA system clock；
Vibrate set-up procedure：
The MUX configuration true random number in module occurs using true random number to occur the different path of module to adjust
Whole cycle of oscillation, cycle of oscillation is set to be more than 70；
Export step：
Extract minimum 2 of counter to export as random number, occur latch structures true random number using metastable state phenomenon
Device produces the true random number for meeting quantity demand.
The present invention is relative to the beneficial effect of prior art：
1st, random number extracting method proposed by the present invention, is that random number is just extracted before latch structure oscillations terminate, with
Existing method is compared, and greatly improves the speed of random number generation.
2nd, random number extracting method proposed by the present invention, has higher robust for the change of temperature, voltage and technique
Property, the data produced at different conditions can pass through NIST Randomness tests.
3rd, random number extracting method proposed by the present invention, is realized in FPGA platform, widely used relative on FPGA
Real random number generator, context of methods has relatively low resource consumption, and new reference is provided for correlative study on FPGA.
Brief description of the drawings
Fig. 1 is the general flow chart of random number extracting method of the present invention.
Fig. 2 is the structural representation of latch structure real random number generators.
Fig. 3 is the structural representation that module occurs for true random number.
Fig. 4 a are basic metastable structure.
Fig. 4 b are metastable state transfer curve.
Fig. 5 is the signal timing diagram of random number extracting method of the present invention.
Fig. 6 is the overall workflow figure of random number extracting method of the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that embodiment described herein is only to explain the present invention,
It is not intended to limit the present invention.
Embodiment 1：
Real random number generator, Development plank system are realized in this experiment on xc6vlx240t-1ffg1156FPGA development boards
Working frequency 50Mhz, normal working voltage 1.0V, 25 DEG C of normal working temperature, Microblaze working frequencies 100Mhz.Software
Comprehensive for the writing of Verilog code using ISE14.3 versions, mapping, placement-and-routing generates bit files.Such as Fig. 1 institutes
Show, the present embodiment provides a kind of random number extracting method based on latch structure real random number generators, wherein：
The concrete structure of latch structure real random number generators is as shown in Fig. 2 soft including the Microblaze being sequentially connected
Module, counter, finite state machine occur for core, true random number；The soft cores of Microblaze respectively with counter and finite state machine
Connection；It is the latch structures using even number door that module, which occurs, for true random number.In fig. 2, Microblaze carries for FPGA
Soft core, utilizes serial ports and interruption control data transmission；To add the true random number of even number door module occurs for latch；
Counter is counter；FMS is finite state machine；Enable signals are used to make true random number generation module latch start to shake
Swing, count is Counter Value, Clear signals are used to empty Counter Value, and TRN is that finite state machine is obtained according to program setting
The counter moment value.The soft cores of Microblaze realize latch structures real random number generator and outside by USB port
Computer HOST (PC) connection.
The concrete structure of module occurs for true random number shown in the present embodiment as shown in figure 1, including 2 selector channels, its
In：Every selector channel includes 1 nor gate being sequentially connected and 2 NOT gate selecting units；Two inputs of nor gate point
Not other alternatively two inputs of passage, the output end of the output end of the NOT gate selecting unit of end alternatively passage.It is non-
Door selecting unit includes 4 NOT gates and 1 MUX, one of the output end correspondence connection MUX of each NOT gate
Input, the inputs of 4 NOT gates is collectively as the input of NOT gate selecting unit, and the output end of MUX is used as NOT gate
The output end of selecting unit.
One input of one selector channel is with an input of another selector channel collectively as true random number
Occurs the input of module, another input of a selector channel is connected with the output end of another selector channel, one
The output end of selector channel is connected with another input of another selector channel, and the output end of two selector channels is made jointly
The output end of module occurs for true random number.
Random number extracting method comprises the following steps：
Step S1, initialization step：
Latch structure real random number generators are realized on FPGA.Specifically include：Defined using default unbound document
Position of the latch structure real random number generators on FPGA；Recycle unbound document to carry out temporal constraint, prevent sequential from disobeying
Rule.To realize that true random number occurs module and 6 Slice are taken in FPGA, wherein 2 are configured to or non-as exemplified by Fig. 3
Door, respectively takes 2 inputs of 1 look-up table.Remaining each structure for being configured to 4 NOT gates one MUXs of connection,
It is each to take 1 look-up table, 6 inputs.
Step S2, starting of oscillation step：
True random number is occurred module and is started vibration using metastable state phenomenon, occur by counter records true random number
The cycle of oscillation of module, while recording duration of oscillation using FPGA system clock.
Simply introduce metastable state phenomenon first, as shown in fig. 4 a, wherein input signal Enable driving A and B two or
NOT gate.As Enable=1, Y1Y2=00.If Fig. 4 b are Y1Y2Transfer curve, it can be seen that Y1Y2=00 is at pressure
In metastable state state.Enable is jumped to 0 from 1, then A, B two is equivalent to phase inverter, therefore Y1And Y2All there is conversion
For the trend of stable state so that structure produces the phenomenon of vibration.Because the door in latch can be by noise and process deviation
Influence, can cause the level signal on wherein one side to be transmitted soon, whole latch structures are finally reached stable state, Y1Y2=01 or
Y1Y2=10, this process is traditional metastable state phenomenon.
The structure of latch structure real random number generators with reference to shown in Fig. 2 is illustrated, and is caused using metastable state phenomenon
True random number occurs module latch structures and starts vibration, and its time sequential routine is as shown in figure 5, wherein Enable signals make for vibration
Energy signal, then latch structures start vibration when Enable trailing edges arrive.Clear signal removal Counter Values, when being 1 all the time
Counter Value is kept to reset.CLK is system clock, for recording how many cycle of having vibrated, and Counter is counter, and record shakes
Swing the cycle.
Step S3, vibrates set-up procedure：
The MUX configuration true random number in module occurs using true random number to occur the different path of module to adjust
Whole cycle of oscillation, cycle of oscillation is set to be more than or equal to 70.
If layout is asymmetric, latch both sides delay inequality is larger, and system deviation is larger, and collapse period can only achieve ten
Several times, random number speed is produced slower.If layout symmetry, latch both sides delay inequality is closely and system deviation is smaller
In the case of, cycle of oscillation can reach hundreds of thousands, with higher speed.The different path by configuring, adjustment vibration
Cycle, cycle of oscillation, which was more than at least 2,70 counters, to be exported as random order to the scope needed.
The concrete configuration method of MUX is as follows herein：NOT gate selecting unit is both that 4 NOT gates connect a multichannel
Selector, the unit is left with one 6 input look-up tables'implementation, two of which input as MUX control port
Four inputs are four NOT gates, when adjusting cycle of oscillation, pass through the value gating that state machine changes MUX control port
Different NOT gates, had both selected different paths.
Step S4, calibration steps：
Before vibration terminates, the sampling time is adjusted using finite state machine, at the time of choosing cycle of oscillation more than or equal to 70
Sampled.
Due to being influenceed by process deviation, the identical sampling time may obtain different knots on different chips
Really, to ensure that the sampling time meets requirement, realize that the true random number occurs module TRNG and is also required on different fpga chips
First calibrated by finite state machine.Calibrating mode is specially：The sampling time is adjusted, collects after 5000 groups of data, judges it
Whether average is more than or equal to 70, is sampled at the time of choosing cycle of oscillation more than or equal to 70；, will if average is less than 70
Sampling time adds 1 backward, continues collection data and is judged, until its average is finished more than or equal to 70 calibrations, subsequent
Random number is gathered using this moment as standard.
Step S5, exports step：
Extract minimum 2 of counter to export as random number, occur latch structures true random number using metastable state phenomenon
Device produces the true random number for meeting quantity demand.
Dead wind area is obeyed because total is metastable state nodule structure, therefore in the count distribution for providing the moment, because
This can be exported using minimum 2 of counter as random number, then this 2 there is identical 0,1 to be distributed.It is complete the step of above
After, follow-up is exactly to produce random number according to demand, and integrated operation flow chart is as shown in fig. 6, according to Fig. 5 sequential not stopping pregnancy
Raw random number, pending data amount meets demand, and then random number output is finished.
In the present embodiment, can also be further in order to which the random number to output is tested, it is ensured that the accuracy of data
Including step S6, testing procedure：
The random number produced using NIST Randomness tests external member to latch structures real random number generator is tested,
Test result exports a series of P values, then represents that the data randomness passes through when P values are more than 0.0001.
In a particular application, NIST SP800-22 standard Randomness test softwares can be used to be tested.Shown in table 1
It is second lowest order of experiment test counter and to collect 1K data at normal temperature and voltage, is understood by test, it is defeated
The data gone out have all passed through 15 NIST Randomness tests, and with higher P values, and higher entropy
(probability that Proportion passes through for 300 times for test).
The LSB NIST test results of table 12
The present invention is relative to the beneficial effect of prior art：
1st, random number extracting method proposed by the present invention, is that random number is just extracted before latch structure oscillations terminate, with
Existing method is compared, and greatly improves the speed of random number generation.
2nd, random number extracting method proposed by the present invention, has higher robust for the change of temperature, voltage and technique
Property, the data produced at different conditions can pass through NIST Randomness tests.
3rd, random number extracting method proposed by the present invention, is realized in FPGA platform, widely used relative on FPGA
Real random number generator, context of methods has relatively low resource consumption, and new reference is provided for correlative study on FPGA.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, it is not used to
The limitation present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the invention etc., it all should include
Within protection scope of the present invention.
Claims (6)
1. a kind of random number extracting method based on latch structure real random number generators, wherein, the latch structures it is true with
Machine number generator includes the soft cores of Microblaze being sequentially connected, and module, counter, finite state machine occur for true random number；
The soft cores of Microblaze are connected with the counter and the finite state machine respectively；Mould occurs for the true random number
Block is the latch structures using even number door；Characterized in that, the random number extracting method comprises the following steps：
Initialization step：
The latch structures real random number generator is realized on FPGA；
Starting of oscillation step：
The true random number is occurred module and is started vibration using metastable state phenomenon, by described in the counter records it is true with
The cycle of oscillation of module occurs for machine number, while recording duration of oscillation using FPGA system clock；
Vibrate set-up procedure：
The MUX in module occurs using the true random number and configures the different path of the true random number generation module
To adjust cycle of oscillation, cycle of oscillation is set to be more than or equal to 70；
Export step：
Extract minimum 2 of the counter to export as random number, make the latch structures true random number using metastable state phenomenon
Generator produces the true random number for meeting quantity demand.
2. the random number extracting method according to claim 1 based on latch structure real random number generators, its feature exists
In, the true random number occurs module and specifically includes 2 selector channels, wherein：
The selector channel includes 1 nor gate being sequentially connected and 2 NOT gate selecting units；Two inputs of the nor gate
Two inputs respectively as the selector channel are held, the output end of the NOT gate selecting unit of end is used as the selection
The output end of passage；
The NOT gate selecting unit includes 4 NOT gates and 1 MUX, the output end correspondence connection institute of each NOT gate
State an input of MUX, the inputs of 4 NOT gates collectively as the NOT gate selecting unit input,
The output end of the MUX as the NOT gate selecting unit output end；
One input of one input of one selector channel and selector channel another described is collectively as described
The input of module, another input and another selector channel of a selector channel occur for true random number
Output end is connected, and the output end of a selector channel is connected with another input of selector channel another described, and two
The output end of module occurs collectively as the true random number for the output end of the individual selector channel.
3. the random number extracting method according to claim 1 or 2 based on latch structure real random number generators, it is special
Levy and be, the initialization step further comprises：
Position of the latch structures real random number generator on FPGA is defined using default unbound document；Recycle institute
State unbound document and carry out temporal constraint, prevent sequential in violation of rules and regulations.
4. the random number extracting method according to claim 1 or 2 based on latch structure real random number generators, it is special
Levy and be, also include calibration steps before the output step：
Before vibration terminates, the sampling time is adjusted using the finite state machine, at the time of choosing cycle of oscillation more than or equal to 70
Sampled.
5. the random number extracting method according to claim 4 based on latch structure real random number generators, its feature exists
In the calibration steps further comprises：
First calibrated using the finite state machine, adjust the sampling time, collected after 5000 groups of data, whether judge its average
More than or equal to 70, sampled at the time of choosing cycle of oscillation more than or equal to 70；If average be less than 70, by the sampling time to
Plus 1 afterwards, continue collection data and judged, until its average is finished more than or equal to 70 calibrations, subsequent random number collection
Using this moment as standard.
6. the random number extracting method according to claim 1 or 2 based on latch structure real random number generators, it is special
Levy and be, also include testing procedure after the output step：
The random number produced using NIST Randomness tests external member to the latch structures real random number generator is tested,
Test result exports a series of P values, then represents that the data randomness passes through when P values are more than 0.0001.
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| CN111966330A (en) * | 2020-09-02 | 2020-11-20 | 湖北大学 | True random number generator based on Venturi bridge oscillator structure |
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| CN110825347A (en) * | 2018-08-09 | 2020-02-21 | 旺宏电子股份有限公司 | Adjustable random number generation circuit and adjustable random number generation method |
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| CN111966330A (en) * | 2020-09-02 | 2020-11-20 | 湖北大学 | True random number generator based on Venturi bridge oscillator structure |
| CN111966330B (en) * | 2020-09-02 | 2022-06-17 | 湖北大学 | True random number generator based on Venturi bridge oscillator structure |
| CN113835679A (en) * | 2021-09-30 | 2021-12-24 | 海宁奕斯伟集成电路设计有限公司 | Random number generation method, device and system |
| CN113835679B (en) * | 2021-09-30 | 2023-09-29 | 海宁奕斯伟集成电路设计有限公司 | Random number generation method, device and system |
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