CN107015846B - Simulation method and device for realizing eukaryon simulation of processor - Google Patents
Simulation method and device for realizing eukaryon simulation of processor Download PDFInfo
- Publication number
- CN107015846B CN107015846B CN201710243286.XA CN201710243286A CN107015846B CN 107015846 B CN107015846 B CN 107015846B CN 201710243286 A CN201710243286 A CN 201710243286A CN 107015846 B CN107015846 B CN 107015846B
- Authority
- CN
- China
- Prior art keywords
- instruction
- simulation
- breakpoint
- simulated
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004088 simulation Methods 0.000 title claims abstract description 154
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000012545 processing Methods 0.000 claims abstract description 30
- 230000006399 behavior Effects 0.000 claims description 12
- 210000003527 eukaryotic cell Anatomy 0.000 claims description 10
- 230000002159 abnormal effect Effects 0.000 claims description 8
- 241000206602 Eukaryota Species 0.000 abstract description 5
- 238000011161 development Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
- G06F9/45516—Runtime code conversion or optimisation
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The embodiment of the invention discloses a simulation method and a device for realizing eukaryon simulation of a processor. The method comprises the following steps: s1, acquiring a program counter value according to a target simulation program; s2, acquiring a simulation instruction from a memory according to the program counter value; s3, if the simulation instruction is a breakpoint instruction, performing breakpoint processing according to a breakpoint execution type and the simulation state of the simulated eukaryon; s4, the simulated eukaryotic body switches the running state to a preset running state; and S5, if the simulation instruction is a non-breakpoint instruction, executing the simulation instruction, and returning to the step of executing S1 until a simulation result is obtained. According to the simulation method for realizing the simulated eukaryote of the processor, the breakpoint instruction is added into the simulation program, and the debugging of the program can be processed in a segmented mode, so that the flexibility of the simulation process is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of simulation processing, in particular to a simulation method and a simulation device for realizing eukaryon simulation of a processor.
Background
The processor emulation core virtual operating system is a software system capable of performing complete simulation on an embedded hardware system. The user can simulate the running of the embedded software on the system, and the embedded software can be tested and debugged without corresponding hardware. By using the system, a user can not only greatly shorten the development period of the embedded software, but also avoid the high development cost of auxiliary test hardware and greatly reduce the system cost. The system can be widely applied to the development fields of embedded systems of aviation, aerospace, weaponry, automobiles, robots, industrial control and the like, the labor production efficiency of the industries is improved, the cost is reduced, and the competitive power of products is enhanced.
In the prior art, when a processor simulation core virtual running system is used for simulation, the flexibility in debugging operation is poor.
Disclosure of Invention
The invention provides a simulation method and a device for realizing simulation of a processor to simulate an eukaryotic cell, so as to improve the flexibility of a simulation process.
In a first aspect, an embodiment of the present invention provides a simulation method for realizing processor eukaryotic simulation, where the method includes:
s1, acquiring a program counter value according to a target simulation program;
s2, acquiring a simulation instruction from a memory according to the program counter value;
s3, if the simulation instruction is a breakpoint instruction, performing breakpoint processing according to a breakpoint execution type and the simulation state of the simulated eukaryon;
s4, the simulated eukaryotic body switches the running state to a preset running state;
and S5, if the simulation instruction is a non-breakpoint instruction, executing the simulation instruction, and returning to the step of executing S1 until a simulation result is obtained.
Further, if the emulation instruction is a breakpoint instruction, performing breakpoint processing according to a breakpoint execution type and the emulation state of the emulated eukaryote, including:
if the currently executed code acts as a non-breakpoint instruction, configuring at least one breakpoint instruction, and setting the simulation state of the simulated eukaryotic system to be a continuous state; setting the counter value of an initial program as the current line, and starting the simulated eukaryotic cell;
if the currently executed code behavior breakpoint instruction is executed, setting the simulated eukaryotic state as a single-step state, setting an initial program counter value as a current line, starting the simulated eukaryotic, configuring at least one breakpoint instruction, setting the simulated state of the simulated eukaryotic as a continuous state, setting the initial program counter value as the current line, and starting the simulated eukaryotic;
and restoring the at least one breakpoint instruction to be the original instruction.
Further, if the emulation instruction is a breakpoint instruction, performing breakpoint processing according to a breakpoint execution type and the emulation state of the emulated eukaryote, including:
if the currently executed code acts as a non-breakpoint instruction, configuring at least one breakpoint instruction, and setting the simulation state of the simulated eukaryotic system to be a single-step state; setting the counter value of an initial program as the current line, and starting the simulated eukaryotic cell;
if the current executed code behavior breakpoint instruction is in, setting the simulated eukaryotic state as a single-step state, setting an initial program counter value as a current line, and starting the simulated eukaryotic;
and restoring the at least one breakpoint instruction to be the original instruction.
Further, the configuring at least one breakpoint instruction includes:
and (4) checking the breakpoint instruction through a debugging tool GDB and simulation to set.
Further, the obtaining the emulation instruction from the memory according to the program counter value includes:
acquiring a binary instruction from a memory according to the program counter value;
judging whether the simulation process is abnormal or not;
and if no exception occurs, decoding the binary instruction to obtain the simulation instruction.
In a second aspect, an embodiment of the present invention further provides a simulation apparatus for implementing a processor simulation core, where the apparatus includes:
the program counter value acquisition module is used for acquiring a program counter value according to a target simulation program;
the simulation instruction acquisition module is used for acquiring a simulation instruction from a memory according to the program counter value;
the breakpoint processing module is used for carrying out breakpoint processing according to the breakpoint execution type and the simulation state of the simulated eukaryotic system when the simulation instruction is a breakpoint instruction;
the operation state switching module is used for switching the operation state of the simulated eukaryotic body to a preset operation state;
and the simulation instruction execution module is used for executing the simulation instruction when the simulation instruction is a non-breakpoint instruction.
Further, the breakpoint processing module is further configured to:
if the currently executed code acts as a non-breakpoint instruction, configuring at least one breakpoint instruction, and setting the simulation state of the simulated eukaryotic system to be a continuous state; setting the counter value of an initial program as the current line, and starting the simulated eukaryotic cell;
if the currently executed code behavior breakpoint instruction is executed, setting the simulated eukaryotic state as a single-step state, setting an initial program counter value as a current line, starting the simulated eukaryotic, configuring at least one breakpoint instruction, setting the simulated state of the simulated eukaryotic as a continuous state, setting the initial program counter value as the current line, and starting the simulated eukaryotic;
and restoring the at least one breakpoint instruction to be the original instruction.
Further, the breakpoint processing module is further configured to:
if the currently executed code acts as a non-breakpoint instruction, configuring at least one breakpoint instruction, and setting the simulation state of the simulated eukaryotic system to be a single-step state; setting the counter value of an initial program as the current line, and starting the simulated eukaryotic cell;
if the current executed code behavior breakpoint instruction is in, setting the simulated eukaryotic state as a single-step state, setting an initial program counter value as a current line, and starting the simulated eukaryotic;
and restoring the at least one breakpoint instruction to be the original instruction.
Further, the breakpoint processing module is further configured to:
and (4) checking the breakpoint instruction through a debugging tool GDB and simulation to set.
Further, the simulation instruction obtaining module is further configured to:
acquiring a binary instruction from a memory according to the program counter value;
judging whether the simulation process is abnormal or not;
and if no exception occurs, decoding the binary instruction to obtain the simulation instruction.
According to the embodiment of the invention, a program counter value is obtained according to a target simulation program, then a simulation instruction is obtained from a memory according to the program counter value, if the simulation instruction is a breakpoint instruction, breakpoint processing is carried out according to a breakpoint execution type and a simulation state of an artificial eukaryotic system, then the artificial eukaryotic system switches the running state to a preset running state, and if the simulation instruction is a non-breakpoint instruction, the simulation instruction is executed until a simulation result is obtained. In the prior art, when a processor simulation core virtual running system is used for simulation, debugging can be performed only after the whole program is executed, so that the flexibility in debugging operation is poor. In the application, the breakpoint instruction is added into the simulation program, and the debugging of the program can be processed in a segmented mode, so that the flexibility of the simulation process is improved.
Drawings
FIG. 1 is a flowchart of a simulation method for simulating an eukaryotic system by a processor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an emulation apparatus for implementing a processor emulation core according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a flowchart of a simulation method for simulating an eukaryotic system by a processor according to an embodiment of the present invention, where the present embodiment is applicable to a case of simulation by a simulation verification program, and the method may be executed by a server, as shown in fig. 1, and the method specifically includes the following steps:
s1, obtaining the program counter value according to the target simulation program.
Among them, a Program Counter (PC) may be used to store an address of an instruction. In this embodiment, when the target program is executed, the initial value of the PC is the address of the first instruction of the target program, and when the target program is executed sequentially, the server first fetches an instruction from the memory according to the instruction address pointed by the PC, and then analyzes and executes the instruction, and the PC value points to the next instruction to be executed.
And updating the PC value according to the structure of the pipeline. The structure of the pipeline may include one stage, three stages, five stages, seven stages, and the like. Illustratively, taking a three-stage pipeline structure as an example, the storage variables in the three-stage pipeline include an instruction fetch segment, a decode segment, and an execution segment. In the simulation, before each instruction is executed, the pipeline needs to be updated, and the following two cases need to be considered in updating.
When the pipeline is in normal conditions, a sequential filling of the pipeline is required before each execution of an instruction. When filling the pipeline, firstly, the PC value is moved forward by 4 bytes to point to the address of the next instruction entering the pipeline; then, the address value of the currently executed instruction will also move forward by 4 bytes to obtain the next instruction to be executed, and meanwhile, the instruction in the decoding stage in the current pipeline will become the instruction in the instruction fetching stage in the last pipeline; finally, the instruction fetch stage will fetch new instructions from memory to fill the pipeline.
When the pipeline is blocked, it is necessary to refill the pipeline. That is, the contents in the existing pipeline are flushed, and it is necessary to fetch the instruction from the current program counter value again, then sequentially fetch the instruction 3 times, and sequentially fill in the pipeline to form a new pipeline structure.
Optionally, when adjusting the program counter value, the following situations need to be considered respectively:
when the emulated instruction is a jump instruction, the program counter value should be equal to the current program counter value plus the offset field. Also, the pipeline needs to be flushed again before the next execution of the instruction.
When the emulation instruction is an interrupt instruction, and the interrupt does not occur at the breakpoint instruction. After the interrupt is generated, the program will be fetched to a new address and executed, and therefore, the program counter value needs to be changed. However, after the interrupt processing is completed, it is necessary to return to the instruction address at the time of the generation of the interrupt.
When the emulation instruction is an interrupt instruction, and the interrupt occurs on the breakpoint instruction. When the interrupt returns, the address pointed to by the PC value-8 is returned instead of the address pointed to by the PC value-4.
S2, the simulation instruction is obtained from the memory according to the program counter value.
The server retrieves the emulation instructions from memory according to the address pointed to by the program counter value. Preferably, the process of obtaining the emulation instruction from the memory according to the program counter value may be that a binary instruction is obtained from the memory according to the program counter value, whether the emulation process is abnormal is judged, and if the emulation process is not abnormal, the binary instruction is decoded to obtain the emulation instruction. The decoding process may be a process of parsing the binary instruction.
Optionally, if an exception occurs in the simulation process, the simulation core is switched to the exception mode. The mode of switching to the abnormal mode includes: switch mode, switch register, and switch specified mode PC values. And after the exception handling is finished, the simulation core returns to the original simulation process, and the PC value is obtained again to continue the simulation.
Optionally, if the exception is an interrupt, the simulation core switches to an interrupt mode. And after the interrupt processing is finished, returning to the interrupt, and continuing the simulation from the interrupted place by the simulation core.
And S3, if the simulation instruction is a breakpoint instruction, performing breakpoint processing according to the breakpoint execution type and the simulation state of the simulated eukarya.
The breakpoint instruction may be an instruction to stop the emulation flow. The execution types of breakpoints may include continuous execution and single-stepping. The program breakpoint instruction is obtained by replacing instructions at certain positions in the program with breakpoint instructions according to simulation needs. And when the simulation instruction obtained by decoding is a breakpoint instruction, the simulation process is marked as a 'stop' state, and the simulation process is exited. Meanwhile, breakpoint processing is carried out according to the execution type of the breakpoint and the simulation state of the simulated eukaryon.
Preferably, the method for breakpoint handling according to the breakpoint execution type and the simulation state of the simulated eukaryote may include the following two cases.
When the breakpoint execution type is continuous execution, if the currently executed code acts as a non-breakpoint instruction, configuring at least one breakpoint instruction, and setting the simulation state of the simulated eukaryotic system to be a continuous state; setting the counter value of the initial program as the current line, and starting the simulated eukaryotic system. If the currently executed code behavior breakpoint instruction is in a single-step state, setting the simulation core state as a single-step state, setting the initial program counter value as a current line, starting the simulated eukaryotic system, configuring at least one breakpoint instruction, setting the simulation state of the simulated eukaryotic system as a continuous state, setting the initial program counter value as the current line, and starting the simulated eukaryotic system. And restoring at least one breakpoint instruction to be the original instruction.
When the breakpoint execution type is single-step execution, if the currently executed code acts as a non-breakpoint instruction, configuring at least one breakpoint instruction, and setting the simulation state of the simulated eukaryotic system to be a single-step state; setting the counter value of the initial program as the current line, and starting the simulated eukaryotic system. And if the currently executed code behavior breakpoint instruction is in a single-step state, setting the state of the simulation core, setting the counter value of the initial program as the current line, and starting the simulation core. And restoring at least one breakpoint instruction to be the original instruction.
Preferably, the at least one breakpoint instruction may be configured in a manner that the breakpoint instruction is set through the debugging tool GDB and the simulation core.
And S4, switching the running state to a preset running state by the simulated eukaryotic system.
The operation state may include a continuous operation state and a single step execution state. The user can switch the running state according to the simulation requirement.
S5, if the simulation instruction is a non-breakpoint instruction, executing the simulation instruction, and returning to execute the step S1 until a simulation result is obtained.
The non-breakpoint instruction may include a jump instruction, a memory access instruction, a register access instruction, and the like. When the decoding result is a jump instruction, if the jump instruction is not carried out, executing according to the current sequence; if the program counter value is skipped, the current program counter value needs to be added with an offset field to obtain the skipped program counter value. And when the decoding result is the access instruction, accessing the memory space of the instruction. And when the decoding result is the instruction for accessing the register, the specified register is accessed. And when the simulation core finishes executing the simulation instruction, returning to the step S1, re-acquiring the counter value of the program, and circularly performing the processes of instruction fetching, decoding and executing until a simulation result of the program is obtained.
According to the technical scheme of the embodiment, a program counter value is obtained according to a target simulation program, then a simulation instruction is obtained from a memory according to the program counter value, if the simulation instruction is a breakpoint instruction, breakpoint processing is carried out according to a breakpoint execution type and a simulation state of an artificial eukaryotic system, then the artificial eukaryotic system switches the running state to a preset running state, and if the simulation instruction is a non-breakpoint instruction, the simulation instruction is executed until a simulation result is obtained. In the prior art, when a processor simulation core virtual running system is used for simulation, debugging can be performed only after the whole program is executed, so that the flexibility in debugging operation is poor. In the application, the breakpoint instruction is added into the simulation program, and the debugging of the program can be processed in a segmented mode, so that the flexibility of the simulation process is improved.
Example two
Fig. 2 is a schematic structural diagram of a simulation apparatus for implementing a processor simulation core according to a second embodiment of the present invention. As shown in fig. 2, the apparatus includes: a program counter value obtaining module 210, an emulation instruction obtaining module 220, a breakpoint processing module 230, a running state switching module 240, and an emulation instruction executing module 250.
A program counter value obtaining module 210, configured to obtain a program counter value according to a target simulation program;
a simulation instruction obtaining module 220, configured to obtain a simulation instruction from a memory according to the program counter value;
a breakpoint processing module 230, configured to, when the simulation instruction is a breakpoint instruction, perform breakpoint processing according to a breakpoint execution type and a simulation state of the simulated eukaryotic system;
an operation state switching module 240, configured to switch an operation state to a preset operation state by simulating an eukaryotic cell;
and the simulation instruction execution module 250 is configured to execute the simulation instruction when the simulation instruction is a non-breakpoint instruction.
Further, the breakpoint processing module 230 is further configured to:
if the currently executed code acts as a non-breakpoint instruction, configuring at least one breakpoint instruction, and setting the simulation state of the simulated eukaryotic system to be a continuous state; setting the counter value of the initial program as the current line, and starting the simulated eukaryotic system;
if the currently executed code behavior breakpoint instruction is executed, setting the simulation core state as a single-step state, setting the initial program counter value as a current line, starting the simulated eukaryotic system, configuring at least one breakpoint instruction, setting the simulation state of the simulated eukaryotic system as a continuous state, setting the initial program counter value as the current line, and starting the simulated eukaryotic system;
and restoring at least one breakpoint instruction to be the original instruction.
Further, the breakpoint processing module 230 is further configured to:
if the currently executed code acts as a non-breakpoint instruction, configuring at least one breakpoint instruction, and setting the simulation state of the simulated eukaryotic system to be a single-step state; setting the counter value of the initial program as the current line, and starting the simulated eukaryotic system;
if the currently executed code behavior breakpoint instruction is received, setting the simulation core state as a single-step state, setting the initial program counter value as the current line, and starting the simulation core;
and restoring at least one breakpoint instruction to be the original instruction.
Further, the breakpoint processing module 230 is further configured to:
and (4) checking the breakpoint instruction through a debugging tool GDB and simulation to set.
Further, the simulation instruction obtaining module 220 is further configured to:
acquiring a binary instruction from a memory according to the value of the program counter;
judging whether the simulation process is abnormal or not;
and if no exception occurs, decoding the binary instruction to obtain the simulation instruction.
The product can execute the method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (6)
1. A simulation method for realizing simulation of eukaryotic system by a processor is characterized by comprising the following steps:
s1, acquiring a program counter value according to a target simulation program;
s2, acquiring a simulation instruction from a memory according to the program counter value;
s3, if the simulation instruction is a breakpoint instruction, performing breakpoint processing according to a breakpoint execution type and the simulation state of the simulated eukaryon;
s4, the simulated eukaryotic body switches the running state to a preset running state;
s5, if the simulation instruction is a non-breakpoint instruction, executing the simulation instruction, and returning to the step of executing S1 until a simulation result is obtained;
wherein, if the simulation instruction is a breakpoint instruction, performing breakpoint processing according to a breakpoint execution type and the simulation state of the simulated eukaryon, including:
when the breakpoint execution type is continuous execution, if the currently executed code acts as a non-breakpoint instruction, configuring at least one breakpoint instruction, and setting the simulation state of the simulated eukaryotic system to be a continuous state; setting the counter value of an initial program as the current line, and starting the simulated eukaryotic cell; if the currently executed code behavior breakpoint instruction is executed, setting the simulated eukaryotic state as a single-step state, setting an initial program counter value as a current line, starting the simulated eukaryotic, configuring at least one breakpoint instruction, setting the simulated state of the simulated eukaryotic as a continuous state, setting the initial program counter value as the current line, and starting the simulated eukaryotic; restoring the at least one breakpoint instruction to be an original instruction;
wherein, if the simulation instruction is a breakpoint instruction, performing breakpoint processing according to a breakpoint execution type and the simulation state of the simulated eukaryon, including:
when the breakpoint execution type is single-step execution, if the currently executed code acts as a non-breakpoint instruction, configuring at least one breakpoint instruction, and setting the simulation state of the simulated eukaryotic system to be a single-step state; setting the counter value of an initial program as the current line, and starting the simulated eukaryotic cell; if the current executed code behavior breakpoint instruction is in, setting the simulated eukaryotic state as a single-step state, setting an initial program counter value as a current line, and starting the simulated eukaryotic; and restoring the at least one breakpoint instruction to be the original instruction.
2. The emulation method of implementing a processor emulation eukaryotic according to claim 1, wherein configuring the at least one breakpoint instruction comprises:
and (4) checking the breakpoint instruction through a debugging tool GDB and simulation to set.
3. The method of claim 1, wherein the retrieving emulation instructions from memory based on the program counter value comprises:
acquiring a binary instruction from a memory according to the program counter value;
judging whether the simulation process is abnormal or not;
and if no exception occurs, decoding the binary instruction to obtain the simulation instruction.
4. An emulation apparatus for implementing a processor emulation core, comprising:
the program counter value acquisition module is used for acquiring a program counter value according to a target simulation program;
the simulation instruction acquisition module is used for acquiring a simulation instruction from a memory according to the program counter value;
the breakpoint processing module is used for carrying out breakpoint processing according to the breakpoint execution type and the simulation state of the simulated eukaryotic system when the simulation instruction is a breakpoint instruction;
the operation state switching module is used for switching the operation state of the simulated eukaryotic body to a preset operation state;
the simulation instruction execution module is used for executing the simulation instruction when the simulation instruction is a non-breakpoint instruction;
wherein the breakpoint processing module is further configured to:
when the breakpoint execution type is continuous execution, if the currently executed code acts as a non-breakpoint instruction, configuring at least one breakpoint instruction, and setting the simulation state of the simulated eukaryotic system to be a continuous state; setting the counter value of an initial program as the current line, and starting the simulated eukaryotic cell; if the currently executed code behavior breakpoint instruction is executed, setting the simulated eukaryotic state as a single-step state, setting an initial program counter value as a current line, starting the simulated eukaryotic, configuring at least one breakpoint instruction, setting the simulated state of the simulated eukaryotic as a continuous state, setting the initial program counter value as the current line, and starting the simulated eukaryotic; restoring the at least one breakpoint instruction to be an original instruction;
wherein the breakpoint processing module is further configured to:
when the breakpoint execution type is single-step execution, if the currently executed code acts as a non-breakpoint instruction, configuring at least one breakpoint instruction, and setting the simulation state of the simulated eukaryotic system to be a single-step state; setting the counter value of an initial program as the current line, and starting the simulated eukaryotic cell; if the current executed code behavior breakpoint instruction is in, setting the simulated eukaryotic state as a single-step state, setting an initial program counter value as a current line, and starting the simulated eukaryotic; and restoring the at least one breakpoint instruction to be the original instruction.
5. The emulation apparatus for implementing a processor emulation core of claim 4, wherein the breakpoint processing module is further configured to:
and (4) checking the breakpoint instruction through a debugging tool GDB and simulation to set.
6. The emulation apparatus for implementing a processor emulation core of claim 4, wherein the emulation instruction obtaining module is further configured to:
acquiring a binary instruction from a memory according to the program counter value;
judging whether the simulation process is abnormal or not;
and if no exception occurs, decoding the binary instruction to obtain the simulation instruction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710243286.XA CN107015846B (en) | 2017-04-14 | 2017-04-14 | Simulation method and device for realizing eukaryon simulation of processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710243286.XA CN107015846B (en) | 2017-04-14 | 2017-04-14 | Simulation method and device for realizing eukaryon simulation of processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107015846A CN107015846A (en) | 2017-08-04 |
| CN107015846B true CN107015846B (en) | 2020-08-14 |
Family
ID=59446066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710243286.XA Expired - Fee Related CN107015846B (en) | 2017-04-14 | 2017-04-14 | Simulation method and device for realizing eukaryon simulation of processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107015846B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108182083B (en) * | 2017-12-06 | 2021-12-24 | 中国航空工业集团公司西安航空计算技术研究所 | Instruction fetching decoding circuit supporting breakpoint debugging |
| CN114442506A (en) * | 2021-12-06 | 2022-05-06 | 埃夫特智能装备股份有限公司 | Simulation debugging platform based on virtual robot controller and debugging method thereof |
| CN115018466B (en) * | 2022-06-28 | 2023-07-25 | 北京世冠金洋科技发展有限公司 | Simulation control method and device, storage medium and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101178685A (en) * | 2007-09-27 | 2008-05-14 | 上海大学 | Enhancement type microprocessor piece on-chip dynamic state tracking method with special function register breakpoints |
| CN104239201A (en) * | 2013-06-20 | 2014-12-24 | 上海博达数据通信有限公司 | Memory read-write monitoring method in flexible single-step system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7299456B2 (en) * | 2003-09-18 | 2007-11-20 | International Business Machines Corporation | Run into function |
-
2017
- 2017-04-14 CN CN201710243286.XA patent/CN107015846B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101178685A (en) * | 2007-09-27 | 2008-05-14 | 上海大学 | Enhancement type microprocessor piece on-chip dynamic state tracking method with special function register breakpoints |
| CN104239201A (en) * | 2013-06-20 | 2014-12-24 | 上海博达数据通信有限公司 | Memory read-write monitoring method in flexible single-step system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107015846A (en) | 2017-08-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110580226B (en) | Object code coverage rate testing method, system and medium for operating system level program | |
| CN107015846B (en) | Simulation method and device for realizing eukaryon simulation of processor | |
| CN109144515B (en) | Off-line simulation method and device for DCS graphical algorithm configuration | |
| CN109213680B (en) | Automatic testing method based on embedded software simulator | |
| WO2009087158A4 (en) | Compare and branch facility and instruction therefore | |
| JP2015060600A (en) | Testing device for real-time testing of virtual control unit | |
| US20120101791A1 (en) | Controlling simulation systems | |
| WO2014196059A1 (en) | Microcontroller fault injection method and system | |
| JP2008310727A (en) | Simulation system and simulation method | |
| US20130254750A1 (en) | Method of debugging software and corresponding computer program product | |
| EP3765963B1 (en) | Tracing branch instructions | |
| CN104866345A (en) | Storage method of executable code under ARMv7m architecture | |
| CN111045730B (en) | Hardware rapid interrupt processing system and method for RISC-V architecture | |
| US9111034B2 (en) | Testing of run-time instrumentation | |
| US20050050524A1 (en) | Generating software test information | |
| CN104731557A (en) | Control method and device for instruction execution | |
| CN110727577B (en) | Debugging method, system and medium for probability reproduction problem in embedded system software | |
| WO2021247074A1 (en) | Resumable instruction generation | |
| CN103197959B (en) | A kind of changing method of multi-core CPU | |
| US6772372B2 (en) | System and method for monitoring unaligned memory accesses | |
| CN111324948A (en) | Simulation method and simulation system | |
| CN117555555B (en) | Exception processing method, device, electronic equipment and storage medium | |
| KR101761732B1 (en) | Apparatus and method for detecting error of application source code | |
| Lee et al. | Fast Verilog Simulation using Tel-based Verification Code Generation for Dynamically Reloading from Pre-Simulation Snapshot | |
| US9830174B2 (en) | Dynamic host code generation from architecture description for fast simulation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200814 |