CN106981472A - Package substrate - Google Patents
Package substrate Download PDFInfo
- Publication number
- CN106981472A CN106981472A CN201610027874.5A CN201610027874A CN106981472A CN 106981472 A CN106981472 A CN 106981472A CN 201610027874 A CN201610027874 A CN 201610027874A CN 106981472 A CN106981472 A CN 106981472A
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- China
- Prior art keywords
- conduction region
- layer
- circuit element
- conductive
- package substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
The present invention discloses a kind of package substrate, and it includes：One first conductive layer, includes one first conduction region and one second conduction region；One encapsulation unit layer, it is arranged on first conductive layer, and include one first circuit element, one first conductive pole and an adhesive material, first circuit element connects the second connection end of second conduction region with first connection end for connecting first conduction region and one, and first conductive pole connects first conduction region；And one second conductive layer, it is arranged on encapsulation unit layer, and include first metal routing for connecting first conductive pole.
Description
Technical field
The present invention relates to a kind of package substrate technology.
Background technology
The electronic product of a new generation not only pursues compact, develops more towards multi-functional with high performance direction,
Therefore, integrated circuit (Integrated Circuit, abbreviation IC) technology constantly densification and miniaturization, with
Phase accommodates more electronic components in limited die space, and the package substrate of its rear end and its structure fill technology
Also it is in progress therewith, to meet the electronic product trend that this is of new generation.
Conventional art often carrys out structure dress package substrate based on core board (Core substrate), for example, Figure 1A~
Fig. 1 D are diagrammatic cross-section of the existing package substrate in different fabrication steps.Put in circuit element 14a, 14b
Enter before core board 11, prior art can first make upper strata metallic circuit in the upper and lower surface of core board 11
12 and lower metal circuit 13, as shown in Figure 1A.Then opened in circuit element 14a, 14b precalculated position
If openning, and paste temporary film carrier 15 in the lower section of lower metal circuit 13, by circuit element 14a,
14b inserts the openning of core board 11, as shown in Figure 1B.Be subsequently formed insulating barrier 16, by core board 11,
Upper strata metallic circuit 12, lower metal circuit 13 and circuit element 14a, 14b are all coated, and are made
The conducting of upper strata metallic circuit 12, lower metal circuit 13 and circuit element 14a, 14b outwards to connect
Hole 17, as shown in Figure 1 C.Eventually form the conductive metal layer 18 for filling up via hole 17 so that metallic circuit
12nd, lower metal circuit 13 and circuit element 14a, 14b are able to outside externally connected circuit.However,
Above-mentioned openning is opened up in needing the process technology of costliness in core board 11, above-mentioned via hole 17 is made in exhausted
The problem of levels layout contraposition (alignment) is had in edge layer 16, thereby increases and it is possible to laser beam drilling skill can be selected
Art and cause process time tediously long.Therefore, it is necessary to develop new package substrate technology, to solve the above problems.
The content of the invention
To reach this purpose, according to an aspect of the present invention, an embodiment provides a kind of package substrate, and it is wrapped
Include：One first conductive layer, includes one first conduction region and one second conduction region；One encapsulation unit layer, is set
In on first conductive layer, and comprising one first circuit element, one first conductive pole and an adhesive material,
First circuit element connects second conduction region with first connection end for connecting first conduction region and one
The second connection end, and first conductive pole connects first conduction region；And one second conductive layer, set
In the encapsulation unit layer on, and include one connect first conductive pole the first metal routing.
In one embodiment, first circuit element is IC wafer or monolithic ceramic capacitor.
In one embodiment, the adhesive material be filled in encapsulation unit layer first circuit element and this
Remainder outside one conductive pole.
In one embodiment, encapsulation unit layer further includes one second conductive pole, and second conductive layer enters
One step includes one second metal routing, and second conductive pole connects second conduction region and walked with second metal
Line.
In one embodiment, encapsulation unit layer further includes a second circuit element, and it has a connection
3rd connection end of first conduction region.
In one embodiment, the encapsulation unit layer further comprising a second circuit element, one second conductive pole,
And one the 3rd conductive pole, first conductive layer further includes one the 3rd conduction region, second circuit element tool
There are the 3rd connection end of a connection first conduction region and the 4th connection end of the 3rd conduction region of connection, should
Second conductive pole connects second conduction region, and the 3rd conductive pole connects the 3rd conduction region.
In one embodiment, encapsulation unit layer further includes a connection unit, and second conductive layer enters one
Step includes one second metal routing, and the second connection end of first circuit element is connected by the connection unit
Second metal routing.
In one embodiment, encapsulation unit layer is further single comprising one first connection unit, one second connection
Member and one the 3rd connection unit, second conductive layer further include one second metal routing and one the 3rd gold medal
Belong to cabling, the second connection end of first circuit element connects second metal by first connection unit and walked
Line, the first connection end of first circuit element connects the 3rd metal routing by second connection unit,
And the 3rd connection end of the second circuit element connects first metal routing by the 3rd connection unit.
Brief description of the drawings
The section of the different fabrication steps of package substrates of Figure 1A~Fig. 1 D for correspondence based on core board shows
It is intended to.
Fig. 2 is the upper viewing view of the package substrate according to first embodiment of the invention.
Fig. 3 is then the section of structure for cutting and obtaining the package substrate along Fig. 2 straight line AA '.
Fig. 4 A~Fig. 4 E are the section of structure of each fabrication steps of correspondence the present embodiment package substrate.
Fig. 5 is the section of structure of the package substrate according to second embodiment of the invention.
Description of reference numerals：11 core boards；12 upper strata metallic circuits；13 lower metal circuits；14a、14b
Circuit element；15 temporary film carriers；16 insulating barriers；17 via holes；18 conductive metal layers；100th, 200 envelope
Fill substrate；120 first conductive layers；121 first conduction regions；122 second conduction regions；123 the 3rd conduction regions；
130 encapsulation units layer；131 first circuit elements；131a, 131b connection end；132 first conductive poles；133
Adhesive material；134 second circuit elements；134a, 134b connection end；135 second conductive poles；137 the 3rd
Conductive pole；138 first connection units；139 second connection units；239 the 3rd connection units；140 second
Conductive layer；141 first metal routings；142 second metal routings；143 the 3rd metal routings；145 protections
Layer；150 connection gaskets.
Embodiment
Have further cognitive with understanding for feature, purpose and function to the present invention, hereby coordinate schema detailed
Bright embodiments of the invention are described in detail as after.In all specifications and diagram, it will be compiled using identical element
Number with specify same or similar element.
In the explanation of each embodiment, when an element be described be another element " top/on " or " under
Side/under ", refer to either directly or indirectly the upper of another element or under situation, it may be comprising setting
It is placed in other elements therebetween；So-called " directly " refers to therebetween and is not provided with other intermediary elements." on
Side/on " or the description of " lower section/under " etc. be to be illustrated on the basis of schema, it is but also possible comprising other
Direction changes.So-called " first ", " second " and " the 3rd " system to describe different elements,
These elements are not restricted because of such meaning diction.It is each in schema for the facility on illustrating and clearly
The thickness or size of element, be by exaggerate or omit or outline in the way of represent, and each element size not
Completely its actual size.
Fig. 2 is the upper viewing view of the package substrate 100 according to first embodiment of the invention, and it is the encapsulation
The layout of the encapsulation unit layer 130 of substrate 100, and Fig. 3 then obtains to be cut along Fig. 2 straight line AA '
The section of structure of the package substrate 100.The package substrate 100 is included：One first conductive layer 120, an envelope
Fill the conductive layer 140 of elementary layer 130 and 1 second.First conductive layer 120 includes an at least metal routing
Or conduction region, to form the lower circuit of the package substrate 100, as illustrated, first conductive layer 120
Include the first conduction region 121, the second conduction region 122 and the 3rd conduction region 123.Encapsulation unit layer 130
It is arranged on first conductive layer 120, and includes an at least circuit element and an at least conductive pole.This is at least
One circuit element can be IC wafer or surface mount element (Surface Mounted Device, letter
Claim SMD), for example, monolithic ceramic capacitor (Multi-Layer Ceramic Capacitor, abbreviation MLCC),
As illustrated, encapsulation unit layer 130 includes one first circuit element 131 and a second circuit element 134.
An at least conductive pole can be the column of metal material, for example, copper post, it passes through encapsulation unit layer
130, to connect first conductive layer 120 (lower circuit of the package substrate 100) and second conductive layer 140
(the upper strata circuit of the package substrate 100), as illustrated, encapsulation unit layer 130 includes one first conductive pole
132 and one second conductive pole 135.The adhesive material 133 is filled in this described in encapsulation unit layer 130
Remainder outside a little circuit elements 131,134 and these described conductive poles 132,135, by institute
These circuit elements 131,134 and these described conductive poles 132,135 stated encapsulate and are fixed on the envelope
Fill in elementary layer 130.Second conductive layer 140 is arranged on encapsulation unit layer 130, and comprising at least
One metal routing or conduction region, to form the upper strata circuit of the package substrate 100, as illustrated, this second
Conductive layer 140 includes the first metal routing 141 and the second metal routing 142.The adhesive material 133 can be by fitting
Close top mold (Top Molding), compression mold (Compression Molding), conversion mold (Transfer
Molding) or injection mold (Injection Molding) etc. technology and select the adhesive material that suitably insulate
(Molding Compound) is constituted, for example, phenolic group resin (Novolac-Based Resin), epoxy radicals
Resin (Epoxy-Based Resin) or silicone (Silicone-Based Resin), to reduce the encapsulation list
The thickness of first layer 130, and can effectively prevent the package substrate 100 from occurring prying or deformation.
In the present embodiment, these described circuit elements 131,134 rely on the connection gasket (Pad) of conductive material
150 and affix directly to first conductive layer 120, it is comparatively simple in making and without levels be laid out contraposition asking
Topic, helps to reduce the manufacturing cost of package substrate.Above-mentioned 150 need of the connection gasket by screen printing or
It is ink-jet printed to wait plain mode, you can to allot on first conductive layer 120.If in addition, this first is led
Electric area 121 or second conduction region 122 are used as connection power supply or ground connection, then may be designed to large area
Metal level.As shown in Figures 2 and 3, first circuit element 131 has two connection ends：Connect this
The connection end 131a of one conduction region 121, and connect the connection end 131b of second conduction region 122；This second
Circuit element 134 also has two connection ends：The connection end 134a of first conduction region 121 is connected, and even
Meet the connection end 134b of the 3rd conduction region 123.Described these connection ends 131a, 131b, 134a, 134b
Composition material be metal, for example, copper (Cu), tin (Sn), aluminium (Al), tin copper (SnCu) alloy, tin-lead (SnPb)
Alloy or SAC (SnAgCu) alloy, if described these connection ends 131a, 131b, 134a, 134b
Large scale is designed as, then may be such that these described circuit elements 131,134 are adhered to this with large access area
On first conductive layer 120, help to reduce resistance therebetween.
In addition, compared to the prior art by taking the figure D of 1A~1 as an example, circuit element 14a has to pass through
The conductive metal layer 18 and two via holes 17 so long path just can connect to the package substrate
Upper strata metallic circuit 12；Review the present embodiment, first circuit element, 131 need affix directly to this first
Conductive layer 120, just can connect to the lower metal circuit of the package substrate 100.In this way, contributing to reduction should
The path of the externally connected circuit of first circuit element 131 and thus caused resistance, and without element contraposition
(alignment) the problem of on.
In addition, first conductive pole 132 to connect the first conduction region 121 of first conductive layer 120 with
First metal routing 141 of second conductive layer 140, second conductive pole 135 is to connect first conduction
Second metal routing 142 of the second conduction region 122 and second conductive layer 140 of layer 120, described these
Conductive pole 132,135 can be any appropriate shape (for example, circular or rectangular cylindrical thing), can also design
Into with big sectional area, and its may be disposed at first conductive layer 120 these described conduction regions 121,
122nd, any position on 123, if for example, first conductive pole 132 is more close to first circuit element
131, then the path of the externally connected circuit of the first circuit element 131 is shorter, helps to reduce its external connection
The path on road and thus caused resistance.In addition, encapsulation unit layer 130 can further include one the 3rd and lead
Electric post 137, as shown in Fig. 2 it connects the 3rd conduction region 123.
Fig. 4 A~Fig. 4 E and Fig. 3 for the present embodiment package substrate 100 each fabrication steps S310~S390 institutes
Corresponding section of structure, and details are as follows.
First, as shown in Figure 4 A there is provided a bearing substrate 110, made thereon wire circuit 111 and
Metal guide pillar 112.The bearing substrate 110 can be metal substrate or the glass fibre core with metal level
Core (Core Substrate), to carry or support conducting wire thereon and electronic component；For example, such as the
First conductive layer 120, encapsulation unit layer 130 and second conductive layer 140 shown in 2 or 3 figures.
Above-mentioned metal includes iron (Fe), iron/nickel (Fe/Ni), copper (Cu), aluminium (Al) and combinations thereof or alloy, but this hair
It is bright to be not limited.Described these wire circuits 111 and these described metal guide pillars 112 will be then to will
First conductive layer 120 as shown in Figure 2 or Figure 3 is all connected to external circuit.
Then, as shown in Figure 4 B, one first conductive layer 120 is formed on the bearing substrate 100, and pattern
Be melted into the package substrate 100 lower circuit set in advance metal routing or conduction region, for example, first
Conduction region 121, the second conduction region 122.First conductive layer 120 can rely on the plating (Electrolytic of metal
Plating) or evaporation (Evaporation) technology makes, for example, copper, aluminium or nickel, and its electric conduction routing
Patterning can etch (Photolithography) technology to make by light lithography.
Then, as shown in Figure 4 C, using screen printing or the means such as ink-jet printed, in first conductive layer
The connection gasket (Pad) 150 of conductive material is formed on 120, and by the first circuit element 131 and second circuit element
134 are placed on the connection gasket 150, the connection end 131a of described these circuit elements 131,134,131b,
134a corresponds to these described connection gaskets 150 respectively and affixes to first conductive layer 120.In this way, this
One circuit element 131 and the second circuit element 134 directly can just can connect under the package substrate 100
Layer metallic circuit, for example, the wire circuit 111.
Then, as shown in Figure 4 D, the first conductive pole 132 and the second conductive pole 135 are formed in first conduction
On layer 120, to connect first conductive layer 120 and second conductive layer 140.These described conductive poles
132nd, 135 can be by metal plating or evaporation coating technique make, and these described conductive poles 132,
135 patterning can make by light lithography etching technique.
Then, as shown in Figure 4 E, adhesive material 133 is formed on first conductive layer 120 so that should
Adhesive material 133 is filled in these circuit elements 131,134 described in encapsulation unit layer 130 and described
These conductive poles 132,135 outside remainder, by these described circuit elements 131,134
And encapsulate and be fixed in encapsulation unit layer 130.This can by the adhesive material 133 top mold,
Compression mold, conversion mold inject the technologies such as mold to make；Wherein, the adhesive material 133 can be with
It is phenolic group resin (Novolac-Based Resin), epoxy (Epoxy-Based Resin) or silicon substrate
The insulating materials such as resin (Silicone-Based Resin) are constituted, but are not limited.Ground in addition, can rely on
(Polishing), grinding (Grinding), sandblasting, plasma-based or chemical etching mode are ground, the envelope is removed from top to bottom
The first half of glue material 133, until the upper surface of these described conductive poles 132,135 is exposed, to be formed
Encapsulation unit layer 130；Namely encapsulation unit layer 130 is located on first conductive layer 120, and wraps
Containing these described circuit elements 131,134 and these described conductive poles 132,135.
Then, as shown in figure 3, forming one second conductive layer 140 on encapsulation unit layer 130, and scheme
Case be melted into the package substrate 100 upper strata circuit set in advance metal routing or conduction region, for example,
One metal routing 141, the second metal routing 142.Second conductive layer 140 also can by metal plating or
Evaporation coating technique makes, for example, copper, aluminium or nickel, and the patterning of its electric conduction routing can rely on light lithography
Etching technique makes.The protective layer 145 of one isolation material can be formed in second conductive layer 140 described
These metal routings 141,142 outside remainder, to protect the package substrate 100 to be protected from
Possibility injury from external environment condition or successive process (for example, welding).So far, the bearing substrate 110 is complete
Into the interim task on its processing procedure, therefore it can remove it.
Fig. 5 is the section of structure of the package substrate 200 according to second embodiment of the invention.The package substrate
200 include：One first conductive layer 120, encapsulation unit layer 130 and one second conductive layer 140, its
Similar to the package substrate 100 of above-mentioned first embodiment, and it will not be repeated here at identical.Such as Fig. 5 institutes
Show, encapsulation unit layer 130 further includes one first connection unit 138, and first circuit element 131
Connection end 131b second metal routing 142 is connected by first connection unit 138.In this way, should
First circuit element 131 can also be connected through holding 131b and connecting the upper strata circuit (example of the package substrate 200
Such as, second conductive layer 140).
In another embodiment, the encapsulation unit layer 130 can further include one second connection unit 139 and
One the 3rd connection unit 239, and second conductive layer 140 further includes one the 3rd metal routing 143,
As shown in figure 5, the connection end 131b of first circuit element 131 can be by first connection unit 138
Second metal routing 142 is connected, its another connection end 131a can be connected by second connection unit 139
The 3rd metal routing 143 is connect, and the connection end 134a of the second circuit element 134 can then pass through the 3rd
Connection unit 239 and connect first metal routing 141.In this way, these described circuit elements 131,134
Also can be connected through hold 131a, 131b, 134a and connect the package substrate 200 upper strata circuit (for example,
Second conductive layer 140).
It is described above to be merely exemplary for the purpose of the present invention, and nonrestrictive, ordinary skill people
Member understand, in the case where not departing from the spirit and scope that claim is limited, can many modifications may be made,
Change is equivalent, but falls within protection scope of the present invention.
Claims (8)
1. a kind of package substrate, it is characterised in that it includes：
One first conductive layer, includes one first conduction region and one second conduction region；
One encapsulation unit layer, is arranged on first conductive layer, and include one first circuit element, one first
Conductive pole and an adhesive material, first circuit element have first connection end for connecting first conduction region
And second connection end for connecting second conduction region, and first conductive pole connects first conduction region；With
And
One second conductive layer, is arranged on encapsulation unit layer, and connect the of first conductive pole comprising one
One metal routing.
2. package substrate according to claim 1, it is characterised in that first circuit element is integrated electricity
Road chip or monolithic ceramic capacitor.
3. package substrate according to claim 1, it is characterised in that the adhesive material is filled in the encapsulation
Remainder outside interior first circuit element of elementary layer and first conductive pole.
4. package substrate according to claim 1, it is characterised in that encapsulation unit layer is further included
One second conductive pole, second conductive layer further includes one second metal routing, and second conductive pole connects
Connect second conduction region and second metal routing.
5. package substrate according to claim 1, it is characterised in that encapsulation unit layer is further included
One second circuit element, it has the 3rd connection end for connecting first conduction region.
6. package substrate according to claim 1, it is characterised in that encapsulation unit layer is further included
One second circuit element, one second conductive pole and one the 3rd conductive pole, first conductive layer further include one
3rd conduction region, the second circuit element has the 3rd connection end for connecting first conduction region and a connection
4th connection end of the 3rd conduction region, second conductive pole connects second conduction region, and the 3rd conduction
Post connects the 3rd conduction region.
7. package substrate according to claim 1, it is characterised in that encapsulation unit layer is further included
One connection unit, second conductive layer further includes one second metal routing, and first circuit element
Second connection end connects second metal routing by the connection unit.
8. package substrate according to claim 5, it is characterised in that encapsulation unit layer is further included
One first connection unit, one second connection unit and one the 3rd connection unit, second conductive layer are further
Comprising one second metal routing and one the 3rd metal routing, the second connection end of first circuit element passes through this
First connection unit connects second metal routing, the first connection end of first circuit element by this second
Connection unit connects the 3rd metal routing, and the 3rd connection end of the second circuit element connects by the 3rd
Order member connects first metal routing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610027874.5A CN106981472A (en) | 2016-01-15 | 2016-01-15 | Package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610027874.5A CN106981472A (en) | 2016-01-15 | 2016-01-15 | Package substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106981472A true CN106981472A (en) | 2017-07-25 |
Family
ID=59340017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610027874.5A Pending CN106981472A (en) | 2016-01-15 | 2016-01-15 | Package substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106981472A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040231885A1 (en) * | 2003-03-07 | 2004-11-25 | Borland William J. | Printed wiring boards having capacitors and methods of making thereof |
| US20080273311A1 (en) * | 2007-02-06 | 2008-11-06 | Nicholas Biunno | Enhanced Localized Distributive Capacitance for Circuit Boards |
| CN102324418A (en) * | 2011-08-09 | 2012-01-18 | 日月光半导体制造股份有限公司 | Semiconductor component packaging structure and its manufacturing approach |
| CN104037166A (en) * | 2013-03-07 | 2014-09-10 | 日月光半导体制造股份有限公司 | Semiconductor package including antenna layer and manufacturing method thereof |
-
2016
- 2016-01-15 CN CN201610027874.5A patent/CN106981472A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040231885A1 (en) * | 2003-03-07 | 2004-11-25 | Borland William J. | Printed wiring boards having capacitors and methods of making thereof |
| US20080273311A1 (en) * | 2007-02-06 | 2008-11-06 | Nicholas Biunno | Enhanced Localized Distributive Capacitance for Circuit Boards |
| CN102324418A (en) * | 2011-08-09 | 2012-01-18 | 日月光半导体制造股份有限公司 | Semiconductor component packaging structure and its manufacturing approach |
| CN104037166A (en) * | 2013-03-07 | 2014-09-10 | 日月光半导体制造股份有限公司 | Semiconductor package including antenna layer and manufacturing method thereof |
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Effective date of registration: 20180322 Address after: The Cayman Islands KY1-1205 Grand Cayman West Bay Road No. 802 Furong Road Hongge mailbox No. 31119 Applicant after: Phoenix pioneer Limited by Share Ltd Address before: Hsinchu County, Taiwan, China Applicant before: Persistent strength or power Science and Technology Co., Ltd. |
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Effective date of registration: 20200710 Address after: Hsinchu County, Taiwan, China Applicant after: PHOENIX PIONEER TECHNOLOGY Co.,Ltd. Address before: The Cayman Islands KY1-1205 Grand Cayman West Bay Road No. 802 Furong Road Hongge mailbox No. 31119 Applicant before: PHOENIX & Corp. |
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Application publication date: 20170725 |