CN106971754A

CN106971754A - Non-volatile memory devices including its storage device and the method for operating it

Info

Publication number: CN106971754A
Application number: CN201610951508.9A
Authority: CN
Inventors: 沈烔敎; 朴商秀
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2015-11-02
Filing date: 2016-11-02
Publication date: 2017-07-21
Anticipated expiration: 2036-11-02
Also published as: KR102377469B1; US9812214B2; KR20170051841A; CN106971754B; US20170125116A1

Abstract

A kind of non-volatile memory devices can include memory cell array, address decoder circuit, page buffer circuit and control logic circuit.Erasing operation includes being iteratively performed erasing circulation, and erasing circulation includes：Part is wiped, erasing voltage is applied to the memory cell of selected memory block wherein；And erasing verification portion, verify the memory cell of selected memory block using erasing verifying voltage wherein.If the memory cell of the memory block selected in erasing verification portion is confirmed as erasing and passed through, control logic circuit can monitor the memory cell of selected memory block.If the result monitored indicates that the memory cell of selected memory block is in abnormality, control logic circuit applies extra erasing voltage to the memory cell of selected memory block.

Description

Non-volatile memory devices including its storage device and the method for operating it

Cross-reference to related applications

This application claims Korea Spro 10-2015-0153267 submitted on November 2nd, 2015 to Korean Intellectual Property Office The priority of state's patent application, the disclosure of the korean patent application is incorporated into this by reference of text.

Technical field

Embodiment of the disclosure is related to a kind of semiconductor equipment, and more particularly, to a kind of nonvolatile memory The storage device of equipment including the non-volatile memory devices and the method for operating the non-volatile memory devices.

Background technology

Storage device refers to depositing under such as control of computer, smart phone or the host device of Intelligent flat equipment The equipment for storing up data.Storage device includes：The equipment of data storage on disk, such as hard drive (HDD)；Or for example The equipment of data storage on the semiconductor memory of nonvolatile memory, such as solid-state drive (SSD) or storage card.

Nonvolatile memory can include, for example, read-only storage (ROM), programming ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory device, phase transformation RAM (PRAM), magnetic RAM (MRAM), resistance-type RAM (RRAM) or ferroelectricity RAM (FRAM).

With the development of semiconductor fabrication, the degree of integration and capacity of non-volatile memory devices and storage device Continue to increase.As non-volatile memory devices are highly integrated with storage device, the reduction of its manufacturing cost.However, non-easy The high integration of the property lost memory devices and storage device causes its size to be reduced and structural change, and therefore, recently There are various problems.So the problem of, causes the damage of the data stored in the storage device, so as to reduce storage device Reliability.The method and apparatus for being required to improve the reliability of non-volatile memory devices and storage device.

The content of the invention

Embodiment of the disclosure provides depositing for a kind of non-volatile memory devices including non-volatile memory devices Storage device and the method for operating non-volatile memory devices.

The one side of embodiment of the disclosure aims to provide a kind of non-volatile memory devices.The non-volatile memories Device equipment can include：Each include multiple memory cell in multiple memory blocks, the plurality of memory block；Address decoder Circuit, memory cell is connected to by wordline；Page buffer circuit, memory cell array is connected to by bit line；And control Logic circuit processed, is configured as erasing operation of the control from the memory cell in the memory block selected in memory block.Wipe Division operation can include being iteratively performed erasing circulation, and erasing circulation includes：Part is wiped, erasing voltage is applied in wherein To the memory cell of selected memory block；And erasing verification portion, wherein using erasing verifying voltage to verify The memory cell of the memory block of selection.If the memory cell of the memory block selected in erasing verification portion is determined Pass through for erasing, then control logic circuit can be configured as monitoring the memory cell of selected memory block.If supervised Depending on result indicate that the memory cell of selected memory block is in abnormality, then control logic circuit can be configured as Apply extra erasing voltage to the memory cell of selected memory block.

The other side of embodiment of the disclosure aims to provide a kind of storage device.The storage device can include：It is non- Volatile memory devices, comprising multiple memory blocks, each include multiple memory cell in the plurality of memory block；And Controller, is configured as transmitting the selected memory for non-volatile memory devices to non-volatile memory devices The erasing order of block.Non-volatile memory devices, which can be configured to respond to erasing order, to be come to selected memory block Memory cell perform erasing order.Erasing operation can include being iteratively performed erasing circulation, and erasing circulation includes：Erasing Part, wherein erasing voltage be applied to the memory cell of selected memory block；And erasing verification portion, wherein The memory cell of selected memory block is verified using erasing verifying voltage.If selected in erasing verification portion The memory cell of memory block is confirmed as erasing and passed through, then non-volatile memory devices can be configured as selected by monitoring Memory block memory cell.If the result monitored indicates that the memory cell of selected memory block is in abnormal shape State, then non-volatile memory devices can be configured as applying extra erasing to the memory cell of selected memory block Voltage.

The another aspect of embodiment of the disclosure aims to provide a kind of side for being used to operate non-volatile memory devices Method, the non-volatile memory devices include each including multiple storage lists in multiple memory blocks, the plurality of memory block Member.This method can include：By the memory cell of from the first memory block to multiple memory blocks apply erasing voltage come Perform erasing operation；After erasing operation is performed, held using the first reading voltage come the memory cell to first memory block The read operation of row first；Result based on the first read operation counts come the quantity to opening unit and closing unit；Make Read voltage to perform the second read operation to the memory cell of first memory block with read voltage less than first second；With And the result based on the second read operation is performed by applying extra erasing voltage to the memory cell of first memory block Extra erasing operation.

Brief description of the drawings

Refer to the attached drawing, according to following description, the above and other objects and features will be apparent, wherein, unless Additionally indicate, otherwise through each accompanying drawing, identical reference refers to identical part, and in the accompanying drawings：

Fig. 1 is the block diagram for illustrating the non-volatile memory devices according to example embodiment；

Fig. 2 is the circuit diagram for illustrating the memory block according to example embodiment；

Fig. 3 is to illustrate the threshold for changing memory cell wherein when the memory cell to memory block is programmed and is wiped The curve map of the example of threshold voltage；

Fig. 4 is to illustrate the difference in the state of performing erasing operation, between the threshold voltage distribution of memory block The curve map of example；

Fig. 5 is to illustrate the memory cell and the storage list of second memory block when on the first memory block in Fig. 4 The figure of threshold voltage during member implementation programming operation；

Fig. 6 is the flow chart for the operating method for illustrating the non-volatile memory devices according to example embodiment；

Fig. 7 is to illustrate the flow chart for being used to monitor the method for the memory cell being wiped free of according to example embodiment；

Fig. 8 is to illustrate being counted wherein based on monitoring reading result to closing unit according to example embodiment The figure of example；

Fig. 9 is to illustrate being counted wherein based on monitoring reading result to opening unit according to example embodiment The figure of example；

Figure 10 is to illustrate to perform erasing operation, monitoring read operation and extra wherein according to example embodiment The timing diagram of the process of the application of erasing voltage；

Figure 11 is the flow chart for the operating method for illustrating the application drawing 6 according to example embodiment；

Figure 12 is to illustrate to perform erasing operation, monitoring read operation and extra wherein according to Figure 11 application The timing diagram of the process of the application of erasing voltage；

Figure 13 is to illustrate the side that abnormal information is managed according to the non-volatile memory devices wherein of example embodiment The flow chart of method；

Figure 14 is the side for illustrating the suppressing exception information of non-volatile memory devices wherein according to example embodiment The flow chart of method；

Figure 15 is to illustrate the side that abnormal information is managed according to the non-volatile memory devices wherein of example embodiment The flow chart of method；

Figure 16 is the block diagram for illustrating the storage device according to example embodiment；

Figure 17 is the flow chart for the operating method for illustrating the storage device according to example embodiment；

Figure 18 is to illustrate to be based on environmental condition control monitoring reading behaviour according to the storage device wherein of example embodiment The flow chart of the method for work；

Figure 19 is the block diagram for illustrating the controller according to specific embodiment；And

Figure 20 is the block diagram for illustrating the computing device 1000 according to specific embodiment.

Embodiment

Fig. 1 is the block diagram for illustrating the nonvolatile memory 110 according to example embodiment.It is non-volatile to deposit with reference to Fig. 1 Reservoir 110 can include memory cell array 111, row decoder circuits 113, page buffer circuit 115, data input/defeated Go out circuit 117 and control logic circuit 119.

Memory cell array 111 can include multiple memory block BLK1 to BLKz.Each memory block can include many Individual memory cell.Each memory block can be connected to row decoder circuits 113 by least one string selection line SSL, multiple Wordline WL and at least one string selection line SSL.Memory block BLK1 can each be connected by multiple bit line BL into BLKz It is connected to page buffer circuit 115.Memory block BLK1 to BLKz can be commonly connected to multiple bit line BL.Memory block Memory cell of the BLK1 into BLKz can have identical structure.

In embodiment, memory block BLK1 into BLKz can be each erasing operation unit.Memory cell battle array Memory cell in row 111 can be wiped by memory block.The memory cell for belonging to a memory block can be while be wiped free of. In another embodiment, each memory block can be divided into multiple sub-blocks.It can be carried out by the sub-block in multiple sub-blocks Erasing.

In embodiment, the physics that each can include by block address distinguish of the multi-memory block BLK1 into BLKz Memory space.In wordline WL each can be corresponding with the amount of physical memory distinguished by row address.In bit line BL Each can be corresponding with the amount of physical memory distinguished by column address.

Line decoder 113 can be connected by multiple ground connection selection line GSL, multiple wordline WL and multiple string selection line SSL It is connected to memory cell array 111.Line decoder 113 can be operated according to the control of control logic circuit 119.Row decoding Device 113 can be to entering row decoding by input/output channel from the address received by controller, and can be based on decoding Address will be applied to string selection line SSL, wordline WL and the voltage for being grounded selection line GSL to switch.

For example, during programming operation, column decoder circuitry 113 can in by the selected memory block in address quilt The wordline of selection applies program voltage, and non-selected wordline is applied through (pass) electricity into selected memory block Pressure.During read operation, row decoder circuits 113 selected wordline can apply selection into selected memory block Voltage is read, and applies non-selected reading voltage to non-selected wordline.During erasing operation, row decoder circuits 113 can apply erasing voltage (for example, ground voltage, its level and ground voltage to the wordline in selected memory block The similar positive voltage or negative voltage of level).

Page buffer circuit 115 can be connected to memory cell array 111 by bit line BL.Page buffer circuit 115 can be connected to data input/output circuit 117 by multiple data wire DL.Page buffer circuit 115 can be in control Operated under the control of logic circuit 119.

During programming operation, page buffer circuit 115 can store the data that will be programmed into memory cell. Page buffer 115 can based on the data stored to bit line BL apply voltage.For example, page buffer 115 can be served as Write driver.During read operation, page buffer circuit 115 with the voltage on sense bit line BL and be able to can be stored The result sensed.For example, page buffer circuit 115 can serve as sensing amplifier.

Data input/output circuit 117 can be connected to page buffer 115 by data wire DL.Data input/output The data read by page buffer circuit 115 by input/output channel can be output to controller by circuit, and Can by by input/output channel from the data transfer received by controller to page buffer circuit 115.

Pass through/unsuccessfully check that circuit PFC can receive the result of verification operation from page buffer circuit 115.Pass through/lose Lose and check that circuit PFC can determine to pass through or failure based on the result of checking read operation.For example, reading behaviour in programming checking During work, passing through/unsuccessfully check circuit PFC can be to opening unit (on-cell) quantity (that is, the number for the unit being unlocked Amount) counted.When the quantity of opening unit is less than or equal to threshold value (or reference value), pass through/unsuccessfully check that circuit PFC can To determine that programming passes through.Hereinafter, the threshold value of each event can be same to each other or different to each other.When the quantity of opening unit is more than During first threshold, PFC can determine program fail.For example, when performing erasing checking read operation, pass through/unsuccessfully check electricity Road PFC can be counted to closing unit (off-cell) quantity (that is, the quantity of pent unit).Work as closing unit Quantity be less than or equal to Second Threshold when, pass through/unsuccessfully check circuit PFC can determine that erasing passes through.When closing unit Quantity be more than Second Threshold when, pass through/unsuccessfully check circuit PFC can determine erasing failure.Pass through/unsuccessfully check circuit PFC It can pass through or failure information to the output of control logic circuit 119.In embodiment, closing unit can be corresponding with logical zero, And opening unit can be corresponding with logic 1.In another embodiment, closing unit can be corresponding with logic 1, and Opening unit can be corresponding with logical zero.

Control logic circuit 119 can be received from controller by input/output channel and ordered, and can pass through control Channel receives from it control signal.Control logic circuit 119 can be received by input/output channel in response to control signal and ordered Order, can transport through the address received by input/output channel to row decoder circuits 113, and can be to input/defeated Go out circuit 117 and transport through data received by input/output channel.Control logic circuit 119 can be to received Order into row decoding, and non-volatile memory devices 110 can be controlled based on the order after decoding.

Control logic circuit 119 can based on from by/unsuccessfully check circuit PFC by or failure information control Programming operation or erasing operation.

Control logic circuit 119 can include erasure controller EC.Erasure controller EC can be configured as control and pass through From the erasing operation of the memory cell of the selected memory block in address (or sub-block) received by controller.In addition, erasing Controller EC can be configured as controlling to follow monitoring read operation after an erase operation and based on monitoring read operation As a result the operation of extra erasing voltage is applied.Hereinafter, for convenience of description, it can be assumed that erasure controller EC presses memory Block controls erasing operation.However, spirit and scope of the present disclosure can be with not limited to this.For example, erasure controller EC can be by Sub-block controls erasing operation.The operation controlled by erasure controller EC is described below with reference to accompanying drawing.

Fig. 2 is the circuit diagram for illustrating the memory block BLKa according to example embodiment.With reference to Fig. 2, memory block BLKa Multiple unit string CS11 to CS21 and CS12 to CS22 can be included.Multiple units can be arranged along line direction and column direction String CS11 to CS21 and CS12 to CS22, to constitute row and column.

For example, the unit string CS11 and CS12 that are arranged along line direction may be constructed the first row, and along line direction institute Unit the string CS21 and CS22 of arrangement may be constructed the second row.Unit the string CS11 and CS21 arranged along column direction can be with structure Into first row, and the unit string CS12 and CS22 that are arranged along column direction may be constructed secondary series.

Each unit string can include multiple cell transistors.Cell transistor can include ground connection selection transistor GST, Memory cell MC1 to MC6 and string select transistor SSTa and SSTb.Ground connection selection transistor GST in each unit string, deposit Storage unit MC1 to MC6 and string select transistor SSTa and SSTb can be stacked on and with lower plane (for example, memory block Plane in BLKa substrate) in vertical short transverse：On this plane, arrangement units string CS11 is carried out extremely along row and column CS21 and CS12 to CS22.

Each cell transistor can be charge-trapping (charge trap) type units transistor, its threshold voltage root Change according to the amount of the electric charge captured in its insulating barrier.

Nethermost ground connection selection transistor GST can be commonly connected to common source polar curve CSL.

The ground connection selection transistor GST of unit string CS11 and CS12 in the first row control gate can publicly connect It is connected to and is grounded selection line GSL1, and the control gate for being grounded selection transistor GST of unit string CS11 and CS22 in a second row Ground connection selection line GSL2 can be extremely commonly connected to.That is, the unit string in not going together may be coupled to different ground connection selections Line.

It is placed on the control of the memory cell at identical height (or order) place from substrate (or ground connection selection transistor GST) Grid processed is commonly connected to a wordline.The control gate for being placed on the memory cell at different height (or order) place is connected to Different wordline W1 to W6.For example, memory cell MC1 can be commonly connected to wordline WL1.Memory cell MC2 can be with public Ground is connected to wordline WL2.Memory cell MC3 can be commonly connected to wordline WL3.Memory cell MC4 can be connected publicly To wordline WL4.Memory cell MC5 can be commonly connected to wordline WL5.Memory cell MC6 can be commonly connected to wordline WL6。

Unit string in not going together may be coupled to different string selection lines.It is with identical height (or order) and belong to Identical string selection line is may be coupled in the string select transistor of the unit string of same a line.With different height (or order) And belong to the string select transistor of the unit string of same a line and may be coupled to different string selection lines.

In embodiment, the string select transistor with the unit string in a line can be commonly connected to string selection line.Example Such as, the string select transistor SSTa and SSTb of unit the string CS11 and CS12 in the first row can be commonly connected to a string of selections Line.The string select transistor SSTa and SSTb of unit string CS21 and CS22 in second row can be commonly connected to a string of selections Line.

Unit string CS11 to CS21 and CS12 to CS22 row can be connected respectively to different bit line BL1 and BL2. For example, the string select transistor SSTb of unit the string CS11 and CS21 in first row can be commonly connected to bit line BL1.Second The string select transistor SSTb of unit string CS12 and CS22 in row can be commonly connected to bit line BL2.

Unit string CS11 and CS12 may be constructed the first plane.Unit string CS21 and CS22 may be constructed the second plane.

As described above, memory block BLKa can be provided with 3 D memory array.3D memory arrays are integrally formed In one or more physical levels of memory cell MC array, memory cell MC, which has, is disposed in having on silicon base Source region and the circuit associated with these memory cell MC operation.The circuit associated with memory cell MC operation can be with On or within such substrate.Term " overall " means that the layer (layer) of each grade of array is directly deposited On the layer of each bottom level (underlying level) of 3D memory arrays.

In the embodiment of present inventive concept, 3D memory arrays include vertical nand string (or unit string), and it is vertical Ground, which is oriented, causes at least one memory cell to be located on another memory cell.At least one memory cell MC can include electricity Lotus trapping layer.Each vertical nand string can also include being placed at least one selection transistor on memory cell MC. At least one selection transistor can have with memory cell MC identicals structure and is identically formed with memory cell MC.

The suitable configuration that the patent document below this describes 3 D memory array is incorporated by reference into, at this In configuration, 3 D memory array is configured as multiple levels, wherein shared word line and/or bit line between the stages：U.S. Patent No. No. 7,679,133；No. 8,553,466；No. 8,654,587；No. 8,559,235；And U.S. Patent Publication the 2011/th No. 0233648.

Fig. 3 is to illustrate wherein to change memory cell when the memory cell to memory block BLKa is programmed and is wiped The curve map of the example of MC threshold voltage.In figure 3, abscissa represents memory cell MC threshold voltage, and ordinate table Show memory cell MC quantity.That is, the curve map G1 and G2 of Fig. 3 shows the threshold voltage distribution of memory cell.

Referring to figs. 1 to Fig. 3, the first curve map G1 can illustrate the threshold value electricity of memory cell when performing erasing operation ERS Pressure.Second curve map G2 can illustrate the threshold voltage of memory cell when performing programming operation PGM.

First, with reference to the first curve map G1, memory cell MC has erase status E.Each storage with erase status E Unit can be programmed by programming operation PGM.When programmed, memory cell MC can have the institute in the second curve map G2 The threshold voltage illustrated.

Programming operation PGM can include multiple program cycles.Each program cycles can include programmed fraction and programming is tested Demonstrate,prove part.In programmed fraction, it can perform following：By adjusting string selection line SSL1a, SSL1b, SSL2a and SSL2b Voltage selects to want programmed plane；Select to want programmed memory cell by adjusting bit line BL1 and BL2 voltage Row；And select to want by applying program voltage to selected wordline and being applied through voltage to non-selected wordline The height of programmed memory cell.

In programming verification portion, it can perform following：Programming checking is read and passes through/unsuccessfully check.Programming checking Reading can include reading programmed memory cell under the following conditions：Programmed memory cell and bit line BL1 and BL2 with And common source polar curve CSL electrical connections, and program the control gate that verifying voltage is separately applied to programmed memory cell Pole.Passing through/unsuccessfully checking to include：The result read based on programming checking, is tested it is determined that to be programmed with higher than programming Among the memory cell for the threshold voltage for demonstrate,proving voltage, each of which has the storage list of the threshold voltage less than programming verifying voltage Whether the quantity of member is less than or equal to threshold value.When the number of the memory cell of each threshold voltage for having and being less than programming verifying voltage When amount is less than or equal to threshold value, it may be determined that programming passes through.There is depositing for the threshold voltage less than programming verifying voltage when each When the quantity of storage unit is more than threshold value, it may be determined that program fail.Threshold value can be 0 or positive integer.

Can the dbjective state that be programmed into according to memory cell determine perform programming verification portion number of times.Example Such as, when every memory cell programs 3 bit data, programmed memory cell can have one in following eight states： Erase status E and first state P1 to the 7th state P7 as shown in Figure 3.During verification portion is programmed, it can use First programming verifying voltage VFY1 to the seventh programming verifying voltage VFY7 corresponding with first state P1 to the 7th state P7 comes Verify memory cell MC.For example, when every memory cell programs N-bit data, can use and first state to the 2nd^N- 1 shape The first corresponding programming verifying voltage of state is to the 2nd^N- 1 programs verifying voltage to verify memory cell.

Its dbjective state memory cell corresponding with erase status E, which can be programmed, forbids.

The dbjective state of each of which memory cell MC corresponding with the first programming state P1 can be programmed with height In the first programming verifying voltage VFY1 threshold voltage.For example, when the memory cell that be programmed to the first programming state P1 is worked as In, each of which have less than or equal to the first verifying voltage VFY1 memory cell quantity be less than or equal to first threshold When, the memory cell for being programmed to the first programming state P1 can be determined that programming passes through.

The dbjective state of each of which memory cell MC corresponding with the second programming state P2 can be programmed with height In the second programming verifying voltage VFY2 threshold voltage.For example, when the memory cell that be programmed to the second programming state P2 is worked as In, each of which have less than or equal to the second verifying voltage VFY2 memory cell quantity be less than or equal to Second Threshold When, the memory cell for being programmed to the second programming state P2 can be determined that programming passes through.

The dbjective state of each of which memory cell MC corresponding with the 3rd programming state P3 can be programmed with height In the 3rd programming verifying voltage VFY3 threshold voltage.For example, when the memory cell that be programmed to the 3rd programming state P3 is worked as In, each of which have less than or equal to the 3rd verifying voltage VFY3 memory cell quantity be less than or equal to the 3rd threshold value When, the memory cell for being programmed to the 3rd programming state P3 can be determined that programming passes through.

The dbjective state of each of which memory cell MC corresponding with the 4th programming state P4 can be programmed with height In the 4th programming verifying voltage VFY4 threshold voltage.For example, when the memory cell that be programmed to the 4th programming state P4 is worked as In, each of which have less than or equal to the 4th verifying voltage VFY4 memory cell quantity be less than or equal to the 4th threshold value When, the memory cell for being programmed to the 4th programming state P4 can be determined that programming passes through.

The dbjective state of each of which memory cell MC corresponding with the 5th programming state P5 can be programmed with height In the 5th programming verifying voltage VFY5 threshold voltage.For example, when the memory cell that be programmed to the 5th programming state P5 is worked as In, each of which have less than or equal to the 5th verifying voltage VFY5 memory cell quantity be less than or equal to the 5th threshold value When, the memory cell for being programmed to the 5th programming state P5 can be determined that programming passes through.

The dbjective state of each of which memory cell MC corresponding with the 6th programming state P6 can be programmed with height In the 6th programming verifying voltage VFY6 threshold voltage.For example, when the memory cell that be programmed to the 6th programming state P6 is worked as In, each of which have less than or equal to the 6th verifying voltage VFY6 memory cell quantity be less than or equal to the 6th threshold value When, the memory cell for being programmed to the 6th programming state P6 can be determined that programming passes through.

The dbjective state of each of which memory cell MC corresponding with the 7th programming state P7 can be programmed with height In the 7th programming verifying voltage VFY7 threshold voltage.For example, when the memory cell that be programmed to the 7th programming state P7 is worked as In, each of which have less than or equal to the 7th verifying voltage VFY7 memory cell quantity be less than or equal to the 7th threshold value When, the memory cell for being programmed to the 7th programming state P7 can be determined that programming passes through.

First threshold into the 7th threshold value can be each 0 or positive integer.

When the memory cell programming that target points to the first programming state P1 to the 7th programming state P7 passes through, it can terminate Programming operation.At least one memory cell of the first programming state P1 into the 7th programming state P7, which is pointed to, when target programs mistake When losing, next program cycles can be carried out.In next program cycles, the level of program voltage can be improved.

When erased, memory cell MC can have the threshold voltage gone out illustrated in the first curve map G1.Erasing ERS is operated to include multiple erasing circulations.Each erasing circulation can include erasing part and erasing verification portion.In erasing In part, it can perform following：Apply the electricity of ground voltage or its level and ground voltage to memory cell MC control gate Flat similar positive or negative low-voltage, and apply erasing voltage to memory cell MC raceway groove.

In erasing verification portion, it can perform following：Erasing checking is read and passes through/unsuccessfully check.Erasing checking Reading can include reading the memory cell being wiped free of under the following conditions：The memory cell that is wiped free of and bit line BL1 and BL2 with And common source polar curve CSL electrical connections, and wipe the control that verifying voltage VFYE is separately applied to the memory cell being wiped free of Grid processed.The result based on erasing checking read operation can be included by passing through/unsuccessfully checking, each with higher than erasing to determine Whether the quantity of verifying voltage VFYE memory cell is less than or equal to threshold value.Have when each higher than erasing verifying voltage VFYE Threshold voltage memory cell quantity be less than or equal to threshold value when, it may be determined that erasing pass through.Have when each higher than wiping When being more than value except the quantity of the memory cell of verifying voltage VFYE threshold voltage, it may be determined that erasing failure.Threshold value can be 0 Or positive integer.

In Fig. 3 the second curve map G2, embodiment of the disclosure is illustrated as erase status E and the first programming state Each threshold voltage distribution ranges of the P1 into the 7th programming state P7 is overlapping with the threshold voltage distribution range of adjacent states. Threshold voltage distribution range may be overlapping due to the characteristic variations of memory cell, and can pass through the mistake in the range of recoverable Error detection and correcting scheme are controlled (or compensation/correction).

As with reference to described by Fig. 1 and Fig. 2, erasing operation can be performed in units of memory block.It was observed that, with There are characteristic variations between the memory block of three-dimensional structure as illustrated in Figure 2.Characteristic variations between memory block can be led Cause to perform the difference between the threshold voltage distribution of the memory block of erasing operation.

Fig. 4 is the song for the example for illustrating the difference between the distribution of the threshold voltage of memory block of erasing operation is performed Line chart.In Fig. 4, abscissa represents memory cell MC threshold voltage, and ordinate represents memory cell MC quantity.

With reference to Fig. 1, Fig. 2 and Fig. 4, solid line can indicate the threshold value electricity of the memory cell in first memory block BLK1 Pressure, and dotted line can indicate the threshold voltage of the memory cell in second memory block BLK2.

During erasing operation, erasing verifying voltage VFYE can be used to verify first memory block BLK1 storage list The memory cell of member and second memory block BLK2.Although however, wiping verifying voltage VFYE to wipe first using identical Memory block BLK1 and second memory block BLK2 memory cell, but the threshold of the memory cell in first memory block BLK1 The distribution grade (level) of threshold voltage may be with the threshold voltage of the memory cell in second memory block BLK2 distribution grade It is different.

For example, the width that the threshold voltage of the memory cell in first memory block BLK1 is distributed can be wider than the second storage The width of the threshold voltage distribution of memory cell in device block BLK2.In embodiment, the storage in first memory block BLK1 Unit can be the quick cell being quickly wiped free of than the memory cell in second memory block BLK2.

Fig. 5 is to illustrate the memory cell and second memory block BLK2 when on the first memory block BLK1 in Fig. 4 Memory cell implement programming operation when threshold voltage figure.In Figure 5, abscissa represents memory cell MC threshold value electricity Pressure, and ordinate represents memory cell MC quantity.

In Figure 5, it is illustrated that among first memory block BLK1 or second memory BLK2 memory cell, will quilt It is programmed for the threshold voltage distribution of the first programming state P1 memory cell.

Erase status E memory cell threshold voltage distribution with the memory cell in first memory block BLK1 In the case of the shape of threshold voltage distribution, erase status E memory cell and the first programming state P1 memory cell can be with It is distributed in together in overlapping region, for example, first area A1.For example, after programming operation is performed, erase status E and first Programming state P1 memory cell can have the mistake corresponding with first area A1.

Erase status E memory cell threshold voltage distribution with the memory cell in second memory block BLK2 In the case of the shape of threshold voltage distribution, erase status E memory cell and the first programming state P1 memory cell can be with It is distributed in together in first area A1 and second area A2.For example, after programming operation is performed, erase status E and first is compiled Journey state P1 memory cell can have the mistake corresponding with first area A1 and second area A2.

As described above, the threshold voltage distribution in erase status E memory cell is formed second memory block BLK2 In memory cell threshold voltage distribution in the case of, perform programming operation after, the quantity of mistake is significantly increased.For Above mentioned problem is prevented, error controller EC in accordance with an embodiment of the present disclosure can perform monitoring after erasing operation is performed Read operation.Monitoring read operation may be performed that whether the memory cell that monitoring is wiped free of has such as second memory block The shape of the threshold voltage distribution of the shape of the threshold voltage distribution of memory cell in BLK2.Erasure controller EC can be based on The result of read operation is monitored to determine whether to apply extra erasing voltage.

Fig. 6 is the flow chart for the operating method for illustrating the non-volatile memory devices 110 according to example embodiment.Ginseng Fig. 1, Fig. 2 and Fig. 6 are examined, in step s 110, non-volatile memory devices 110 can be to selected memory block (example Such as, BLKa) memory cell apply erasing voltage.For example, erasing voltage can be applied under the control of control logic circuit 119 In the main body (body) for the memory cell being added in selected memory block.The erasing portion that step S110 can be circulated with erasing Split-phase correspondence.

In the step s 120, erasing verifying voltage VFYE can be used to perform checking reading for the memory cell being wiped free of Take.The result that checking is read can be passed to pass through/unsuccessfully check circuit PFC.

In step s 130, pass through/unsuccessfully check that the quantity that circuit PFC can be for example to closing unit is counted. In step S140, pass through/unsuccessfully check whether circuit PFC can indicate that erasing passes through with determines counting result.For example, if turned off The quantity of unit is less than or equal to threshold value, then pass through/unsuccessfully check that circuit PFC can determine that erasing passes through.If turned off unit Quantity be more than threshold value, then pass through/unsuccessfully check circuit PFC can determine erasing failure.

If it is determined that erasing failure, then in step S150, control logic circuit 119 can improve erasing voltage.Afterwards, Process may proceed to step S110.If it is determined that erasing passes through, then process may proceed to step S160.

Step S110 to step S140 may be constructed erasing circulation EL.Step S110 can circulate EL erasing portion with erasing Split-phase correspondence, and can to wipe verification portion with it corresponding by step S120 to step S140.Step S120 can be with erasing The checking of verification portion is read corresponding, and step S130 to S140 can be with the passing through of erasing verification portion/unsuccessfully check phase Correspondence.

It is determined that erasing pass through after, in step S160, control logic circuit 119, which can be monitored, performs erasing to it The memory cell (hereinafter referred to as " memory cell being wiped free of ") of operation.For example, control logic circuit 119 can be monitored The threshold voltage distribution for the memory cell being wiped free of and second memory block BLK2 illustrated in Fig. 4 and Fig. 5 memory cell Threshold voltage distribution it is whether similar for shape.In the threshold voltage distribution for the memory cell being wiped free of and Fig. 4 and Fig. 5 In the case that the threshold voltage distribution of illustrated second memory block BLK2 memory cell is similar for shape, control is patrolled Abnormality can be determined to be in by the memory cell being wiped free of by collecting circuit 119.In the threshold value electricity for the memory cell being wiped free of Pressure distribution and the threshold voltage of first memory block BLK1 illustrated in Fig. 4 and Fig. 5 memory cell are distributed for shape In the case of similar, control logic circuit 119 can determine that the memory cell being wiped free of is in normal condition.

If the memory cell being wiped free of in step S170 is determined to be in normal condition, it can not perform extra Operation.If the memory cell being wiped free of is determined to be in abnormality, control logic circuit 119 can be to being wiped free of Memory cell apply extra erasing voltage.For example, under the control of control logic circuit 119, ground voltage or its electricity The control gate for the memory cell being wiped free of can be applied to by equalling the negative or positive low-voltage similar to the level of ground voltage Pole, and extra erasing voltage can be applied to the raceway groove for the memory cell being wiped free of.For example, extra erasing voltage Level can be identical, lower or higher with the level of the erasing voltage of last (or nearest) erasing circulation.In embodiment In, after extra erasing voltage is applied in, control logic circuit 119 can terminate all behaviour associated with erasing operation Make (or processing), without performing following operation (or processing), such as checking is read or passes through/unsuccessfully check.

Fig. 7 is to illustrate the flow chart for being used to monitor the method for the memory cell being wiped free of according to example embodiment.Ginseng Fig. 1, Fig. 2 and Fig. 7 are examined, in step S210, control logic circuit 119 can control line decoder 113 and page buffer Circuit 115, to perform monitoring read operation using monitoring voltage VFYM.For example, line decoder 113 can be to wordline WL1 At least one selected wordline into WL6 applies monitoring voltage VFYM.Page buffer 115 can be respectively to bit line BL1 and BL2 applies supply voltage.Among memory cell MC, each of which has the threshold voltage less than monitoring voltage VFYM Memory cell can be unlocked.Among memory cell MC, each of which has the threshold value electricity greater than or equal to monitoring voltage VFYM The memory cell of pressure can be closed.

When at least one in the memory cell for being connected to a bit line is closed, page buffer circuit 115 can be with The storage closing unit information associated with bit line.When all memory cell for being connected to a bit line are unlocked, the page delays The opening unit information associated with bit line can be stored by rushing device circuit 115.Page buffer circuit 115 can be to passing through/lose Lose and check that circuit PFC offers include closing unit information and result is read in the monitoring of opening unit information.

In step S220, passing through/fail circuit PFC can count to the quantity of closing unit (or opening unit) Number.

In embodiment, step S210 and step S220 can be repeated according to specific frequency.For example, can select to deposit First group of memory cell among memory cell in reservoir block BLKa, and can be in so selected first group Memory cell perform step S210 and step S220.Second among the memory cell in memory block BLKa can be selected Group memory cell, and step S210 and step can be performed for the memory cell in so selected second group S220.Pass through/unsuccessfully check that circuit PFC can accumulate closing while according to specific frequency repeat step S210 and S220 The quantity of unit (or opening unit).

In embodiment, each group can be including the storage in the memory cell in plane (or part of plane), row Unit, the memory cell with a height or the memory cell in physical page.

In step S230, pass through/unsuccessfully check circuit PFC whether can be less than with determines counting value first threshold TH1 (or More than Second Threshold TH2).For example, when being counted to closing unit, pass through/unsuccessfully check that circuit PFC can be with determines counting Whether value is less than first threshold TH1.When being counted to opening unit, pass through/unsuccessfully check that circuit PFC can be with determines counting Whether value is more than Second Threshold TH2.For example, Second Threshold TH2 can be identical or different with first threshold TH1.

If count value is less than first threshold TH1 (or more than Second Threshold TH2), in step S240, it is wiped free of Memory cell can be determined that in normal condition.If count value is not less than first threshold TH1 (or no more than Second Thresholds TH2), then in step s 250, the memory cell being wiped free of can be determined that in abnormality.

Fig. 8 is to illustrate being counted wherein based on monitoring reading result to closing unit according to example embodiment The figure of example.In addition to further illustrating monitoring voltage VFYM, the 3rd region A3 and the 4th region A4, Fig. 8 can be with Fig. 4 is identical, and therefore omits repetitive description.

With reference to Fig. 2, Fig. 7 and Fig. 8, monitoring voltage VFYM (for example, VFYM1) can be less than erasing verifying voltage VFYE. For example, monitoring voltage VFYM1 can be the midrange of the threshold voltage distribution corresponding with first memory block BLK1.When using When monitoring that voltage VFYM1 performs read operation, the storage in the threshold voltage distribution corresponding with first memory block BLK1 Memory cell among unit, belonging to the 3rd region A3 can be determined that closing unit.With second memory block BLK2 It is among memory cell in corresponding threshold voltage distribution, belong to the 3rd region A3 and the 4th region A4 memory cell can To be confirmed as closing unit.Therefore, when first threshold voltage TH1 is confirmed as the memory cell corresponding with the 3rd region A3 Quantity and the memory cell corresponding with the 3rd region A3 and the 4th region A4 quantity between value when, monitoring can be passed through Threshold voltage distribution of the read operation to determine erase status E memory cell is normal or abnormal.For example, it may be determined that The memory block (for example, first memory block BLK1) of the memory cell with the first quantity is in normal shape in 3rd region A3 State, and there is the memory cell of the second quantity of the memory cell for being more than the first quantity in the 3rd region A3 and the 4th region A4 Memory block (for example, memory block BLK2) be in abnormality.

Fig. 9 is to illustrate the figure for reading the example that result is counted to opening unit based on monitoring wherein.Except entering One step figure shows outside monitoring voltage VFYM2, the 5th region A5 and the 6th region A6 that Fig. 9 can be identical with Fig. 6, and because This omits repetitive description.

With reference to Fig. 2, Fig. 7 and Fig. 9, monitoring voltage VFYM (for example, VFYM2) can be less than erasing verifying voltage VFYE. For example, monitoring voltage VFYM2 can be the midrange of the threshold voltage distribution corresponding with first memory block BLK1.When using When monitoring that voltage VFYM2 performs read operation, the storage in the threshold voltage distribution corresponding with first memory block BLK1 It is among unit, belong to the 5th region A5 and the 6th region A6 memory cell can be determined that opening unit.With second Among memory cell in threshold voltage distribution corresponding memory block BLK2, memory cell belonging to the 6th region A6 can To be confirmed as opening unit.Therefore, when second threshold voltage TH2 is confirmed as the memory cell corresponding with the 6th region A6 Quantity and the memory cell corresponding with the 5th region A5 and the 6th region A6 quantity between value when, monitoring can be passed through Threshold voltage distribution of the read operation to determine erase status E memory cell is normal or abnormal.For example, it may be determined that The memory block of the memory cell with the 3rd quantity is (for example, first memory block in 5th region A5 and the 6th region A6 BLK1 normal condition) is in, and the 4th quantity for having the memory cell less than the 3rd quantity in the 6th region A6 is deposited The memory block (for example, memory block BLK2) of storage unit is in abnormality.

Figure 10 is to illustrate to perform erasing operation, monitoring read operation and extra wherein according to example embodiment The timing diagram of the process of the application of erasing voltage.In Fig. 10, abscissa represents time T, and ordinate is represented to be applied to and deposited The voltage V of storage unit.The operation on being applied to performed by the voltage of memory cell is shown in Figure 10 bottom diagram.

With reference to Fig. 1, Fig. 2 and Figure 10, each erasing circulation can include erasing part and erasing verification portion.In erasing portion In point, erasing voltage VERS can be applied to memory cell.In erasing verification portion, it can perform following：Erasing checking Read and pass through/unsuccessfully check.During erasing checking is read, erasing verifying voltage VFYE can be applied to memory cell. During passing through/unsuccessfully checking, it can verify that the result read counts come the quantity to closing unit according to erasing, and It can determine that erasing passes through or wiped failure according to count value.

When the result for passing through/failing inspection operation indicates erasing failure, next erasing circulation can be performed.Work as execution During next erasing circulation, erasing voltage VERS can be improved.

When the result for passing through/failing inspection operation indicates that erasing passes through, monitoring operation can be performed.Monitor that operation can be with Including monitoring read operation and monitoring inspection operation.During read operation is monitored, monitoring voltage VFYM, which can be applied to, to be deposited Storage unit., can be according to the result of monitoring read operation come to closing unit (or opening unit) during inspection operation is monitored Quantity counted, and can be determined according to count results (that is, count value) memory cell threshold voltage distribution be It is normal or abnormal.

, can be by extra wiping if monitoring that the result of read operation indicates the threshold voltage abnormal distribution of memory cell Except voltage VERS ' is applied to memory cell.For example, extra erasing voltage VERS ' can be applied to as wiping purposes target All main bodys in memory cell in memory block.The level of extra erasing voltage can with last (or recently ) erasing circulation erasing voltage level it is identical, lower or higher.

If monitoring that the result of read operation indicates that the threshold voltage distribution of memory cell is normal, it can terminate and wipe The associated processing of operation.

Figure 11 is the flow chart for the operating method for illustrating the application drawing 6 according to example embodiment；With reference to Fig. 1, Fig. 2 and Figure 11, in step S310, erasing voltage can be applied to memory cell.In step s 320, erasing can be used to verify Voltage VFYE performs checking read operation.Step S310 and S320 operation can be with step S110 and step S120 operation It is similar.

In step S330, when by/unsuccessfully check circuit PFC based on checking read operation result come to closing unit Quantity when being counted, control logic circuit 119 can control column decoder circuitry 113 and page buffer circuit 115, with Just monitoring read operation is performed using monitoring voltage VFYM.It can be performed in the mode similar to step S130 operation The step S330 wherein counted to closing unit operation.It can be performed in the mode similar to step S210 operation The step S330 of monitoring read operation operation is performed wherein.In the exemplary embodiment, when passing through/unsuccessfully check circuit PFC When being counted based on the result of checking read operation come the quantity to closing unit, control logic circuit 119 can use prison Monitoring read operation is performed depending on voltage VFYM.

In step S340, it can determine that erasing passes through or wiped mistake according to the result counted to closing unit Lose.If it is determined that erasing failure, then process may proceed to step S350, in step S350, improve erasing voltage.Afterwards, Process may proceed to step S310.If it is determined that erasing failure, then can ignore the result of monitoring read operation, and can be with Reset page buffer circuit 115.If it is determined that erasing passes through, then process may proceed to step S360.Step S340 and S350 operation can be similar to step S140 and S150 operation.

If it is determined that erasing passes through, then passing through/unsuccessfully check circuit PFC can supervise from the reception of page buffer circuit 115 Depending on the result of read operation.In step S360, pass through/unsuccessfully check that circuit PFC can be to closing unit (or opening unit) Quantity counted.In step S370, pass through/unsuccessfully check that circuit PFC can be with determines counting result (for example, count value) Whether first threshold TH1 (or more than Second Threshold TH2) is less than.If count value is less than first threshold TH1 (or more than the second threshold Value TH2), then normal shape can be determined to be in by threshold voltage distribution by step S380, passing through/unsuccessfully check circuit PFC State.If count value is not less than first threshold TH1 (or no more than Second Threshold TH2), in step S390, passes through/fail Check that threshold voltage distribution can be defined as abnormality by circuit PFC.Step S360 to step S390 operation can be with step Rapid S220 to S250 operation is similar.

Figure 12 is to illustrate to perform erasing operation, monitoring read operation and extra wherein according to Figure 11 application The timing diagram of the process of the application of erasing voltage.In fig. 12, abscissa represents time T, and ordinate is represented to be applied to and deposited The voltage V of storage unit.The operation on being applied to performed by the voltage of memory cell is shown in Figure 12 bottom diagram.

With reference to Fig. 1, Fig. 2 and Figure 12, each erasing circulation can include erasing part and erasing verification portion.In erasing portion In point, erasing voltage VERS can be applied to memory cell.In erasing verification portion, it can perform following：Erasing checking Read and pass through/unsuccessfully check.During reading is verified, erasing verifying voltage VFYE can be applied to memory cell.Logical During crossing/unsuccessfully checking, it can verify that the result read count come the quantity to closing unit according to erasing, and can be with Determine that erasing passes through or wiped failure according to count value.

It can be performed in parallel using the monitoring read operation for monitoring that voltage VFYM is carried out with passing through/unsuccessfully checking.In reality Apply in example, monitoring read operation can be included as a part for erasing circulation.

When the result for passing through/failing inspection operation indicates erasing failure, next erasing circulation can be performed.Work as execution During next erasing circulation, erasing voltage VERS can be improved.Furthermore, it is possible to ignore the monitoring carried out using monitoring voltage VFYM The result of read operation.

When the result for passing through/failing inspection operation indicates that erasing passes through, monitoring inspection operation can be performed.In monitoring inspection During looking into operation, it can be counted according to the result of monitoring read operation come the quantity to closing unit (opening unit), and And it is normal or abnormal that can determine that the threshold voltage of memory cell is distributed according to count results (that is, count value).

If monitoring that the result of inspection operation indicates the threshold voltage abnormal distribution of memory cell, extra erasing voltage VERS ' can be applied to memory cell.For example, extra erasing voltage VERS ' can be applied to as wiping purposes target The raceway groove of memory cell in memory block.The erasing voltage that the level of extra erasing voltage can be circulated with last erasing Level it is identical, lower or higher.

If monitoring that the result of inspection operation indicates that the threshold voltage distribution of memory cell is normal, it can terminate and wipe The associated processing of operation, without applying extra erasing voltage to memory cell.

The difference of Figure 12 timing diagram and Figure 10 timing diagram can be：Pass through/fail the same of inspection performing Shi Zhihang monitors read operation.Because performing monitoring read operation concurrently with each other and passing through/fail inspection operation, it is possible to Do not postpone erasing circulation.In addition, when it is determined that erasing passes through, process can be directly to monitoring inspection operation, without Monitoring read operation is executed separately.This, which can enable to reduce, determines whether that applying extra erasing voltage VERS ' spends The time taken.

Figure 13 is to illustrate to manage abnormal information according to the non-volatile memory devices wherein 110 of example embodiment The flow chart of method.With reference to Fig. 1, Fig. 2 and Figure 13, in step S410, non-volatile memory devices 110 can be for institute The memory cell of the memory block of selection performs erasing operation.

In the step s 420, nonvolatile memory 110 can determine that selected memory block is to be in normal condition It is in abnormality.For example, after can terminating referring to the monitoring inspection operation described by Fig. 6, Fig. 7 and Figure 11, Perform step S420.If selected memory block is determined to be in normal condition, non-volatile memory devices 110 The following operation associated with abnormal information can not be performed.If selected memory block is determined to be in abnormal shape State, then can perform step S430.

In step S430, non-volatile memory devices 110 can store the selected memory block of instruction in different The abnormal information of normal state.Abnormal information can be stored among the memory cell in selected memory block, storage is empty In the free memory locations of not busy information, in the memory cell for the source memory block for storing metamessage, or control logic circuit 119 In register in.Abnormal information can be corresponding with the address of selected memory block.

In step S440, non-volatile memory devices 110 can be in the memory block associated with abnormality Use abnormal information at erasing operation below.For example, non-volatile memory devices 110 can be based on coming from external equipment The erasing order of (for example, controller) and address select the second memory block to be wiped free of.Non-volatile memory devices 110 can determine that the abnormal information associated with selected second memory block is stored in memory cell array 111 Also it is stored in control logic circuit 119.If the abnormal information associated with selected second memory block is true Be set to and be stored therein, then non-volatile memory devices 110 can to second memory block perform erasing operation after or Monitoring read operation is not performed while performing erasing operation.After erasing operation is performed, non-volatile memory devices 110 Extra erasing voltage can be applied to the raceway groove of the memory cell in second memory block, without performing monitoring inspection operation.

It is non-easy if the abnormal information associated with selected second memory block is confirmed as being not stored in wherein The property lost memory devices 110 can perform erasing operation and associated with erasing operation as described by reference Fig. 6 to Figure 12 Processing.Here, the processing associated with erasing operation can include performing monitoring read operation, monitoring inspection operation and base Optionally apply extra erasing voltage in the result of monitoring inspection operation.

Figure 14 is to illustrate the suppressing exception information of non-volatile memory devices wherein 110 according to example embodiment The flow chart of method.With reference to Fig. 1, Fig. 2 and Figure 14, in step S510, non-volatile memory devices 110 can be together with first Begin to count and store abnormal information together.For example, initial count can be positive integer.For other examples, initial count can be “1”。

In step S520, what non-volatile memory devices 110 can be in response to external equipment (for example, controller) please Ask, pair memory block associated with abnormal information performs erasing operation.Based on the abnormal information stored, non-volatile memories Device equipment 110 can be it is determined that the after-applied extra erasing voltage that erasing passes through.Now, non-volatile memory devices 110 Monitoring read operation and monitoring inspection operation can not be performed.

In step S530, non-volatile memory devices 110 can reduce counting from initial count.For example, counting 1 can be reduced.

In step S540, can determine to perform based on abnormal information the memory block of erasing operation counting whether For " 0 ".If it not is " 0 " to count, abnormal information can be preserved with the state being lowered, without deleting.If be counted as " 0 ", then in step S550, non-volatile memory devices 110 can be with suppressing exception information and counting.

By the patterns of data and memory block BLK1 to BLKz that are write at memory block BLK1 to BLKz are worked as In change in physical properties, in fact it could happen that memory block BLK1 to the characteristic variations between BLKz.If for example, in memory block Write-in to perform erasing operation after the data of the change pattern of characteristic changing at BLKa, then memory block BLKa erasing shape State E threshold voltage distribution may change from reset condition.For example, the threshold of the memory cell in first memory block BLK1 Threshold voltage distribution may change the threshold voltage distribution to the memory cell in second memory block BLK2.Afterwards, if according to Specific frequency repeats the programming operation and erasing operation of the data of normal mode for memory block BLKa, then memory block BLKa erase status E threshold voltage distribution may return to reset condition.For example, second memory illustrated in Fig. 5 The threshold value for the memory cell that the threshold voltage distribution of memory cell in block BLK2 may return in first memory block BLK1 Voltage's distribiuting.

Therefore, as described by with reference to Figure 14, if grasped when being programmed after specific memory block is confirmed as exception Suppressing exception information when work and erasing operation are repeated multiple as initial count, then can prevent from recovering specifically to deposit The after-applied extra erasing voltage of the threshold voltage distribution of reservoir block.

In embodiment, normal mode can be the pattern of the degree of randomness with more than or equal to threshold value, and change Pattern can be the pattern of the degree of randomness with less than threshold value.

Figure 15 is to illustrate to manage abnormal information according to the non-volatile memory devices wherein 110 of example embodiment The flow chart of method.With reference to Fig. 1, Fig. 2 and Figure 15, in step S610, non-volatile memory devices 110 can be on institute The memory block of selection performs erasing operation.On erasing operation, non-volatile memory devices 110 can perform monitoring and read Operation, monitoring inspection operation and the result based on monitoring read operation and monitoring inspection operation optionally apply extra wiping Except the operation of voltage.

In step S620, non-volatile memory devices 110 can determine that selected memory block is confirmed as place Whether it is more than the 3rd threshold value TH3 in the quantity of the event of abnormality.For example, non-volatile memory devices 110 can be by institute The quantity or selected memory block that the memory block of selection is determined to be in the continuous events of abnormality are determined It is compared for discontinuous event and/or the quantity of continuous events in abnormality with the 3rd threshold value TH3.

If therefore the quantity of identified event is less than or equal to the 3rd threshold value TH3, non-volatile memory devices 110 can not store abnormal information.If therefore the quantity of identified event is more than the 3rd threshold value TH3, non-volatile to deposit Storage device 110 can store the abnormal information associated with selected memory block.

For example, non-volatile memory devices 110 can store abnormal information.Afterwards, in the side with reference to described by Figure 14 In method, non-volatile memory devices 110 can be with suppressing exception information.It is used as another example, non-volatile memory devices 110 It can determine and manage the selected memory block as abnormal mass.For example, the erasing operation to abnormal mass can companion With the operation for applying extra erasing voltage, without monitoring read operation and monitoring inspection operation.

Figure 16 is the block diagram for illustrating the storage device 100 according to example embodiment.With reference to Figure 16, storage device 100 can With including non-volatile memory devices 110, controller 120 and random access memory (RAM) 130.

Non-volatile memory devices 110 can perform write-in under the control of controller 120, read or erasing operation. Non-volatile memory devices 110 can be received from controller 120 by input/output channel and ordered and address.It is non-volatile Memory devices 110 by input/output channel can exchange data with controller 120.

Non-volatile memory devices 110 can include flash memory.However, the scope of the present disclosure and spirit can not It is limited to this.For example, non-volatile memory devices 110 can include at least one non-volatile memory devices, such as phase transformation RAM (PRAM), magnetic RAM (MRAM), resistance-type RAM (RRAM) and ferroelectricity RAM (FeRAM).

Memory Controller 120 can be configured as accessing non-volatile memory devices 110.For example, controller 120 can To control non-volatile memory devices 110 by input/output channel and control channel, so as to perform write-in, read or Erasing operation.

Controller 120 can get off to control non-volatile memory devices in the control of external host device (not shown) 110.For example, controller 120 can be based on the form different from the form for the communication with non-volatile memory devices 110 To be communicated with external host device.The unit for the data that controller 120 is passed on to non-volatile memory devices 110 can be with It is different from the unit for the data that controller 120 is passed on to external host device.

Controller 120 can use RAM 130 as working storage, buffer storage or cache memory.Control Device 120 processed can be in the data required for storage management non-volatile memory devices 110 at RAM 130 or code.For example, control Device 120 processed can read managing non-volatile memory equipment 110 from non-volatile memory devices 110 required for data or Code, and the data read or code can be carried on RAM 130 for driving.

RAM 130 can include at least one in a variety of random access memory, such as, but not limited to, static RAM (SRAM), dynamic ram (DRAM), synchronous dram (SRAM), PRAM, MRAM, RRAM and FRAM.

In figure 16, embodiment of the disclosure is illustrated as RAM 130 and is disposed in outside controller 120.However, this public affairs The scope and spirit opened can be with not limited to this.For example, storage device 100 can not include being disposed in outside controller 120 RAM 130.Controller 120 can use internal RAM (referring to Fig. 9) as buffer storage, working storage or cache Memory.

Wiped for example, non-volatile memory devices 110 can perform monitoring read operation, monitoring inspection operation and apply Except the operation of voltage, as described by referring to figs. 1 to Figure 15.As described by with reference to figures 13 to Figure 15, nonvolatile memory Equipment 110 can manage abnormal information and can determine whether that performing monitoring read operation and monitoring examines based on abnormal information Look into operation.

In embodiment, controller 120 can include error controller EC.Error controller EC may determine whether on The erasing operation of non-volatile memory devices 110 performs monitoring read operation and monitoring inspection operation.Nonvolatile memory Equipment 110 may determine whether to perform monitoring read operation and monitoring inspection operation under error controller EC control.

In embodiment, the error controller EC of controller 120 can manage abnormal information and can be based on abnormal letter Cease to control non-volatile memory devices 110.Non-volatile memory devices 110 can be configured as carrying to controller 120 For abnormal information.

Figure 17 is the flow chart for the operating method for illustrating the storage device 100 according to example embodiment.With reference to Figure 16 and Figure 17, in step S710, controller 120 can transmit the erasing order of the first kind to non-volatile memory devices 110. In step S720, non-volatile memory devices 110 can perform erasing operation in response to the erasing order of the first kind Together with monitoring read operation.After determining that erasing passes through at erasing operation, non-volatile memory devices 110 can be performed Read operation is monitored, inspection operation is monitored and is optionally applied based on monitoring read operation and monitoring the result of inspection operation Plus the operation of extra erasing voltage.

It is non-volatile in step S730 if monitoring that the result of inspection operation indicates abnormality in step S720 Property memory devices 110 can to controller 120 transmit abnormal information.In step S740, controller 120 can be stored from non- Abnormal information received by volatile memory devices 110.

When the memory block for the abnormal information that is stored with wherein asks erasing operation, in step S750, control Device 120 can transmit the erasing order of Second Type to non-volatile memory devices 110.It is non-volatile in step S760 Memory devices 110 can perform erasing operation in response to the erasing order of Second Type, and be not accompanied by monitoring and read behaviour Make.For example, after determining that erasing passes through at erasing operation, non-volatile memory devices 110 can apply extra erasing Voltage, without performing monitoring read operation and monitoring inspection operation.

In embodiment, as with reference to described by Figure 14, controller 120 can manage the counting associated with abnormal letter, And can be based on counting suppressing exception information.

In embodiment, as described by reference Figure 15, when the number of the memory cell of the specific memory block received When amount is more than or equal to threshold value, controller 120 can transmit the erasing order of Second Type to specific memory block.

Figure 18 is to illustrate to be based on environmental condition control monitoring reading according to the storage device wherein 100 of example embodiment The flow chart of the method for operation.With reference to Figure 16 and Figure 18, in step S810, controller 120 can monitor non-volatile memories The state of device equipment 110.For example, controller 120 can monitor the volume of each memory block of non-volatile memory devices 110 The quantity of journey/erasing circulation, or monitor the pattern of the programmed data at each memory block.

In step S820, controller 120 can determine whether monitored state reaches threshold condition.For example, control Device 120 can determine whether the quantity of the program/erase circulation of each memory block is more than reference value.Controller 120 can be true Whether the degree for being scheduled on the randomness of the pattern of the data write at each memory block is less than reference value.

If it is determined that the state monitored not up to threshold condition, then in step S830, controller 120 can be to being supervised Depending on state be not up to the memory block of threshold condition and enable monitoring read operation.For example, controller 120 can be to non-volatile Memory devices 110 provide control information, and the control information asks non-volatile memory devices 110 for the state that is monitored Not up to the memory of threshold condition performs erasing operation together with monitoring read operation.Non-volatile memory devices 110 can be with Store from the control information received by controller 120.It is corresponding with from the control information received by controller 120 when asking Memory block erasing operation when, non-volatile memory devices 110 can perform erasing at corresponding memory block Operation, and read operation, monitoring inspection operation can be monitored and based on the result selection for monitoring inspection operation based on performing Apply to property the operation of extra erasing voltage.For another example, when request is to from non-volatile memory devices 110 , the state monitored reach threshold condition memory block carry out erasing operation when, controller 120 can be deposited to non-volatile Storage device 110 provides the erasing order (referring to Figure 17) of the first kind.

If the state monitored is confirmed as reaching threshold condition, in step S840, controller 120 can be to institute The state of monitoring reaches the memory block disabling monitoring read operation of threshold condition.For example, controller 120 can be to non-volatile Memory devices 110 provide control information, and the control information asks non-volatile memory devices 110 in the state to being monitored Reach and do not perform monitoring read operation when the memory block of threshold condition performs erasing operation.Non-volatile memory devices 110 It can store from the control information received by controller 120.When exist pair with from the control information received by controller 120 During the request of the erasing operation of corresponding memory block, non-volatile memory devices 110 can be in corresponding memory Erasing operation is performed at block and the operation for optionally applying extra erasing voltage can be performed, is read without performing monitoring Operation and monitoring inspection operation.For another example, when request to it is from non-volatile memory devices 110, monitored State reach threshold condition memory block carry out erasing operation when, controller 120 can be to non-volatile memory devices 110 provide the erasing order (referring to Figure 17) of Second Type.

For example, can according to the program/erase of each memory block circulate quantity or to be written to each storage The pattern of the data of device block carrys out threshold value condition.

Figure 19 is the block diagram for schematically illustrating the controller 120 according to specific embodiment.With reference to Figure 19, controller 120 can include bus 121, processor 122, RAM 123, ECC Block 124, HPI 125, Buffer control circuit 126 with And memory interface 127.

Bus 121 can be configured as providing channel between the component of controller 120.

Processor 122 can control the overall operation of controller 120 and can be with execution logic computing.Processor 122 can To be communicated by HPI 125 with external host device, memory interface 127 and non-volatile memory devices can be passed through 110 communications, and can be communicated by Buffer control circuit 126 with RAM 130.Processor 122 can use RAM 123 to make Storage device 100 is controlled for working storage, cache memory or buffer storage.

RAM 123 is used as working storage, cache memory or the buffer storage of processor 122. RAM 123 can store processor 122 by the code of execution or order.RAM 123 can be stored as handled by processor 122 Data.RAM 123 can include static state RAM (SRAM).

ECC Block 124 can perform error correction operations.ECC Block 124 can be based on being write by memory interface 127 Enter the data to non-volatile memory devices 110 to perform error correction operations.The data of error correction coding can pass through Memory interface 127 is passed to non-volatile memory devices 110.ECC Block 124 can to by memory interface 127 from Data received by nonvolatile memory 110 perform error correcting/decoding.In embodiment, ECC Block 124 can be included The component of memory interface 127 is used as in memory interface 127.

HPI 125 can communicate under the control of processor 122 with external host device.HPI 125 can be with Communication is transmitted using at least one in various communication modes.

Buffer control circuit 126 can control RAM 130 under the control of processor 122.

Memory interface 127 can be deposited in response to the control of processor 122 with herein disclosed non-volatile Storage device 110 communicates.As described with reference to fig. 1, memory interface 127 can be by input/output channel to non-volatile Property memory devices 110 are transmitted an order, address and data.Memory interface 127 can be deposited by control channel to non-volatile Storage device 110 passes on control signal.

Figure 20 is the block diagram for illustrating the computing device 1000 according to specific embodiment.With reference to Figure 20, computing device 1000 Processor 1100, RAM 1200, storage device 1300, modem (modem) 1400 and user interface can be included 1500。

Processor 1100 can control the overall operation of computing device 1000, and can be with execution logic computing.Processor 1100 can be the data processing equipment based on following hardware：The hardware include physically being configured as performing by code or Operation in program expressed by included order.For example, processor 1100 can be on-chip system (SoC).Processor 1100 Can be general processor, application specific processor or application processor.

RAM 1200 can communicate with processor 1100.RAM 1200 can be processor 1100 or computing device 1000 Main storage.

Storage device 1300 can communicate with processor 1100.Storage device 1300 can be used for storage number for a long time According to.That is, processor 1100 can store the data to be stored for a long time at storage device 1300.

Storage device 1300 can include nonvolatile memory, such as flash memory, PRAM, MRAM, RRAM or FRAM。

Modem 1400 can under the control of processor 1100 with external device communication.For example, modem 1400 can wirelessly or wired mode and external device communication.

User interface 1500 can communicate under the control of processor 1100 with user.For example, user interface 1500 can be with Including user input interface, such as keyboard, keypad, button, touch panel, touch-screen, touch pad, touch ball, camera, Mike Wind, gyro sensor and vibrating sensor.User interface 1500 may further include user's output interface, such as liquid crystal Display (LCD), Organic Light Emitting Diode (OLED) display device, Activematric OLED (AMOLED) display device, luminous two Pole pipe (LED), loudspeaker and motor.

Storage device 1300 can include the storage device 100 in Figure 16.Processor 1100, RAM 1200, modulation /demodulation Device 1400 and user interface 1500 may be constructed the host device with storage communication.

In accordance with an embodiment of the present disclosure, the state of the threshold voltage for the memory cell that erasing passes through can be monitored, and can So that extra erasing voltage to be applied selectively to based on monitoring result to wipe the memory cell in the memory cell passed through.Cause This, the state for wiping the threshold voltage of the memory cell passed through can be consistent.

Although describing the present invention by reference to exemplary embodiment, it will be apparent that for those skilled in the art It can make various changes and modifications, without departing from the spirit and model of the disclosure such as limited by appended claims Enclose.

Claims

1. a kind of non-volatile memory devices, including：

Each include multiple memory cell in multiple memory blocks, the multiple memory block；

Address decoder circuit, memory cell is connected to by wordline；

Page buffer circuit, memory cell array is connected to by bit line；And

Control logic circuit, is configured as wiping of the control from the memory cell in the first memory block selected in memory block Division operation,

Wherein, erasing operation includes being iteratively performed erasing circulation, and the erasing circulation includes：Part is wiped, is wiped wherein Voltage is applied to the memory cell of first memory block, and erasing verification portion, reads voltage using first wherein The memory cell of first memory block is verified,

Wherein, the control logic circuit is configured such that, if erasing verification portion in first memory block storage Unit is confirmed as erasing and passed through, then the control logic circuit reads voltage using different from the first reading voltage second The memory cell of first memory block is read, and

Wherein, the control logic circuit is configured as based on the storage list that voltage reading first memory block is read using second The result of member, extra erasing voltage is applied to the memory cell of first memory block.

2. non-volatile memory devices according to claim 1, wherein, second, which reads voltage, reads electricity less than first Pressure.

3. non-volatile memory devices according to claim 2, wherein, the control logic circuit is configured as making , closed when the result based on the memory cell that first memory block is read using the second reading voltage is to perform reading Closing unit quantity be more than threshold value in the case of, memory cell from the control logic circuit to first memory block apply Extra erasing voltage.

4. non-volatile memory devices according to claim 2, wherein, the control logic circuit is configured as making , opened when the result based on the memory cell that first memory block is read using the second reading voltage is to perform reading Opening unit quantity be less than threshold value in the case of, memory cell from the control logic circuit to first memory block apply Extra erasing voltage.

5. non-volatile memory devices according to claim 2, wherein, erasing verification portion includes：Checking is read, Wherein the memory cell of first memory block is read using the first reading voltage；And pass through/unsuccessfully check, basis wherein Verify that the result read passes through determining erasing or wipes failure, and

Wherein, the control logic circuit is configured such that, when perform erasing verification portion in when passing through/unsuccessfully checking, Control logic circuit control row decoder circuits and page buffer circuit are to read the using the second reading voltage The memory cell of one memory block.

6. non-volatile memory devices according to claim 5, wherein, the control logic circuit is configured as making , when passing through/failing the result checked instruction erasing failure, the control logic circuit controls erasing operation, to perform It is next erasing circulation, regardless of whether using second read voltage performed by reading result how.

7. non-volatile memory devices according to claim 5, wherein, the control logic circuit is configured as making , when the result for passing through/failing inspection indicates that erasing passes through, the control logic circuit is utilized reads voltage institute using second The result of the reading of execution, to determine whether the memory cell of first memory block is in abnormality.

8. non-volatile memory devices according to claim 1, wherein, the level of extra erasing voltage with it is nearest The level of the erasing voltage of previous erasing circulation is identical.

9. non-volatile memory devices according to claim 1, wherein, the level of extra erasing voltage is higher than or low The level of the erasing voltage circulated in nearest previous erasing.

10. non-volatile memory devices according to claim 1, wherein, the control logic circuit is configured as, when When receiving the erasing order of the first kind, the memory cell that voltage reads first memory block is read using second；And work as When receiving the erasing order of Second Type, the memory cell that voltage reads first memory block is read without using second.

11. non-volatile memory devices according to claim 1, wherein, the control logic circuit is configured as, when When enabling monitoring read operation, the memory cell that voltage reads first memory block is read using second；And when disabling monitoring During read operation, the memory cell that voltage reads first memory block is read without using second, and

Wherein, monitoring read operation is by peripheral equipment control.

12. non-volatile memory devices according to claim 1, wherein, the control logic circuit is configured as making , when the memory cell of first memory block is in abnormality, control logic circuit storage is related to first memory block The abnormal information of connection.

13. non-volatile memory devices according to claim 12, wherein, the control logic circuit is configured as making , during the ensuing erasing operation to the memory cell of first memory block, the control logic circuit is based on being deposited The abnormal information of storage applies extra erasing voltage to the memory cell of first memory block, and in the storage of first memory block Unit is indicated as erasing after without the read operation using the second reading voltage.

14. non-volatile memory devices according to claim 12, wherein, the control logic circuit is configured as connecting Abnormal information is stored together with counting,

Wherein, the control logic circuit is configured such that when the execution at the selected memory cell of first memory block During ensuing erasing operation, the control logic circuit, which reduces, to be counted, and

Wherein, the control logic circuit is configured such that, when being counted as 0, the control logic circuit suppressing exception letter Breath and counting.

15. non-volatile memory devices according to claim 1, wherein, the control logic circuit is configured as making , when the memory cell of first memory block is determined to be in abnormality up to default number of times, the control logic electricity Road stores the abnormal information associated with first memory block.

16. a kind of storage device, including：

Non-volatile memory devices, comprising multiple memory blocks, each include multiple storages in the multiple memory block Unit；And

Controller, is configured as depositing for the selected of non-volatile memory devices to non-volatile memory devices transmission The erasing order of reservoir block,

Wherein, non-volatile memory devices can be configured to respond to erasing order to deposit selected memory block Storage unit performs erasing order,

Wherein, erasing operation includes being iteratively performed erasing circulation, and the erasing circulation includes：Part is wiped, is wiped wherein Voltage is applied to the memory cell of selected memory block, and erasing verification portion, wherein using erasing checking electricity Press to verify the memory cell of selected memory block, and

Wherein, non-volatile memory devices are configured such that, if the memory block selected in erasing verification portion Memory cell be confirmed as erasing and pass through, then non-volatile memory devices monitor the storage list of selected memory block Member, and

Wherein, non-volatile memory devices are configured such that, if the result monitored indicates selected memory block Memory cell be in abnormality, then memory cell from non-volatile memory devices to selected memory block apply volume Outer erasing voltage.

17. storage device according to claim 16, wherein, the memory cell of each memory block is formed with three Structure is tieed up, and

Wherein, each memory cell includes electric charge capture layer.

18. a kind of method for operating non-volatile memory devices, the non-volatile memory devices include multiple deposit Each include multiple memory cell in reservoir block, the multiple memory block, methods described includes：

A) apply erasing voltage to perform erasing by the memory cell of the first memory block into multiple memory blocks；

B) after erasing is performed, read voltage using first and read to perform first to the memory cell of first memory block；

C) counted based on the first result read come the quantity to opening unit and closing unit；

Voltage is read using read voltage less than first second to read to perform second to the memory cell of first memory block； And

Result based on the second read operation is held by applying extra erasing voltage to the memory cell of first memory block The extra erasing of row.

19. method according to claim 18, wherein, when the quantity of opening unit refers to quantity, or closing less than first The quantity of unit be more than with first with reference to quantity it is identical or different second with reference to quantity when, repeat step a), b) and c), and

Wherein, in repeat step a), b) and c) during, erasing voltage is little by little improved.

20. method according to claim 18, wherein, when the quantity of opening unit refers to quantity, or closing more than first When the quantity of unit is less than second identical or different with the first reference quantity with reference to quantity, performs second and read.