CN106970519A - Time test circuit and time method of testing - Google Patents
Time test circuit and time method of testing Download PDFInfo
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- CN106970519A CN106970519A CN201710349637.5A CN201710349637A CN106970519A CN 106970519 A CN106970519 A CN 106970519A CN 201710349637 A CN201710349637 A CN 201710349637A CN 106970519 A CN106970519 A CN 106970519A
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- time
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- voltage comparator
- delay unit
- gate delay
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
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- General Physics & Mathematics (AREA)
- Measurement Of Unknown Time Intervals (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention relates to a kind of time test circuit, including voltage comparator, oscillator, multiple D-latch, temperature code device and counter.The internal transmission signal that voltage comparator can export the precipitous step signal of a pair of rising edges to start to terminate with the time as the time；Oscillator is to include multistage gate delay unit delay chain circuits in series, and oscillator is connected with voltage comparator, counter respectively.Every grade of gate delay unit connects clock signal input terminal of the time end signal output end respectively with each D-latch in a D-latch, voltage comparator and is connected, and the input of the signal output part of each D-latch with temperature code device is connected.Time test circuit works, and passes through formula t=N × n × TLSB+n1×TLSBComputing relay time t, wherein N is the count value of counter, and n is total series of gate delay unit in delay chain, TLSBFor the time delay of single gate delay unit.The time test circuit and time method of testing can reduce signal in the flip-flop transition of gate delay at different levels and can reduce power consumption.
Description
Technical field
The present invention relates to digital circuit technique field, and in particular to a kind of time test circuit and time method of testing.
Background technology
With continuing to develop that integrated circuit dimensions are minimized, split-second precision test chip turns into study hotspot, tradition
Direct counting method, by the frequency of reference clock count the measurement for time of realizing, when clock frequency is GHz, its
Time resolution just reaches ns grades, and the frequency that its precision is referenced clock is limited significantly, it is impossible to meet higher measurement accuracy.
The time measurement method based on delay cell then is had also been proposed, time commencing signal is propagated in delay chain, and letter is terminated when the time
Number arrive when locking time commencing signal propagate position, the time that can be just measured by the number of computing relay chain.Its
Precision depends on the time delay of each delay cell, and time delay minimum reaches tens psecs.The gate delay time is believed by input
Number, the influence of the factor such as technique, circuit parameter structure and parasitic capacitance resistance.In directly being connected from trigger signal as delay
Transmitting signal, because long as the pulse signal rising time of trigger signal, while being mingled with interference signal, for prolonging
When being propagated in slow chain per one-level delay chain signal, flip-flop transition and the power consumption of signal are added, while interference signal is also easy to make
Into the mistake of circuit other parts.
The content of the invention
The technical problems to be solved by the invention are to provide one kind for above-mentioned prior art to reduce signal at different levels
The flip-flop transition of gate delay and the time test circuit and time method of testing that power consumption can be reduced.
The present invention the used technical scheme that solves the above problems is：A kind of time test circuit, it is characterised in that：Including
Voltage comparator, oscillator, multiple D-latch, temperature code device and counter；
The voltage comparator can export the precipitous step signal of a pair of rising edges and be tied using starting as the time with the time
The internal transmission signal of beam；
The oscillator is to include multistage gate delay unit delay chain circuits in series, first order gate delay unit
Input is connected with time commencing signal output end in the voltage comparator, the output end of afterbody gate delay unit with
The signal input part of the voltage comparator is connected, the input of the output end of afterbody gate delay unit also with counter
It is connected；
When the output end of every grade of gate delay unit is connected in the data input pin of a D-latch, the voltage comparator
Between clock signal input terminal of the end signal output end respectively with each D-latch be connected, the signal output part of each D-latch is equal
It is connected with the input of the temperature code device.
Preferably, the delay chain circuits include 50 grades of gate delay units.
In order to which the temperature code device uses semi-static dual-edge trigger.
A kind of time test method that use aforesaid time test circuit is carried out, it is characterised in that comprise the following steps：
Step 1: producing the precipitous step signal of a pair of rising edges as the time to start and the time by the use of voltage comparator
The internal transmission signal of end；
Step 2: after voltage comparator detects the triggering of time commencing signal, then control time commencing signal is in delay
Propagated in chain circuit；
Step 3: before the triggering of time end signal, each step signal is traveled to after afterbody gate delay unit, meter
Number device carries out Counts；
Step 4: after voltage comparator detects the triggering of time end signal, counter is stopped, while each D locks
Storage latches the state of each gate delay unit, and the status signal of each gate delay unit is sent into temperature code device, and temperature is compiled
Code device obtains the series n for the delay cell that step signal is traveled to1；
Step 5: passing through formula t=N × n × TLSB+n1×TLSBComputing relay time t, wherein N is the counting of counter
Value, n is total series of gate delay unit in delay chain, TLSBFor the time delay of single gate delay unit.
As an improvement, also including Step 6: t is tabled look-up according to DNL and INL, whole circuit is modified.
Improve again, voltage division processing is carried out to the step signal that the voltage comparator is exported, so as to obtain a rising edge
The internal transmission signal that shorter step signal starts to terminate with the time as the time.
Compared with prior art, the advantage of the invention is that：The time test circuit is in Conventional temporal digital quantizer
On the basis of, produce the precipitous step signal of a rising edge by the use of voltage comparator and start to believe with time finishing control as the time
Number, the step signal compares as the internal transmission signal of time measurement relative to outside input pulse signal rising time
Grow and be mingled with interference signal, reduce signal gate delay unit flip-flop transition, power consumption is reduced, while avoiding interference
Influence of the signal to circuit.Step signal is transmitted in an oscillator, after often having circulated once, is sent to again in delay cell, directly
To the triggering of time end signal, and then terminate the propagation of the step signal.Now, D-latch latches all gate delay cell-likes
State.By Counter Value and temperature code device value so as to try to achieve time delay.Because the gate delay time is by temperature, technique, voltage
Disturb and change etc. environmental factor, pass through the interference of correction these factors of reduction time delay on the door.
Brief description of the drawings
Fig. 1 is the circuit block diagram of time test circuit in the embodiment of the present invention.
Fig. 2 is time test circuit timing diagram in the embodiment of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing embodiment.
As shown in figure 1, the time test circuit in the present embodiment, it is characterised in that：Including voltage comparator 1, oscillator
2nd, multiple D-latch 3, temperature code device 4 and counter 5.
Voltage comparator 1 can be by biasing circuit, difference amplifier, common-source amplifier and push-pull cascade output circuit group
Into because the signal rising time that voltage comparator 1 is exported is oversize for carrying out to increase during delay transit in oscillator 2
The discharge and recharge time of electric capacity, it can accordingly increase the time delay of single gate delay unit 21, therefore to the output of voltage comparator 1
Step signal carries out voltage division processing, obtains that a shorter step signal of rising edge starts Start as the time and the time terminates
Stop internal transmission signal.The flip-flop transition of each gate delay unit 21 in delay chain can be so reduced, is surveyed for the time
The precision of examination circuit improves a lot.The final rising edge that produces is opened for 100ps step signal as the time in the present embodiment
Beginning Start and time terminate Stop internal transmission signal.If rising time continues to reduce, it is impossible to ensure that mos capacitance has
Enough discharge and recharge time, output will obtain the step signal of disorder, make the result of whole timekeeping circuit output error.
Oscillator 2 is to include delay chain electricity in multistage gate delay unit 21 delay chain circuits in series, the present embodiment
Road includes 50 grades of gate delay units 21.The input of first order gate delay unit 21 and time commencing signal in voltage comparator 1
Start output ends are connected, and the output end of afterbody gate delay unit 21 is connected with the signal input part of voltage comparator 1
Connect, the input of the output end of afterbody gate delay unit 21 also with counter 5 is connected.
Counter 5 is mainly designed to increase the measurement range of time, and the delay cell time is in fine measurement
30ps and 35ps, if not using circulation delay, time of measuring scope is too short.For the such high count frequency of general counter 5
The logical miss mistake of counter 5 can be caused, therefore, using double-edge counter 5 count frequency can be made to reduce half herein, together
When reduce the utilization of power consumption, to output signal carry out latch processing.
When the output end of every grade of gate delay unit 21 is connected in the data input pin of a D-latch 3, voltage comparator 1
Between clock signal input terminal of the end signal output end respectively with each D-latch 3 be connected, the signal output part of each D-latch 3
Input with temperature code device 4 is connected.Temperature code device 4 uses semi-static dual-edge trigger.
Such as Fig. 2, the time test method carried out using foregoing time test circuit is comprised the following steps：
Step 1: by the use of voltage comparator 1 produce the precipitous step signal of a pair of rising edges using start as the time and when
Between the internal transmission signal that terminates；
Step 2: after voltage comparator 1 detects the triggering of time commencing signal, then control time commencing signal is in delay
Propagated in chain circuit；
Step 3: before the triggering of time end signal, each step signal is traveled to after afterbody gate delay unit 21,
Counter 5 carries out Counts；
Step 4: after voltage comparator 1 detects the triggering of time end signal, counter 5 is stopped, while each D
Latch 3 latches the state of each gate delay unit 21, and the status signal of each gate delay unit 21 is sent into temperature code device
4, temperature code device 4 obtains the series n for the delay cell that step signal is traveled to1；
Step 5: passing through formula t=N × n × TLSB+n1×TLSBComputing relay time t, wherein N is the counting of counter 5
Value, n is total series of gate delay unit 21 in delay chain, TLSBFor the time delay of single gate delay unit 21.
Step 6: t is tabled look-up according to DNL and INL, whole circuit is modified, temperature can be reduced by amendment
The interference of the environmental factors such as degree, technique, voltage time delay on the door.
Whole time measuring circuit design is completed under TSMC 180nm techniques, is emulated by Cadence Spectre
It is 20ps to the time measuring circuit the least measuring time, maximum measuring time is 16ns, and differential nonlinearity (DNL) is
0.6LSB, integral nonlinearity (INL) is 2.2LSB.
Claims (6)
1. a kind of time test circuit, it is characterised in that：Including voltage comparator, oscillator, multiple D-latch, temperature code
Device and counter；
The voltage comparator can export the precipitous step signal of a pair of rising edges to start what is terminated with the time as the time
Internal transmission signal；
The oscillator is to include multistage gate delay unit delay chain circuits in series, the input of first order gate delay unit
End be connected with time commencing signal output end in the voltage comparator, the output end of afterbody gate delay unit with it is described
The signal input part of voltage comparator is connected, and the output end of afterbody gate delay unit is also connected with the input of counter
Connect；
The output end of every grade of gate delay unit connects time knot in the data input pin of a D-latch, the voltage comparator
Clock signal input terminal of the beam signal output part respectively with each D-latch is connected, and the signal output part of each D-latch is and institute
The input for stating temperature code device is connected.
2. time test circuit according to claim 1, it is characterised in that：The delay chain circuits include 50 grades of gate delays
Unit.
3. time test circuit according to claim 1, it is characterised in that：The temperature code device is using semi-static bilateral
Along trigger.
4. a kind of time test method that time test circuit using as described in claims 1 to 3 any claim is carried out,
It is characterized in that comprising the following steps：
Terminated Step 1: producing the precipitous step signal of a pair of rising edges by the use of voltage comparator using starting as the time with the time
Internal transmission signal；
Step 2: after voltage comparator detects the triggering of time commencing signal, then control time commencing signal is in delay chain electricity
Propagated in road；
Step 3: before the triggering of time end signal, each step signal is traveled to after afterbody gate delay unit, counter
Carry out Counts；
Step 4: after voltage comparator detects the triggering of time end signal, counter is stopped, while each D-latch
The state of each gate delay unit is latched, and the status signal of each gate delay unit is sent to temperature code device, temperature code device
Obtain the series n for the delay cell that step signal is traveled to1；
Step 5: passing through formula t=N × n × TLSB+n1×TLSBComputing relay time t, wherein N is the count value of counter, and n is
Total series of gate delay unit, T in delay chainLSBFor the time delay of single gate delay unit.
5. time test method according to claim 4, it is characterised in that：Also include Step 6: by t according to DNL and INL
Tabled look-up, whole circuit is modified.
6. time test method according to claim 4, it is characterised in that：The step letter exported to the voltage comparator
Number voltage division processing is carried out, passed so as to obtain the inside that a shorter step signal of rising edge starts to terminate with the time as the time
Defeated signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710349637.5A CN106970519A (en) | 2017-05-17 | 2017-05-17 | Time test circuit and time method of testing |
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|---|---|---|---|
| CN201710349637.5A CN106970519A (en) | 2017-05-17 | 2017-05-17 | Time test circuit and time method of testing |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109450411A (en) * | 2019-01-04 | 2019-03-08 | 京东方科技集团股份有限公司 | Latch and its driving method and chip |
| CN109509506A (en) * | 2018-12-20 | 2019-03-22 | 珠海博雅科技有限公司 | To the detection method and device of Vcc when a kind of power up test |
| CN110764395A (en) * | 2018-07-25 | 2020-02-07 | 苏州超锐微电子有限公司 | Annular time-to-digital conversion circuit applied to SPAD detector |
| CN110945788A (en) * | 2017-07-28 | 2020-03-31 | 高通股份有限公司 | Voltage histogram generation |
| CN111033312A (en) * | 2017-08-31 | 2020-04-17 | 深圳市大疆创新科技有限公司 | Delay time calibration for optical distance measurement devices and associated systems and methods |
| CN111157878A (en) * | 2019-12-31 | 2020-05-15 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Solder joint test structure and test method thereof |
| CN112824983A (en) * | 2019-11-20 | 2021-05-21 | 圣邦微电子（北京）股份有限公司 | Time measuring circuit, time measuring chip and time measuring device |
| CN114563682A (en) * | 2020-11-27 | 2022-05-31 | 上海寒武纪信息科技有限公司 | Method and apparatus for calculating static delay timing of integrated circuit |
-
2017
- 2017-05-17 CN CN201710349637.5A patent/CN106970519A/en active Pending
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| 李乾锋: "基于0_18um_CMOS工艺的时间数字转换器的设计与实现", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110945788A (en) * | 2017-07-28 | 2020-03-31 | 高通股份有限公司 | Voltage histogram generation |
| CN111033312A (en) * | 2017-08-31 | 2020-04-17 | 深圳市大疆创新科技有限公司 | Delay time calibration for optical distance measurement devices and associated systems and methods |
| CN110764395A (en) * | 2018-07-25 | 2020-02-07 | 苏州超锐微电子有限公司 | Annular time-to-digital conversion circuit applied to SPAD detector |
| CN109509506A (en) * | 2018-12-20 | 2019-03-22 | 珠海博雅科技有限公司 | To the detection method and device of Vcc when a kind of power up test |
| CN109450411A (en) * | 2019-01-04 | 2019-03-08 | 京东方科技集团股份有限公司 | Latch and its driving method and chip |
| CN109450411B (en) * | 2019-01-04 | 2022-10-11 | 京东方科技集团股份有限公司 | Latch and driving method thereof and chip |
| CN112824983A (en) * | 2019-11-20 | 2021-05-21 | 圣邦微电子（北京）股份有限公司 | Time measuring circuit, time measuring chip and time measuring device |
| CN112824983B (en) * | 2019-11-20 | 2022-08-19 | 圣邦微电子（北京）股份有限公司 | Time measuring circuit, time measuring chip and time measuring device |
| CN111157878A (en) * | 2019-12-31 | 2020-05-15 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Solder joint test structure and test method thereof |
| CN114563682A (en) * | 2020-11-27 | 2022-05-31 | 上海寒武纪信息科技有限公司 | Method and apparatus for calculating static delay timing of integrated circuit |
| CN114563682B (en) * | 2020-11-27 | 2024-01-26 | 上海寒武纪信息科技有限公司 | Method and apparatus for calculating static delay time sequence of integrated circuit |
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Application publication date: 20170721 |