CN106952650A - A kind of train voice amplifying unit based on ARM+FPGA frameworks - Google Patents
A kind of train voice amplifying unit based on ARM+FPGA frameworks Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
- H04H20/44—Arrangements characterised by circuits or components specially adapted for broadcast
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G10—MUSICAL INSTRUMENTS; ACOUSTICS
- G10L—SPEECH ANALYSIS OR SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING; SPEECH OR AUDIO CODING OR DECODING
- G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
- G10L19/0017—Lossless audio signal coding; Perfect reconstruction of coded audio signal by transmission of coding error
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- G—PHYSICS
- G10—MUSICAL INSTRUMENTS; ACOUSTICS
- G10L—SPEECH ANALYSIS OR SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING; SPEECH OR AUDIO CODING OR DECODING
- G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
- G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
- G10L19/16—Vocoder architecture
- G10L19/18—Vocoders using multiple modes
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- G—PHYSICS
- G10—MUSICAL INSTRUMENTS; ACOUSTICS
- G10L—SPEECH ANALYSIS OR SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING; SPEECH OR AUDIO CODING OR DECODING
- G10L21/00—Processing of the speech or voice signal to produce another audible or non-audible signal, e.g. visual or tactile, in order to modify its quality or its intelligibility
- G10L21/02—Speech enhancement, e.g. noise reduction or echo cancellation
- G10L21/0316—Speech enhancement, e.g. noise reduction or echo cancellation by changing the amplitude
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
- H04H20/53—Arrangements specially adapted for specific applications, e.g. for traffic information or for mobile receivers
- H04H20/61—Arrangements specially adapted for specific applications, e.g. for traffic information or for mobile receivers for local area broadcast, e.g. instore broadcast
- H04H20/62—Arrangements specially adapted for specific applications, e.g. for traffic information or for mobile receivers for local area broadcast, e.g. instore broadcast for transportation systems, e.g. in vehicles
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
- H04H20/86—Arrangements characterised by the broadcast information itself
- H04H20/88—Stereophonic broadcast systems
Abstract
The invention discloses a kind of train voice amplifying unit based on ARM+FPGA frameworks, belong to embedded system field.The train voice amplifying unit includes main control module, encoding and decoding amplification module and the part of communication module three.Main control module includes main control chip and peripheral components, is responsible for initialization, audio storage and the processing of system, and operation application program and AGC, amplitude limit limit frequency algorithm.Encoding and decoding amplification module includes encoding and decoding submodule, power amplifier submodule and detection sub-module, is responsible for that the audio signal of various forms is handled and amplified, while realizing current detecting and audio degradation function.Communication module includes two-way gigabit Ethernet and RS485 and RS232 buses, is responsible for audio and inspection signal transmission of making an uproar.Each functional module co-ordination, constitutes complete voice amplifying unit.The present invention can be applied in the field of traffic such as motor-car, city underground, light rail.
Description
Technical field
The invention belongs to embedded computer field, it is related to a kind of train voice amplification based on ARM+FPGA frameworks single
Member.
Background technology
With sharply increasing for multimedia era information content, the information content of train communication is consequently increased, therefore track is handed over
The logical performance to train broadcasting system proposes higher and higher requirement.First, audio transmission network service will have real-time
The characteristics of, this requires that the bandwidth of communication equipment is improved constantly；Secondly, requirement of the broadcasting for train to tonequality, audio is improved constantly,
This is accomplished by quantization digit for improving sample frequency and increasing digital-to-analogue conversion etc.；Again, broadcasting for train needs to be made an uproar according to environment
The change of sound automatically adjusts broadcast volume, and should ensure that broadcast is not disturbed by artificial and environmental factor when manually broadcasting, this
Require that broadcast system is needed with functions such as noise measuring and automatic growth controls；Finally, in order to ensure broadcasting for train system
The stability of system, it is desirable to the characteristics of train broadcasting system has backup, it is ensured that the artificial broadcast of unimpeded or maintenance of communication network
Etc. basic function.In this context, the present invention proposes a kind of train voice amplifying unit based on ARM+FPGA frameworks, with full
The demand of sufficient current train broadcast system.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of train voice amplifying unit based on ARM+FPGA frameworks, make
Communicated with gigabit Ethernet and encoding and decoding and power amplification can be carried out to the audio signal of various forms, while can also be real
Existing stereo audio, the output of high-low sound frequency branch, volume and Gain Automatic control, induced field current are detected and audio degrades etc.
Function.
Technical scheme：
A kind of train voice amplifying unit based on ARM+FPGA frameworks, the train voice amplifying unit includes three functions
Module：Main control module, encoding and decoding amplification module, communication module.
Main control module is made up of main control chip and its peripheral components, the initialization of main responsible system, the storage of audio
The operation of frequency algorithm is limited with processing, AGC (automatic growth control) and amplitude limit.Main control chip uses the processing of ARM+FPGA frameworks
Device, inside includes double ARM Cortex-A9 kernels, FPGA and Dram control interface, static memory control interface, SDIO
Interface, gigabit MAC interface, UART interface etc., wherein double ARM Cortex-A9 kernels are connected with FPGA by AXI high-speed buses,
Double ARM kernels are mainly responsible for the processing of audio signal, and FPGA is responsible for forwarding, AGC and the amplitude limit limit frequency algorithm of audio signal
Operation, AGC algorithms are exported for the different amplitude audio signals of input to be converted into identical amplitude, and amplitude limit limit frequency algorithm is used
In the amplitude versus frequency characte for limiting audio signal.Peripheral components include DDR3 memory chips, Flash chip, iNAND chips, CPLD cores
Piece and clock-reset chip；Wherein, DDR3 memory chips are connected with the Dram control interface of main control chip, for running
Operating system and application program；Flash chip is connected with the static memory control interface of main control chip, for depositing
Bootloader files；INAND chips are connected depositing as application program and audio file with the SDIO interfaces of main control chip
Store up chip；CPLD chips are used to ensure the security of various algorithms in FPGA；Clock-reset chip is used to provide reliable to master control
Clock and reset signal.The gigabit MAC interface of FPGA extensions is connected with the chip of ethernet physical layer all the way of communication module,
It is used as audio signal transmission path；The gigabit MAC interface of main control chip and another road ethernet physical layer chip of communication module
It is connected, is used as the backup of communication network；Main control chip UART interface and FPGA extension UART interface respectively with communication module
RS232 with RS485 bus transceivers are connected, for equipment debugging and inspection signal transmission of making an uproar；FPGA extended SPIs, I2S and I2C
Interface is used for the transmission and configuration management of audio signal between main control module and encoding and decoding amplification module.
Encoding and decoding amplification module includes encoding and decoding submodule, power amplifier submodule and detection sub-module.Encoding and decoding submodule by
Two-way codec chip, two-way switch and wave filter group into.It is lossless and damage two groups of codec chips and realize various forms
The encoding and decoding of audio signal；Two-way switch controls the gating of two-way codec chip；Wave filter is responsible for the height in audio signal
Low frequency component is separated.Encoding and decoding submodule separates output using left and right acoustic channels, and audio signal passes through different power amplifications
Chip can realize that different content is played in the guest room left and right sides, so as to reach stereosonic effect.Power amplifier submodule is by four railway digitals
Power amplifier chips and low pass filter composition.It is high that four railway digital power amplifier chips constitute left and right acoustic channels low frequency channel, left and right acoustic channels
Frequency path, left and right acoustic channels high frequency channel and left and right acoustic channels low frequency channel correspond to corresponding middle/high frequency loudspeaker respectively and low frequency is raised
Sound device, it is to avoid use full range speaker.Detection sub-module is made up of induced field current detector and analogue audio frequency path.Magnetic
Induced-current detector detects the electric current of digital power amplifier output channel by Hall effect, can determine that and raises according to the change of electric current
The short circuit of sound device circuit network and open circuit；Analogue audio frequency path is used to realize audio degradation function, i.e., when communication network failure
The audio signal of acceptable analogue audio frequency path transmission, maintains basic artificial broadcast capability, and codec chip has been internally integrated firmly
Part automatic gain control function, can make the audio signal of input reach identical output amplitude, it is ensured that broadcast volume is not by artificial
Factor is disturbed.
Communication module is made up of two-way gigabit Ethernet, RS485 buses and RS232 buses, is mainly used in audio with making an uproar
Examine the transmission and unit debugging of signal.Two-way gigabit Ethernet is used to transmit audio signal, wherein being located at equipment all the way
The backboard of unit, another road is located at the panel of unit, the backboard gigabit that audio signal passes through unit when normally using
Ethernet enters main control module, and panel gigabit ethernet interface is used for the backup of communication network, when the event of backboard gigabit Ethernet
During barrier, panel gigabit Ethernet can switch to, it is ensured that the stability of broadcast system.Ethernet physical layer chip and master control molding
EMAC (Ethernet MAC controller) and MDIO (physical layer equipment data transmit-receive management module) interface of block is connected, EMAC
For controlling main control module to the data packet stream of ethernet physical layer chip, MDIO is mainly responsible to be configured and monitors and EMAC phases
Ethernet physical layer chip even.Ethernet physical layer chip is connected by Ethernet transformer with extraneous Ethernet, is realized
Ethernet physical layer chip is isolated with extraneous.Noise collector unit has been laid in the left and right sides in compartment, and RS485 buses are used to pass
The inspection signal of making an uproar for sending noise collector unit to send, each noise collector unit of compartment both sides is responsible for the gap detection car in broadcast
Level of noise in railway carriage or compartment, the inspection signal that will make an uproar beams back main control module by RS485 buses, and the main control chip of main control module is responsible for meter
The noise average value that each noise collector unit is detected is calculated, the output gain of codec chip is adjusted according to average value size
Section, so as to reach the purpose for automatically controlling broadcast volume.In order to strengthen signal quality, the transceiver of RS485 buses uses optocoupler
Isolated with the external world.RS232 buses are mainly used in the debugging of unit, by RS232 buses come commissioning device unit
Each functional module, to verify whether each functional module is working properly.
The train voice amplifying unit method of operation based on ARM+FPGA frameworks is as follows：Main control module is complete after device power
Initialization, the configuration management of encoding and decoding amplification module and operation application program and AGC, amplitude limit limit frequency algorithm into system；Sound
Gigabit Ethernet of the frequency signal Jing Guo communication module enters in main control module, the double ARM kernels and FPGA of main control module
AGC, amplitude limit limit frequency algorithm be responsible for handling audio signal, after the completion of be forwarded to encoding and decoding by SPI, I2S interface and put
Big module, encoding and decoding submodule drives to being forwarded to power amplifier submodule, power amplifier submodule after audio signal decoding after amplifying to it
Loudspeaker is broadcasted, and detection sub-module is responsible for detecting electric current in broadcast.The gap noise collector unit of broadcast, which can be detected, makes an uproar
Value, RS485 Bus repeater of the inspection signal Jing Guo communication module that will make an uproar realizes Automatic control of sound volume to main control chip.Each function
Module coordination works, and constitutes complete voice amplifying unit.
Automatic volume regulation can be carried out the beneficial effects of the present invention are train voice amplifying unit first and automatic
Gain controls (AGC), so as to ensure that passenger can clearly hear Auto broadcast or artificial broadcast；Secondly, can encoding and decoding it is various
The audio signal of form, meets the demand of lifting tonequality；Again, high-low sound frequency signal branch is exported, and adds loudspeaker
Service life；Finally, the function with detection and backup, passes through magnetic induction measurement electric current device, two-way ethernet communication and sound
Frequency degradation function ensure that the stability of broadcast system.
Brief description of the drawings
Fig. 1 is the hardware block diagram of train voice amplifying unit of the present invention.
Fig. 2 is the main control module of train voice amplifying unit of the present invention.
Fig. 3 is the encoding and decoding amplification module of train voice amplifying unit of the present invention.
Fig. 4 is the communication module of train voice amplifying unit of the present invention.
Embodiment
Describe the embodiment of the present invention in detail below in conjunction with accompanying drawing and technical scheme.
Train voice amplifying unit based on ARM+FPGA frameworks includes main control module, encoding and decoding amplification module and communication
The part of module three, structure is as shown in Figure 1.Main control module is responsible for the initialization of system, the configuration management of encoding and decoding amplification module
And operation application program and AGC, amplitude limit limit frequency algorithm etc.；Communication module is responsible for receiving the audio signal sent on network with making an uproar
Examine signal；Encoding and decoding amplification module be responsible for audio signal is handled and amplified, detection sub-module then complete current detecting with
And audio degradation function.In addition, this equipment is powered using DC-DC modes, 24V DC voltages are converted into needed for related chip
Voltage is powered.
Main control module is made up of main control chip and its peripheral components, as shown in Figure 2.Main control chip selects ARM+FPGA framves
The chip of structure, the chip integrates FPGA with double ARM Cortex-A9 kernels, and it is entered by arm processor rather than FPGA
Row control.Designer can be programmed to arm processor, configure FPGA as needed, thus reduce design threshold and
Cycle, at the same in FPGA may be programmed realize AGC and limit frequency slicing algorithm, can be to the amplitude versus frequency characte of audio signal at
Reason.Main control chip includes a variety of Peripheral Interfaces：Including an addressing space 1GB, DDR3 Dram control interface is supported；One
Individual support Quad-SPI static memory control interface；Two SDIO interfaces with DMA；Two compatibility GMII/RGMII/
SGMII gigabit MAC interface；Two transmission rates are up to 1Mb/s High Speed UART interface, if peripheral hardware can excessively pass through FPGA
Carry out Interface Expanding.The two panels DDR3 memory chips that the present invention is used constitute 1GB memory headroom, and its bank address is BA
[0:2], row address is A [0:14], column address is A [0:9], data bit width is 16, for operating system and application program
Operation；There is the Flash chip of Quad-SPI interfaces to constitute 16MB memory space using two panels, for depositing
Bootloader files, two panels Flash chip collectively forms 8 digital independent interfaces, and reading speed contracts significantly up to 52MB/s
The short startup time of system；It is used for the storage of application program and audio file using iNAND chips, iNAND chips will be interior
Memory controller and NAND Flash are integrated, and master controller need to be only written and read to iNAND, and Memory Controller Hub is responsible for data
The work such as storage and interface protocol, so not only reduces the live load of main control chip and has saved system resource；CPLD
Chip is used for when FPGA starts, and FPGA sends a string of code streams to CPLD, CPLD and FPGA is performed same algorithm, CPLD is held
FPGA is given by operation result after row algorithm, the FPGA operation programs if CPLD is consistent with FPGA results are locked if inconsistent
FPGA, so as to ensure the security of algorithm in FPGA；Clock-reset chip is used to provide reliable clock and reset to master control
Signal.Main control chip gigabit MAC and FPGA extension gigabit MAC communication interface are all configured to RGMII interfaces, as with the mould that communicates
The audio signal transmission interface of block；Main control chip UART interface extends the RS232 of UART interface respectively with communication module with FPGA
It is connected with RS485 bus transceivers, for equipment debugging and inspection signal transmission of making an uproar；The I2S of FPGA extensions is used as master with SPI interface
Module and the audio signal transmission interface of encoding and decoding amplification module are controlled, I2C is used for the management and configuration of codec chip.Equipment electricity
Source use by 24V DC voltages by switching power source chip and peripheral circuit be converted into 1.0V, 1.2V, 1.5V, 1.8V, 2.5V,
2.8V and 3.3V mode is powered for related chip.
Encoding and decoding amplification module includes encoding and decoding submodule, power amplifier submodule and the part of detection sub-module three, such as Fig. 3 institutes
Show.Encoding and decoding submodule includes two-way encoding and decoding path, wherein all the way to damage encoding and decoding path, another road is lossless encoding/decoding
Path.The encode/decode audio signal that encoding and decoding path is responsible for the compressed formats such as MP3 is damaged, audio signal is entered by SPI interface
The serial data interface of codec chip, then passes to the DSP of codec chip, enters DAC by DSP forwardings, most passes through afterwards
Driver drives exports audio signal, and DAC is using advanced ∑-△ oversampling techniques, sample rate is adjustable and sampling resolution can
Up to 18.Lossless encoding/decoding path is responsible for the encode/decode audio signal of the unpacked formats such as PCM, WAV, and main control module passes through
It is managed for configuration I2C interfaces, and audio signal enters the audio serial interface of codec chip by I2S interfaces, passes through
DAC is forwarded to after the processing of codec chip, driver driving exports audio signal is eventually passed, in 8KHZ to 96KHZ frequency
In the range of rate, DAC supports 16,20,24 and 32 samplings.Codec chip all has the adjustable function of output gain and supported
Left and right acoustic channels are exported, and left and right acoustic channels connect different power amplifier chips respectively, it is possible to realize that the left and right sides is simultaneously in guest room
Different content is played, so as to reach stereosonic effect.According to the difference of audio format, main control module control two-way switch enters
The gating of row codec chip, encoding and decoding are carried out so as to realize to the audio signal of different-format.Audio after encoding and decoding
Signal is converted into low frequency and high-frequency audio path respectively through low pass and high-pass filter, so as to realize the low-and high-frequency of audio signal
The separation of component.Power amplifier submodule is made up of four railway digital power amplifier chips and corresponding low pass filter.Power amplifier it is worked
Cheng Wei：When inputting simulated audio signal, simulated audio signal is transformed into pulsewidth pair by comparator and PWM modulator first
The high-frequency PWM pulse signal of its amplitude is answered, through drive circuit driving high-power switch device work, low pass filter is eventually passed
Acoustic information in PWM waveform is restored, loudspeaker even load sounding is promoted.Detection sub-module is detected by induced field current
Device and analogue audio frequency path composition.Induced field current detector by the electric current of power amplifier output end by introducing hall device, suddenly
Current value is converted into corresponding voltage differential signal at devices use Hall effect by you, and corresponding voltage differential signal is reached into magnetic induction
The DSP of current detector, is forwarded to ADC after being converted to corresponding current value through DSP, ADC converts analog signals into data signal
Into main control module, so as to realize the detection of current value.Analogue audio frequency path is used to realize audio degradation function, because simulation
Signal has certain loss by long transmission line transmission, so transmitting terminal first boosts to it, is entered in receiving terminal by transformer
Row step-down, then audio signal is sent into the linear input of codec chip, can make input by hardware automatic gain control
Audio signal reach identical output amplitude, last audio signal promotes loudspeaker work after carrying out power amplification through power amplifier chips
Make.
Communication module is made up of two-way gigabit Ethernet, RS485 buses and RS232 buses, as shown in Figure 4.In order to full
The requirement of real-time of foot communication, the present invention is using two-way gigabit Ethernet transmission audio signal, wherein being located at unit all the way
Backboard, another road be located at unit panel, the gigabit ether that audio signal passes through unit backboard when normally using
Net enters main control module, and panel gigabit ethernet interface is used for the backup of communication network, when backboard gigabit Ethernet failure,
It can switch to panel gigabit Ethernet, it is ensured that the stability of broadcast system.The EMAC of two-way gigabit Ethernet and Ethernet thing
Communication between reason layer chip is all configured to RGMII interfaces, and it includes 12 signals such as data transmission, reception, clock, control
Line.MDIO includes MDCLK and DATA, respectively manages the clock line and data wire of data module.Main control chip is internally integrated
Meet the EMAC and MDIO of IEEE802.3 standards.EMAC is that a kind of efficient interface is provided between equipment and network, for reality
Existing MAC layer is controlled to the data packet stream of ethernet physical layer chip；MDIO using a kind of shared two-wire system bus go access and
Ethernet physical layer chip is controlled, it is main to be responsible for the ethernet physical layer chip that configuration and monitoring are connected with EMAC, including system
Priority of reset, interruption and system etc..Ethernet physical layer chip is connected by transformer with extraneous Ethernet, and Ethernet becomes
Depressor mainly plays signal transmission, impedance matching, waveform reparation, signal noise suppression and high-voltage isolating etc..RS485 buses
Transceiver is connected with the FPGA UART interfaces extended, and in order to strengthen communication quality, RS485 bus transceivers pass through with external equipment
Optocoupler is isolated.In order to exclude the interference of broadcast, each noise collector unit of compartment both sides is responsible for the gap inspection in broadcast
Inspection value of making an uproar in measuring car railway carriage or compartment, the inspection value that will make an uproar beams back main control module by RS485 buses, and the main control chip of main control module is responsible for
The noise average value that each noise collector unit is detected is calculated, according to output gain of the inspection average value size to codec chip of making an uproar
It is adjusted, so as to reach the purpose for automatically controlling broadcast volume.The transceiver of RS232 buses and the UART of main control module connect
Mouth is connected, and RS232 buses are mainly used in the debugging of unit, such as memory read-write, codec chip register configuration and work(
Enable control of chip etc. is put, is easy to verify whether each functional module is working properly.
Claims (1)
1. a kind of train voice amplifying unit based on ARM+FPGA frameworks, including three modules：Main control module, encoding and decoding are put
Big module and communication module, it is characterised in that：
Main control module is made up of main control chip and its peripheral components, initialization, the storage of audio and the place of main responsible system
Reason, AGC (automatic growth control) and amplitude limit limit the operation of frequency algorithm；Main control chip uses the processor of ARM+FPGA frameworks,
Inside comprising double ARM Cortex-A9 kernels, FPGA, Dram control interface, static memory control interface, SDIO interfaces,
Gigabit MAC interface and UART interface etc., wherein double ARM Cortex-A9 kernels are connected with FPGA by AXI high-speed buses, it is double
ARM Cortex-A9 kernels are mainly responsible for the processing of audio signal, and FPGA is responsible for the forwarding of audio signal, AGC algorithms and limit
Width limits the operation of frequency algorithm, and AGC algorithms are exported for the different amplitude audio signals of input to be converted into identical amplitude, are limited
Width limit frequency algorithm is used for the amplitude versus frequency characte for limiting audio signal；Peripheral components include DDR3 memory chips, Flash chip, iNAND
Chip, CPLD chips and clock-reset chip；Wherein, the Dram control interface phase of DDR3 memory chips and main control chip
Even, for running operating system and application program；Flash chip is connected with the static memory control interface of main control chip, is used for
Deposit bootloader files；INAND chips are connected as application program and audio file with the SDIO interfaces of main control chip
Storage chip；CPLD chips are used to ensure the security of various algorithms in FPGA；Clock-reset chip is used for main control chip
Reliable clock and reset signal are provided；The gigabit MAC interface of FPGA extensions and the ethernet physical layer all the way of communication module
Chip is connected, and is used as audio signal transmission path；The gigabit MAC interface of main control chip and another road Ethernet thing of communication module
Manage layer chip to be connected, be used as the backup of communication network；The UART interface of main control chip is with FPGA extensions UART interface respectively with leading to
RS232 with the RS485 bus transceivers of letter module are connected, for equipment debugging and inspection signal transmission of making an uproar；FPGA extended SPIs, I2S
And I2C interfaces are used for the transmission and configuration management of audio signal between main control module and encoding and decoding amplification module；
Encoding and decoding amplification module includes encoding and decoding submodule, power amplifier submodule and detection sub-module；Encoding and decoding submodule is by two-way
Codec chip, two-way switch and wave filter group into；It is lossless and damage two-way codec chip and realize various format audios letter
Number encoding and decoding, two-way switch control two-way codec chip gating, wave filter be responsible for the height frequency division in audio signal
Amount is separated；Encoding and decoding submodule separates output using left and right acoustic channels, and audio signal is real by different power amplifier chips
Different content is played in the existing guest room left and right sides, so as to reach stereosonic effect；Power amplifier submodule is by four railway digital power amplifier chips
And low pass filter composition；Four railway digital power amplifier chips constitute left and right acoustic channels low frequency channel and left and right acoustic channels high frequency channel, left
R channel high frequency channel and left and right acoustic channels low frequency channel correspond to corresponding middle/high frequency loudspeaker and woofer respectively, it is to avoid
Use full range speaker；Detection sub-module is made up of induced field current detector and analogue audio frequency path；Induced field current
Detector detects the electric current of digital power amplifier output channel by Hall effect, and speaker wire road network is judged according to the change of electric current
Short circuit with open circuit；Analogue audio frequency path is used to realize that audio degrades, i.e., receive analogue audio frequency path when communication network failure
The audio signal of transmission, maintains basic artificial broadcast capability, and codec chip is internally integrated hardware automatic gain control function, made
The audio signal of input reaches identical output amplitude, it is ensured that broadcast volume is not by interference from human factor；
Communication module is made up of two-way gigabit Ethernet, RS485 buses and RS232 buses, is mainly used in audio and inspection letter of making an uproar
Number transmission and unit debugging；Two-way gigabit Ethernet is used to transmit audio signal, wherein being located at unit all the way
Backboard, another road be located at unit panel, the backboard gigabit ether that audio signal passes through unit when normally using
Net enters main control module, and panel gigabit ethernet interface is used for the backup of communication network, when backboard gigabit Ethernet failure,
Switch to panel gigabit Ethernet, it is ensured that the stability of broadcast system；The EMAC of ethernet physical layer chip and main control module
(Ethernet MAC controller) is connected with MDIO (physical layer equipment data transmit-receive management module) interface, and EMAC is used to control
Main control module is to the data packet stream of ethernet physical layer chip, and MDIO is mainly responsible to configure and monitor the ether being connected with EMAC
Net physical chip；Ethernet physical layer chip is connected by Ethernet transformer with extraneous Ethernet, realizes Ethernet physics
Layer chip is isolated with extraneous；Noise collector unit is laid in the left and right sides in compartment, and RS485 buses are used to transmit noise collection list
The inspection signal of making an uproar that member is sent, each noise collector unit of compartment both sides is responsible for the noise in the gap detection compartment of broadcast
Value, the inspection value that will make an uproar beams back main control module by RS485 buses, and the main control chip of main control module is responsible for calculating each noise collection
The noise average value that unit is detected, the output gain of codec chip is adjusted according to average value size, so as to reach
Automatically control the purpose of broadcast volume；In order to strengthen signal quality, the transceivers of RS485 buses using optocoupler with it is extraneous carry out every
From；RS232 buses are mainly used in the debugging of unit, by RS232 buses come each functional module of commissioning device unit, with
Verify whether each functional module is working properly.
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Cited By (18)
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| CN108254757A (en) * | 2018-04-11 | 2018-07-06 | 大连理工大学 | A kind of speed measuring device based on double TOF sensors |
| CN108305631A (en) * | 2018-04-04 | 2018-07-20 | 西安合谱声学科技有限公司 | A kind of Acoustic treatment equipment based on multinuclear modularization framework |
| CN108667541A (en) * | 2018-04-11 | 2018-10-16 | 大连理工大学 | A kind of train digital broadcast controller based on HomePlug |
| CN109378009A (en) * | 2018-09-21 | 2019-02-22 | 中国航空无线电电子研究所 | Airborne alarm instantaneous speech power |
| CN109840233A (en) * | 2019-01-25 | 2019-06-04 | 上海创景信息科技有限公司 | 60X bus bridge system, method and medium based on FPGA |
| CN109963227A (en) * | 2017-12-25 | 2019-07-02 | 长城汽车股份有限公司 | A kind of horn control circuit and loudspeaker control method |
| CN110389919A (en) * | 2019-07-04 | 2019-10-29 | 苏州浪潮智能科技有限公司 | Asynchronous receiving-transmitting transmitter peripheral hardware and system based on RISC-V processor |
| CN110391941A (en) * | 2019-07-29 | 2019-10-29 | 深圳震有科技股份有限公司 | A kind of method, circuit board and the storage medium of circuit board sending and receiving data |
| CN110473558A (en) * | 2019-07-31 | 2019-11-19 | 深圳市长龙铁路电子工程有限公司 | A kind of real-time multi-functional codec of 450M locomotive station unit |
| CN110488694A (en) * | 2019-08-09 | 2019-11-22 | 大连理工大学 | A kind of sliding plug door of motor train unit control system based on SoC FPGA |
| CN110941862A (en) * | 2019-12-11 | 2020-03-31 | 博依特(广州)工业互联网有限公司 | Data isolation system based on FPGA + ARM |
| CN112559430A (en) * | 2020-12-24 | 2021-03-26 | 上海微波技术研究所（中国电子科技集团公司第五十研究所） | CPU and FPGA data interaction method and system suitable for narrow-band channel unit |
| CN112799886A (en) * | 2020-12-14 | 2021-05-14 | 惠州市博实结科技有限公司 | Online system and remote debugging method of vehicle-mounted video equipment |
| CN113075896A (en) * | 2021-04-01 | 2021-07-06 | 长春工业大学 | Industrial Ethernet controller based on FPGA |
| CN114121033A (en) * | 2022-01-27 | 2022-03-01 | 深圳市北海轨道交通技术有限公司 | Train broadcast voice enhancement method and system based on deep learning |
| CN114253344A (en) * | 2021-12-06 | 2022-03-29 | 广州芯德通信科技股份有限公司 | Method and system for improving PCM (pulse code modulation) gap signal noise of IAD (integrated access device) |
| CN114401418A (en) * | 2021-12-30 | 2022-04-26 | 北京北广科技股份有限公司 | Embedded audio and video server based on multiple ARM chip architectures |
| CN115243161A (en) * | 2022-07-13 | 2022-10-25 | 上海富芮坤微电子有限公司 | Audio output pin multiplexing circuit, device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109963227A (en) * | 2017-12-25 | 2019-07-02 | 长城汽车股份有限公司 | A kind of horn control circuit and loudspeaker control method |
| CN108305631A (en) * | 2018-04-04 | 2018-07-20 | 西安合谱声学科技有限公司 | A kind of Acoustic treatment equipment based on multinuclear modularization framework |
| CN108305631B (en) * | 2018-04-04 | 2023-09-05 | 西安合谱声学科技有限公司 | Acoustic processing equipment based on multi-core modularized framework |
| CN108254757A (en) * | 2018-04-11 | 2018-07-06 | 大连理工大学 | A kind of speed measuring device based on double TOF sensors |
| CN108667541A (en) * | 2018-04-11 | 2018-10-16 | 大连理工大学 | A kind of train digital broadcast controller based on HomePlug |
| CN109378009A (en) * | 2018-09-21 | 2019-02-22 | 中国航空无线电电子研究所 | Airborne alarm instantaneous speech power |
| CN109840233A (en) * | 2019-01-25 | 2019-06-04 | 上海创景信息科技有限公司 | 60X bus bridge system, method and medium based on FPGA |
| CN109840233B (en) * | 2019-01-25 | 2020-10-27 | 上海创景信息科技有限公司 | 60X bus bridging system, method and medium based on FPGA |
| CN110389919A (en) * | 2019-07-04 | 2019-10-29 | 苏州浪潮智能科技有限公司 | Asynchronous receiving-transmitting transmitter peripheral hardware and system based on RISC-V processor |
| CN110391941A (en) * | 2019-07-29 | 2019-10-29 | 深圳震有科技股份有限公司 | A kind of method, circuit board and the storage medium of circuit board sending and receiving data |
| CN110391941B (en) * | 2019-07-29 | 2022-04-19 | 深圳震有科技股份有限公司 | Method for receiving and transmitting data by circuit board, circuit board and storage medium |
| CN110473558A (en) * | 2019-07-31 | 2019-11-19 | 深圳市长龙铁路电子工程有限公司 | A kind of real-time multi-functional codec of 450M locomotive station unit |
| CN110473558B (en) * | 2019-07-31 | 2022-01-14 | 深圳市长龙铁路电子工程有限公司 | Real-time multifunctional coder-decoder of 450M locomotive radio station unit |
| CN110488694A (en) * | 2019-08-09 | 2019-11-22 | 大连理工大学 | A kind of sliding plug door of motor train unit control system based on SoC FPGA |
| CN110488694B (en) * | 2019-08-09 | 2021-05-07 | 大连理工大学 | EMUs stopper sliding door control system based on SoC FPGA |
| CN110941862A (en) * | 2019-12-11 | 2020-03-31 | 博依特(广州)工业互联网有限公司 | Data isolation system based on FPGA + ARM |
| CN112799886A (en) * | 2020-12-14 | 2021-05-14 | 惠州市博实结科技有限公司 | Online system and remote debugging method of vehicle-mounted video equipment |
| CN112799886B (en) * | 2020-12-14 | 2023-04-04 | 惠州市博实结科技有限公司 | Online system and remote debugging method of vehicle-mounted video equipment |
| CN112559430A (en) * | 2020-12-24 | 2021-03-26 | 上海微波技术研究所（中国电子科技集团公司第五十研究所） | CPU and FPGA data interaction method and system suitable for narrow-band channel unit |
| CN113075896A (en) * | 2021-04-01 | 2021-07-06 | 长春工业大学 | Industrial Ethernet controller based on FPGA |
| CN114253344A (en) * | 2021-12-06 | 2022-03-29 | 广州芯德通信科技股份有限公司 | Method and system for improving PCM (pulse code modulation) gap signal noise of IAD (integrated access device) |
| CN114401418A (en) * | 2021-12-30 | 2022-04-26 | 北京北广科技股份有限公司 | Embedded audio and video server based on multiple ARM chip architectures |
| CN114401418B (en) * | 2021-12-30 | 2023-09-12 | 北京北广科技股份有限公司 | Embedded audio and video server based on multiple ARM chip architectures |
| CN114121033A (en) * | 2022-01-27 | 2022-03-01 | 深圳市北海轨道交通技术有限公司 | Train broadcast voice enhancement method and system based on deep learning |
| CN115243161A (en) * | 2022-07-13 | 2022-10-25 | 上海富芮坤微电子有限公司 | Audio output pin multiplexing circuit, device and method |
| CN115243161B (en) * | 2022-07-13 | 2023-06-27 | 上海富芮坤微电子有限公司 | Audio output pin multiplexing circuit, device and method |
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