CN106935480B - Cleaning method implemented after chemical mechanical polishing of copper metal interconnection layer - Google Patents
Cleaning method implemented after chemical mechanical polishing of copper metal interconnection layer Download PDFInfo
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- CN106935480B CN106935480B CN201511018593.5A CN201511018593A CN106935480B CN 106935480 B CN106935480 B CN 106935480B CN 201511018593 A CN201511018593 A CN 201511018593A CN 106935480 B CN106935480 B CN 106935480B
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
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Abstract
The invention provides a cleaning method implemented after chemical mechanical polishing of a copper metal interconnection layer, which comprises the following steps: sending the wafer with the copper interconnection metal layer subjected to the chemical mechanical polishing into a cleaning operation chamber, and washing with deionized water; immersing the wafer into a container containing heated deionized water for 80-90 seconds; performing a first brushing session, the first brushing session comprising three steps performed in sequence: firstly, brushing the wafer with deionized water, secondly, adsorbing the wafer by using a wafer carrying head, and grinding the front surface of the wafer by using a miniature grinding pad, and thirdly, brushing the wafer with citric acid and deionized water; performing a second brushing process, and brushing the wafer by using citric acid and deionized water; and drying the wafer. According to the invention, the chemical substance residue after grinding can be obviously reduced, and the corrosion phenomenon can be inhibited.
Description
Technical Field
The invention relates to a semiconductor manufacturing process, in particular to a cleaning method implemented after chemical mechanical polishing of a copper metal interconnection layer.
Background
In back end of line (BEOL) of semiconductor devices, a dual damascene process is typically used to form a copper interconnect structure for filling a copper interconnect layer. After the copper metal interconnection structure is filled with the copper metal interconnection layer by adopting an electroplating process, chemical mechanical polishing is needed to completely remove copper outside the copper metal interconnection structure. In the process of chemical mechanical polishing, the polishing slurry used belongs to a chemical substance, and under the action of an external force, the defects in the polished copper metal interconnection layer need to be strictly controlled and avoided, so that the cleaning of the wafer after polishing is very important. However, the conventional cleaning process cannot completely remove defects in the copper metal interconnection layer, and also causes chemical residues, which may cause the copper diffusion to be accelerated, resulting in the degradation of device performance.
Therefore, a method is needed to solve the above problems.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a cleaning method implemented after chemical mechanical polishing of a copper metal interconnection layer, which comprises the following steps: sending the wafer with the copper interconnection metal layer subjected to the chemical mechanical polishing into a cleaning operation chamber, and washing with deionized water; immersing the wafer into a container containing heated deionized water for 80-90 seconds; performing a first brushing session, the first brushing session comprising three steps performed in sequence: firstly, brushing the wafer with deionized water, secondly, adsorbing the wafer by using a wafer carrying head, and grinding the front surface of the wafer by using a miniature grinding pad, and thirdly, brushing the wafer with citric acid and deionized water; performing a second brushing process, and brushing the wafer by using citric acid and deionized water; and drying the wafer.
In one example, the duration of the DI water rinse performed after the wafer is transferred into the cleaning chamber is 80-90 seconds.
In one example, the duration of the chemical mechanical polishing is 70 seconds to 80 seconds.
In one example, the first step of the first brushing session has a duration of 10 seconds to 15 seconds.
In one example, the duration of the micro polishing pad polishing is 20 seconds to 25 seconds, the chemical components of the polishing liquid used for the micro polishing pad polishing are additive, silicon dioxide and water, and the flow rate of the polishing liquid is 200 ml/min to 220 ml/min.
In one example, the micro polishing pad rotates at a rate of 25 rpm to 30 rpm, the micro polishing pad rotates counterclockwise, the wafer carrier head rotates clockwise, and the wafer carrier head rotates at a rate of 30 rpm to 40 rpm.
In one example, the micro polishing pad is made of polyurethane, the diameter of the micro polishing pad is 205 mm-210 mm, circular grooves are densely distributed on the micro polishing pad, the diameter of each circular groove is 3.5 mm-3.8 mm, and the depth of each circular groove is 50 micrometers-80 micrometers.
In one example, the second and third steps of the first brushing cycle are repeated.
In one example, the citric acid used in the first brushing session is 25-30% by volume, and the duration of the third step of the first brushing session is 35-40 seconds.
In one example, the citric acid used in the second brushing process is 25-30% by volume, and the duration of the second brushing process is 80-90 seconds
According to the invention, the chemical substance residue after grinding can be obviously reduced, and the corrosion phenomenon can be inhibited.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1A is a schematic cross-sectional view of a chemical mechanical polishing apparatus used in performing the cleaning method of the present invention;
FIG. 1B is a schematic view of a micro polishing pad in the chemical mechanical polishing apparatus shown in FIG. 1A;
fig. 2 is a flow chart of steps performed in sequence by a method according to an exemplary embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
[ exemplary embodiments ]
Referring to fig. 2, a flow chart illustrating steps performed in sequence by a method according to an exemplary embodiment of the present invention is shown for schematically illustrating the flow of a manufacturing process.
First, in step 201, a wafer with a chemical mechanical polishing copper interconnect metal layer is sent to a cleaning operation chamber and rinsed with deionized water for 80 seconds to 90 seconds.
The chemical components of the polishing liquid used for chemically and mechanically polishing the copper interconnection metal layer are additive, silicon dioxide and water, wherein the weight percentage of the additive is less than 1.0 percent, the weight percentage of the silicon dioxide is 1.0 to 10.0 percent, and the weight percentage of the water is 89.0 to 98.0 percent. The duration of the chemical mechanical polishing is 70 seconds to 80 seconds.
The wafer before the chemical mechanical polishing comprises: a semiconductor substrate in which an isolation structure and various well structures are formed, the isolation structure being, for example, a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure; a front-end device formed on the semiconductor substrate, wherein the front-end device refers to a device formed before a back-end process of the semiconductor device, and a specific structure of the front-end device is not limited herein; an etching stop layer, a low-k dielectric layer, a buffer layer and a hard mask layer are formed on the semiconductor substrate from bottom to top, the material of the etching stop layer is preferably SiCN, SiC, SiN or BN, and the etching stop layer can be used as an etching stop layer for subsequently etching the low-k dielectric layer to form an upper copper metal interconnection structure and simultaneously can prevent the lower copper metal interconnection line from being etchedCopper is diffused into the overlying dielectric layer (e.g., low-k dielectric layer), and the material of the low-k dielectric layer may be selected from materials with low-k value (dielectric constant less than 4.0) commonly used in the art, including but not limited to, silicate compounds (HSQ) with k value of 2.6-2.9, HOSP with k value of 2.8
TM(Low dielectric constant material based on a mixture of organic and silicon oxides manufactured by Honeywell Corp.) and SiLK with a k value of 2.65
TM(a low dielectric constant material manufactured by Dow Chemical company), etc., the buffer layer may include an OMCTS (octamethylcyclotetrasiloxane) layer and a TEOS (tetraethylorthosilicate) layer stacked from bottom to top, the OMCTS layer serves as a transition material layer between the low-k dielectric material and the TEOS to increase an adhesion therebetween, the TEOS layer serves to prevent a mechanical stress from damaging a porous structure of the low-k dielectric material when subsequently grinding the filled copper interconnection metal, the hard mask layer may include a metal hard mask layer and an oxide hard mask layer stacked from bottom to top, the double-layered hard mask layer structure may ensure a double patterning or multiple patterning process accuracy, ensure a depth of all patterns to be formed in the hard mask layer and a uniformity of a sidewall profile, i.e., patterns having different feature sizes are first formed in the oxide hard mask layer, etching the metal hard mask layer by taking the oxide hard mask layer as a mask to prepare a pattern required to be formed in the hard mask layer, wherein the metal hard mask layer is made of Ti, TiN, BN, AlN, CuN or any combination thereof, and preferably TiN; the oxide hard mask layer is made of SiO
2SiON, and the like, and it is required to have a better etching selection ratio with respect to the constituent material of the metal hard mask layer; before forming the copper metal interconnection layer, a copper metal diffusion barrier layer and a copper metal seed layer are required to be sequentially formed on the bottom and the side wall of a copper metal interconnection structure which is formed in the low-k dielectric layer and used for filling the copper metal interconnection layer, wherein the copper metal diffusion barrier layer can prevent copper in the copper metal interconnection layer from diffusing into the low-k dielectric layer, the copper metal seed layer can enhance the adhesion between the copper metal interconnection layer and the copper metal diffusion barrier layer, and the copper metal diffusion barrier layer and the copper metal seed are formedThe layers may be formed using any suitable process technique known to those skilled in the art, such as physical vapor deposition to form a copper metal diffusion barrier layer, sputtering or chemical vapor deposition to form a copper metal seed layer, the material of the copper metal diffusion barrier layer being a metal, metal nitride or a combination thereof, such as a combination of Ta and TaN or a combination of Ti and TiN.
Next, in step 202, the wafer is immersed in a heated deionized water container for 80 seconds to 90 seconds. As an example, the temperature of the deionized water after temperature rise is 45-65 ℃.
Next, in step 203, a first brushing session is performed, which includes three steps performed in sequence: firstly, brushing the wafer for 10-15 seconds by using deionized water; second, as shown in fig. 1A, a wafer carrier head 101 is used to adsorb the wafer 100, the front surface of the wafer 100 is polished by a micro polishing pad 104 for 20 seconds to 25 seconds, the polishing slurry flows out from a nozzle 107 at a flow rate of 200 ml/min to 220 ml/min, the chemical components of the polishing slurry are additive, silicon dioxide and water, the additive is less than 1.0 wt%, the silicon dioxide is 1.0 wt% to 10.0 wt%, the water is 89.0 wt% to 98.0 wt%, the contact pressure between the front surface of the wafer 100 and the micro polishing pad 104 is 5.0 lbs to 5.5 lbs, the rotation rate of the micro polishing pad 104 is 25 rpm to 30 rpm, the rotation direction of the micro polishing pad 104 is counterclockwise rotation, the micro polishing pad 104 is fixed on a polishing pad support table 103, the polishing pad support table 103 is connected to a driving motor 105 fixed on a support plate 102 through a rotating shaft 106, as shown in fig. 1B, the material of the micro polishing pad 104 is polyurethane, the diameter of the micro polishing pad 104 is 205 mm-210 mm, the polishing pad 104 is densely covered with the circular grooves 108, the diameter of the circular grooves 108 is 3.5 mm-3.8 mm, the depth of the circular grooves 108 is 50 μm-80 μm, the wafer carrier head 101 generates a certain vacuum degree through the air pressure chamber therein to adsorb the wafer 100, the vacuum degree between the wafer 100 and the film fixed to the wafer carrier head 101 is 1.2 lb-3.2 lb, the rotation direction of the wafer carrier head 101 is clockwise rotation, and the rotation rate is 30 rpm-40 rpm; and thirdly, brushing the wafer for 35-40 seconds by using 25-30% by volume of citric acid and deionized water. The second and third steps may be repeatedly performed in order to sufficiently remove defects and residual chemicals.
Next, in step 204, a second brushing process is performed to brush the wafer with 25% -30% citric acid and deionized water by volume for 80-90 seconds.
Next, in step 205, the wafer is dried, which may be, for example, dried in a wafer spin dryer. Then, the wafer is sent to the operation unit of the next process.
To this end, the process steps performed according to the method of the exemplary embodiment of the present invention are completed. According to the invention, by performing the first brushing process, namely brushing the wafer 100 with deionized water, polishing the front surface of the wafer 100 with the micro-polishing pad 104, and brushing the wafer 100 with citric acid and deionized water in a volume ratio of 25-30%, the chemical substance residue after polishing, especially the chemical substance residue in the defects of the copper metal interconnection layer, can be significantly reduced, and the occurrence of corrosion phenomenon can be inhibited.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A cleaning method implemented after chemical mechanical polishing of a copper metal interconnection layer comprises the following steps:
sending the wafer with the copper interconnection metal layer subjected to the chemical mechanical polishing into a cleaning operation chamber, and washing with deionized water;
immersing the wafer into a container containing heated deionized water for 80-90 seconds;
performing a first brushing session, the first brushing session comprising three steps performed in sequence: firstly, brushing the wafer with deionized water, secondly, adsorbing the wafer by using a wafer carrying head, and grinding the front surface of the wafer by using a miniature grinding pad, and thirdly, brushing the wafer with citric acid and deionized water;
performing a second brushing process, and brushing the wafer by using citric acid and deionized water;
drying the wafer; the chemical components of the grinding liquid used for grinding the micro grinding pad are additive, silicon dioxide and water, wherein the weight percentage of the additive is less than 1.0%, the weight percentage of the silicon dioxide is 1.0-10.0%, and the weight percentage of the water is 89.0-98.0%.
2. The method of claim 1, wherein the duration of the DI water rinse performed after the wafer is transferred into the cleaning chamber is 80-90 seconds.
3. The method of claim 1, wherein the duration of the chemical mechanical polishing is 70 seconds to 80 seconds.
4. The method of claim 1, wherein the duration of the first step of the first brushing session is between 10 seconds and 15 seconds.
5. The method of claim 1, wherein the duration of the micro polishing pad polishing is 20 seconds to 25 seconds, and the flow rate of the polishing slurry is 200 ml/min to 220 ml/min.
6. The method of claim 1, wherein the micro polishing pad rotates at a rate of 25 rpm to 30 rpm, the micro polishing pad rotates counter-clockwise, the wafer carrier head rotates clockwise, and the micro polishing pad rotates at a rate of 30 rpm to 40 rpm.
7. The method of claim 1, wherein the micro polishing pad is made of polyurethane, the micro polishing pad has a diameter of 205 mm to 210 mm, the micro polishing pad has a dense circular groove, the circular groove has a diameter of 3.5 mm to 3.8 mm, and the depth of the circular groove is 50 μm to 80 μm.
8. The method of claim 1, wherein the second and third steps of the first brushing cycle are repeated.
9. The method according to claim 1, wherein the citric acid is used in an amount of 25 to 30% by volume during the first brushing session, and the duration of the third step of the first brushing session is 35 to 40 seconds.
10. The method according to claim 1, wherein the citric acid is used in an amount of 25-30% by volume during the second brushing session, and the duration of the second brushing session is 80-90 seconds.
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| CN111900200A (en) * | 2020-06-24 | 2020-11-06 | 西安交通大学 | Diamond-based gallium nitride composite wafer and bonding preparation method thereof |
| CN111834259A (en) * | 2020-07-17 | 2020-10-27 | 中国科学院微电子研究所 | Cleaning assembly |
| CN114473845A (en) * | 2020-11-11 | 2022-05-13 | 中国科学院微电子研究所 | Cleaning device |
| CN114887976B (en) * | 2022-05-25 | 2024-01-23 | 宁波芯丰精密科技有限公司 | Cleaning device |
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| US6479443B1 (en) * | 1997-10-21 | 2002-11-12 | Lam Research Corporation | Cleaning solution and method for cleaning semiconductor substrates after polishing of copper film |
| US6303551B1 (en) * | 1997-10-21 | 2001-10-16 | Lam Research Corporation | Cleaning solution and method for cleaning semiconductor substrates after polishing of cooper film |
| US6946397B2 (en) * | 2003-11-17 | 2005-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chemical mechanical polishing process with reduced defects in a copper process |
| CN101752206B (en) * | 2008-12-01 | 2011-09-07 | 中芯国际集成电路制造(上海)有限公司 | Method for improving grinding particle residue |
| CN101908465A (en) * | 2009-06-04 | 2010-12-08 | 中芯国际集成电路制造(上海)有限公司 | Method for removing residues after chemical mechanical polishing |
| CN102810459B (en) * | 2011-06-03 | 2015-04-08 | 中国科学院微电子研究所 | Method for cleaning wafer after chemical mechanical planarization |
| CN103035504B (en) * | 2011-10-09 | 2016-07-06 | 中芯国际集成电路制造(北京)有限公司 | Cmp method and chemical-mechanical polisher |
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