CN106933766B - bus control implementation method - Google Patents
bus control implementation method Download PDFInfo
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- CN106933766B CN106933766B CN201511013476.XA CN201511013476A CN106933766B CN 106933766 B CN106933766 B CN 106933766B CN 201511013476 A CN201511013476 A CN 201511013476A CN 106933766 B CN106933766 B CN 106933766B
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000001914 filtration Methods 0.000 claims abstract description 14
- 230000000630 rising effect Effects 0.000 claims description 5
- 238000001514 detection method Methods 0.000 abstract description 4
- 239000000779 smoke Substances 0.000 abstract description 4
- 230000006855 networking Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Small-Scale Networks (AREA)
- Dc Digital Transmission (AREA)
Abstract
The invention relates to the field of networking type smoke detection, in particular to a bus control implementation method, which comprises the following steps: judging whether the bus protocol is two-level or three-level; configuring related parameters; opening an enabling end of the comparator; comparing the bus voltage to a threshold voltage; judging whether the receiving mode is an up mode or a down mode; performing burr filtering treatment; and finally, the bus communication module carries out communication processing. The invention can not only solve the two-level bus protocol, but also can solve the three-level bus protocol, and can filter burrs with different widths.
Description
Technical Field
The invention relates to the field of networking type smoke detection, in particular to a bus control implementation method in the field of smoke detection.
Background
In the field of networked smoke detection, the master controller is typically connected to each of the slave detectors via a two-wire bus. The two-wire bus supports a bus protocol of two or three level states. The bus protocol with two levels only has two coding states of 0 and 1 when sending codes, and different codes can be realized by matching with the length of time, while the bus protocol with three levels can have three coding states of 0, 1 and 2 when sending codes, and more codes can be realized without matching with the length of time. The same coding is realized in a period of time, the bus protocol with three levels has shorter code length than the bus protocol with two levels, and the coding efficiency is higher, so that when the system is realized, the bus protocol with three levels can greatly shorten the polling period of the host computer to the slave computer. The existing bus control implementation method can only process two levels of bus protocols, and communication is difficult to realize for three levels of bus protocols.
As shown in fig. 1, it is a schematic diagram of a conventional bus control implementation method, which only supports a bus protocol with two level states, a host computer performs code transmission communication on a slave computer by changing a bus voltage, compares the bus voltage (abbreviated as VLN 24) with a threshold voltage (abbreviated as VTH) by a comparator (abbreviated as CMP), the threshold Voltage (VTH) is configured by receiving a threshold voltage register, the threshold Voltage (VTH) is defined as an absolute value, if VLN24> VTH, a compared code transmission output signal (abbreviated as rxd signal) of the comparator is at a high level, otherwise, the compared rxd signal is at a low level, and the compared rxd signal is taken as an input signal and directly enters a bus communication module for communication.
The existing bus control implementation method can only process bus protocols with two levels, and has the following problems: firstly, when the host computer adopts different code sending modes to send codes, the existing bus control implementation method adopts an up receiving mode and a down receiving mode to respectively process, thereby wasting the subsequent hardware overhead; secondly, the interference of noise to communication cannot be eliminated in bus control, which is a problem, the existing method is to provide analog filtering, and a capacitor is externally connected to an LN24CAP port, but the method cannot filter burrs caused by transient bus voltage fluctuation (error code sending), bus voltage reduction caused by code returning current in a sending mode, and the like.
Disclosure of Invention
The invention aims to solve the problems in the prior art, and provides a bus control implementation method which is suitable for bus protocol communication with two or three level states on a two-wire bus, can filter burrs with different widths on the bus and has an adjustable burr width range.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a bus control realizing method is based on a digital processing module, a receiving mode selection Register (RXMMODE), a bus protocol level state selection Register (RXVTH), two comparators (CMP 1 and CMP 2), receiving threshold voltage registers respectively corresponding to the two comparators and a bus communication module in a bus circuit, and is characterized by comprising the following steps: (1) judging whether a bus protocol of the host side for sending codes is two levels or three levels; (2) if the two levels are available, configuring a bus protocol level state selection signal (RXVTH) to be 1 through a bus protocol level state selection register, namely RXVTH = 1; if the voltage levels are three levels, configuring a bus protocol level state selection signal (RXVTH) to be 0 through a bus protocol level state selection register, namely RXVTH = 0; (3) if the two levels exist, opening the enabling end of any path of comparator; if the voltage levels are three, enabling ends of the two paths of comparators are opened; (4) each comparator compares the bus voltage (VLN 24) with the threshold Voltage (VTH) set by the receiving threshold voltage register to obtain a code sending signal (rxd) of the comparator, and transmits the code sending signal to the digital part of the bus communication module; (5) judging a receiving mode of the receiving mode selection Register (RXMODE), wherein the receiving mode selection register defines two receiving modes, namely a down mode and an up mode, the down mode refers to a high level when a bus normally works and a low level when a code is sent; the up mode refers to the low level when the bus works normally and the high level when the bus sends codes; if 1 (i.e., high level) is set in the reception mode selection Register (RXMODE), the reception mode is the up mode; if 0 (i.e., low level) is set in the mode selection Register (RXMODE), the reception mode is down mode; (6) carrying out signal selection processing on a receiving mode, and if the receiving mode is the up mode, carrying out subsequent filtering processing on a code sending signal (rxd) of the comparator in the step (4) after negating the code sending signal (rxd); if the signal is in the down mode, directly carrying out subsequent filtering processing on the code sending signal of the comparator in the step (4) through a digital processing module; (7) and the filtered code sending signal is subjected to communication processing through a bus communication module.
The control method for opening the enabling ends of the two comparators comprises the following steps: the two comparator enabling ends are controlled by two gating structures, each gating structure is formed by connecting two selectors in series and is divided into a front-end selector and a rear-end selector, the input of the front-end selector is a high level (namely 1), a low level (namely 0) and an output selection signal (RXD _ SEL) of the results of the two comparators, and the output selection signal (RXD _ SEL) of the results of the two comparators refers to one of code sending signals RXD of the two comparators; the input of the back-end selector is low level (namely 0), the output of the front-end selector and the value of RXVTH set in the step (1); the output of the back-end selector corresponds to the enable signal for turning on the comparator and sets its output enable signal to be active low (i.e., 0).
The digital processing module comprises a digital filter, an 8-bit counter and a digital filtering register, and the step (6) is realized by the following steps: setting the width (abbreviated as M) of the burr to be filtered through a digital filter register, starting counting from 0 by a counter at the initial edge of the code sending signal obtained in the step (4), resetting the counter when the edge is detected (whether the edge is a rising edge or a falling edge), and restarting counting; comparing the count value (K for short) of the counter with the burr width, and when K is not equal to M, keeping the state of the signal with the noise filtered at the last moment; and when K = M, inputting the filtered signal into the bus communication module for further processing, and closing the digital filtering function. The digital processing module can filter burrs with different widths, and can also close the digital filtering function by configuring a digital filtering register as 0.
The invention has the beneficial effects that: the invention can process the bus signals of which the bus protocol is in two level states, can also process the bus signals of which the bus protocol is in three level states, and is completely suitable for the communication of a two-wire system bus; in the invention, the code sending signals processed by the back end are signals in a down mode no matter what mode the bus receives, thereby simplifying subsequent processing procedures and reducing additional data processing overhead; the digital filter can filter the burrs which cannot be filtered by analog filtering such as large bus voltage fluctuation (error code sending) or bus voltage pulled down by code returning current and the like, the width of the burrs is adjustable, the digital filter has strong configuration flexibility, and the obtained code sending signal is purer.
Drawings
FIG. 1 is a schematic diagram of one embodiment of the present invention;
Fig. 2 is a schematic diagram of a control structure for turning on the enable terminal of the two-way comparator in fig. 1.
Detailed Description
The following detailed description of the preferred embodiments of the present invention will be made with reference to the accompanying drawings.
Example (b): when the host machine sends code communication to the slave machine by changing the bus voltage, different receiving modes can be set through a receiving mode selection Register (RXMMODE), and can be defined as a down mode and an up mode, wherein the down mode refers to that the bus is at a high level when normally working, and is at a low level when sending code, and the bus pulse time is the time from the bus falling edge to the rising edge; the up mode refers to the bus being at low level when working normally, and high level when sending code, and the bus pulse time is the time from the rising edge to the falling edge of the bus, and can be expressed as: RXMODE =0, down mode; RXMODE =1, up mode.
One implementation of the bus control circuit of the present invention is shown in fig. 1, in which fig. 1 has two comparators (CMP 1 and CMP 2), the bus voltage (VLN 24) is compared with two threshold voltages (VTH 1 and VTH 2), and the threshold points of the two comparators can be set by the microcontroller reading the values of the registers. The enable signals (CMP 1_ EN and CMP2_ EN) of the two comparators can be controlled by the selector structure with the output select signals (RXD _ SEL) and RXVTH of the two comparator results as strobe control signals, and the implementation method is shown in fig. 2. A bus protocol level state selection Register (RXVTH) can set the level number of a bus protocol, wherein RXVTH =0, and a bus in the bus protocol has only two levels, namely a high level and a low level; RXVTH =1, there are three level states on the bus protocol. The RXD _ SEL can control the two levels of the bus to select CMP1_ EN or CMP2_ EN to be opened, and code sending signals after being compared by the comparator are RXD1 and RXD2 respectively.
The receiving modes of different hosts may be different, and the algorithms for determining the initial edge and the ending edge of the code sending signals of the up receiving mode and the down receiving mode are different at the bus communication module, the inverter in fig. 1 inverts rxd1/rxd2 signals, rxd1/rxd2, (-rxd 1)/(-rxd 2) are respectively used as two input signals of the selector (MUX), wherein the selection is performed by an RXMODE signal, RXMODE =0 (down mode) selects and outputs rxd1/rxd2, RXMODE =1 (up mode) selects and outputs (— rxd 1)/(-rxd 2), and this implementation method enables the code sending signals rxd1_ in/rxd2_ in which are subsequently processed to be down mode.
rxd1_ in/rxd2_ in is filtered by a digital filter (D-rxfilter), the width (M) of the glitch to be filtered is set by configuring a digital filter register, the counter starts counting from 0 at the beginning of the rxd1_ in/rxd2_ in, the counter resets when an edge (either rising or falling) is detected, and counting is restarted; comparing the count value (K) of the counter with the burr width (M), and when K is not equal to M, rxd1_ filt/rxd2_ filt keeps the state of the previous moment; when K = M, rxd1_ filt/rxd2_ filt is equal to rxd1_ in/rxd2_ in, and the filtered signal rxd1_ filt/rxd2_ filt is input into the bus communication module for further processing. The digital filtering can filter out glitches of different widths, and the register can be configured to be 0 to turn off the digital filtering function.
The enable terminal in the present invention refers to a port that enables or disables the integrated circuit.
The circuit of the invention is provided with two comparators, no matter the bus code sending mode is the up mode or the down mode, the code sending signal after processing is the down mode by adding a phase inverter and a selector, the code sending signal can filter burrs through a digital filter, the width of the burrs can be configured to different widths through a digital filter register, and simultaneously, the register can be configured to be 0 to close the digital filter function.
Claims (4)
1. a bus control realizing method is based on a digital processing module, a receiving mode selection register, a bus protocol level state selection register, two comparators respectively corresponding receiving threshold voltage registers and a bus communication module in a bus circuit, and is characterized by comprising the following steps:
(1) judging whether a bus protocol of the host side for sending codes is two levels or three levels;
(2) If the bus protocol level state selection signal is 1, the bus protocol level state selection signal is configured through a bus protocol level state selection register; if the bus protocol level state selection signal is three levels, configuring a bus protocol level state selection signal 0 through a bus protocol level state selection register;
(3) if the two levels exist, opening the enabling end of any path of comparator; if the voltage levels are three, enabling ends of the two paths of comparators are opened;
(4) each path of comparator compares the bus voltage with the threshold voltage set by the receiving threshold voltage register to obtain a code sending signal of the comparator, and transmits the code sending signal to the digital part of the bus communication module;
(5) Judging a receiving mode of the receiving mode selection register, wherein the receiving mode selection register defines two receiving modes, namely a down mode and an up mode, the down mode refers to that the bus is at a high level when normally working and at a low level when sending codes; the up mode refers to the low level when the bus works normally and the high level when the bus sends codes; if the high level is set in the reception mode selection register, the reception mode is the up mode; if the low level is set in the mode selection register, the reception mode is a down mode;
(6) Carrying out signal selection processing on a receiving mode, and if the receiving mode is the up mode, carrying out subsequent filtering processing on a code sending signal of the comparator in the step (4) through a digital processing module after negation; if the signal is in the down mode, directly carrying out subsequent filtering processing on the code sending signal of the comparator in the step (4) through a digital processing module;
(7) And the filtered code sending signal is subjected to communication processing through a bus communication module.
2. the bus control implementation method according to claim 1, wherein the control method for turning on the two comparator enable terminals is as follows: the two paths of comparator enable ends are controlled by two paths of gating structures, each path of gating structure is formed by connecting two selectors in series and is divided into a front-end selector and a rear-end selector, the input of the front-end selector is a high level, a low level and an output selection signal of a result of the two comparators, and the output selection signal of the result of the two comparators is one of code sending signals of the two comparators; the input of the rear end selector is low level, the output of the front end selector and the bus protocol level state selection signal set in the step (1); the output of the back-end selector is correspondingly used as an enable end signal of the open comparator, and the output enable end signal is set to be effective at a low level.
3. The method of claim 1, wherein the digital processing module in step (6) comprises a digital filter, an 8-bit counter and a digital filter register, and step (6) is implemented as follows: setting the width of the burr to be filtered through a digital filter register, starting counting from 0 by a counter at the initial edge of the code sending signal obtained in the step (4), detecting a rising edge or a falling edge, resetting the counter, and restarting counting; comparing the count value of the counter with the width of the burr, and when the count value is not equal to the width of the burr, keeping the state of the signal with the noise filtered at the previous moment; when the counting value is equal to the width of the burr, the filtered signal is input into the bus communication module for further processing, and the digital filtering function is closed.
4. the bus control implementation of claim 3, wherein the digital filter register is configured to turn off a digital filter function by configuring digital filter register 0.
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| CN201511013476.XA CN106933766B (en) | 2015-12-31 | 2015-12-31 | bus control implementation method |
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| CN201511013476.XA CN106933766B (en) | 2015-12-31 | 2015-12-31 | bus control implementation method |
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| CN106933766B true CN106933766B (en) | 2019-12-06 |
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| CN111385172B (en) * | 2018-12-27 | 2021-11-26 | 杭州萤石软件有限公司 | Control system, control method and storage medium based on bus |
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| CN1434945A (en) * | 2000-06-02 | 2003-08-06 | 汤姆森特许公司 | Bus operation with integrated circuits in unpowered state |
| CN201917898U (en) * | 2011-01-20 | 2011-08-03 | 电子科技大学 | Inter-integrated circuit (I2C) bus interface circuit module |
| CN203608227U (en) * | 2013-11-07 | 2014-05-21 | 北京机械设备研究所 | Bidirectional buffering 1553B/CAN bus protocol converter |
| CN103955419A (en) * | 2014-04-28 | 2014-07-30 | 电子科技大学 | Logic analyzer with serial bus protocol on-line real-time detection analysis function |
| CN204576502U (en) * | 2015-04-13 | 2015-08-19 | 无锡新硅微电子有限公司 | Be applied to the dynamic threshold comparator circuit of M-BUS interface communication |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8374925B2 (en) * | 2005-04-29 | 2013-02-12 | Abbott Diabetes Care Inc. | Method and system for monitoring consumable item usage and providing replenishment thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1434945A (en) * | 2000-06-02 | 2003-08-06 | 汤姆森特许公司 | Bus operation with integrated circuits in unpowered state |
| CN201917898U (en) * | 2011-01-20 | 2011-08-03 | 电子科技大学 | Inter-integrated circuit (I2C) bus interface circuit module |
| CN203608227U (en) * | 2013-11-07 | 2014-05-21 | 北京机械设备研究所 | Bidirectional buffering 1553B/CAN bus protocol converter |
| CN103955419A (en) * | 2014-04-28 | 2014-07-30 | 电子科技大学 | Logic analyzer with serial bus protocol on-line real-time detection analysis function |
| CN204576502U (en) * | 2015-04-13 | 2015-08-19 | 无锡新硅微电子有限公司 | Be applied to the dynamic threshold comparator circuit of M-BUS interface communication |
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Address after: 214135 -6, Linghu Avenue, Wuxi Taihu international science and Technology Park, Wuxi, Jiangsu, China, 180 Patentee after: China Resources micro integrated circuit (Wuxi) Co.,Ltd. Address before: No.180-22, Linghu Avenue, Taihu International Science and Technology Park, Wuxi, Jiangsu, 214135 Patentee before: WUXI CHINA RESOURCES SEMICO Co.,Ltd. |
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Denomination of invention: A Bus Control Implementation Method Effective date of registration: 20231008 Granted publication date: 20191206 Pledgee: Bank of China Limited Wuxi Branch Pledgor: China Resources micro integrated circuit (Wuxi) Co.,Ltd. Registration number: Y2023980060027 |